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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp @ 101

Last change on this file since 101 was 101, checked in by rosiere, 15 years ago
1) Add soc test 2) fix bug (Pc management, Decod and execute, Update prediction ...)
Property svn:keywords set to `Id`
File size: 17.1 KB

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1	/*
2	* $Id: test.cpp 101 2009-01-15 17:19:08Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9
10	#define NB_ITERATION 1024
11	#define CYCLE_MAX (128*NB_ITERATION)
12
13	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/include/test.h"
14	#include "Common/include/Test.h"
15	#include "Behavioural/include/Allocation.h"
16
17	void test (string name,
18	morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param)
19	{
20	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
21
22	#ifdef STATISTICS
23	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
24	#endif
25
26	Tusage_t _usage = USE_ALL;
27
28	// _usage = usage_unset(_usage,USE_SYSTEMC );
29	// _usage = usage_unset(_usage,USE_VHDL );
30	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
31	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
32	// _usage = usage_unset(_usage,USE_POSITION );
33	// _usage = usage_unset(_usage,USE_STATISTICS );
34	// _usage = usage_unset(_usage,USE_INFORMATION );
35
36	Address_management * _Address_management = new Address_management
37	(name.c_str(),
38	#ifdef STATISTICS
39	_parameters_statistics,
40	#endif
41	_param,
42	_usage);
43
44	#ifdef SYSTEMC
45	/*********************************************************************
46	* Déclarations des signaux
47	*********************************************************************/
48	string rename;
49
50	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
51	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
52
53	ALLOC_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t );
54	ALLOC_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t );
55	ALLOC_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t);
56	ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
57	ALLOC_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t);
58	ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t );
59	ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
60	ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t );
61	ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t );
62	ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t);
63	ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t);
64	ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t );
65	ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t);
66	ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t );
67	ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
68	ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t);
69	//ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT ," in_PREDICT_BRANCH_IS_CURRENT ",Tcontrol_t );
70	ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t );
71	ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
72	ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t );
73	ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t );
74	ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t);
75	ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT ," in_EVENT_ADDRESS_NEXT ",Tgeneral_address_t);
76	ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS_NEXT_VAL ," in_EVENT_ADDRESS_NEXT_VAL ",Tcontrol_t );
77	ALLOC_SC_SIGNAL ( in_EVENT_IS_DS_TAKE ," in_EVENT_IS_DS_TAKE ",Tcontrol_t );
78
79	/********************************************************
80	* Instanciation
81	********************************************************/
82
83	msg(_("<%s> : Instanciation of _Address_management.\n"),name.c_str());
84
85	((_Address_management->in_CLOCK)) ((in_CLOCK));
86	((_Address_management->in_NRESET)) ((in_NRESET));
87
88	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_VAL );
89	INSTANCE_SC_SIGNAL (_Address_management, in_ADDRESS_ACK );
90	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS );
91	INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction);
92	if (_param->_have_port_inst_ifetch_ptr)
93	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR );
94	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE );
95	if (_param->_have_port_depth)
96	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
97	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL );
98	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_ACK );
99	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS );
100	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT );
101	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE );
102	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT );
103	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE );
104	INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction);
105	if (_param->_have_port_inst_ifetch_ptr)
106	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR );
107	//INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT );
108	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE );
109	if (_param->_have_port_depth)
110	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
111	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL );
112	INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK );
113	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS );
114	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT );
115	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS_NEXT_VAL );
116	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_IS_DS_TAKE );
117
118	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
119
120	Time * _time = new Time();
121
122	/********************************************************
123	* Simulation - Begin
124	********************************************************/
125
126	// Initialisation
127
128	const uint32_t seed = 0;
129	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
130
131	srand(seed);
132
133	const int32_t percent_transaction_address = 100;
134	const int32_t percent_transaction_predict = 100;
135	const int32_t percent_transaction_event = 0;
136
137	SC_START(0);
138	LABEL("Initialisation");
139
140	LABEL("Reset");
141
142	in_ADDRESS_ACK->write(0);
143	out_PREDICT_VAL->write(0);
144	in_EVENT_VAL ->write(0);
145
146	in_NRESET->write(0);
147	SC_START(5);
148	in_NRESET->write(1);
149
150	LABEL("Test Reset");
151
152	TEST(Tcontrol_t, out_ADDRESS_VAL->read(), false);
153	TEST(Tcontrol_t, in_PREDICT_ACK->read(), false); // can't send a prediction
154	TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event
155
156	uint32_t jump = 7 ;// packet
157	uint32_t nb_packet = 1;
158
159	Tcontrol_t a_val = false;
160	Tcontrol_t c_val = false;
161	Tcontrol_t n_val = true ;
162	Tcontrol_t nn_val = false;
163
164	Tgeneral_data_t a_addr = 0x100>>2;
165	Tgeneral_data_t c_addr = 0x100>>2;
166	Tgeneral_data_t n_addr = 0x100>>2;
167	Tgeneral_data_t nn_addr = 0x100>>2;
168
169	Tcontrol_t a_enable [_param->_nb_instruction];
170	Tcontrol_t c_enable [_param->_nb_instruction];
171	Tcontrol_t n_enable [_param->_nb_instruction];
172
173	Tcontrol_t a_is_ds_take = 0;
174	Tcontrol_t c_is_ds_take = 0;
175	Tcontrol_t n_is_ds_take = 0;
176	Tcontrol_t nn_is_ds_take = 0;
177
178	n_enable [0] = 1;
179	for (uint32_t i=1; i<_param->_nb_instruction; i++)
180	n_enable [i] = 0;
181
182	LABEL("Send Reset");
183	// do
184	// {
185	// in_EVENT_VAL ->write(1);
186	// in_EVENT_ADDRESS ->write(n_addr);
187	// in_EVENT_ADDRESS_NEXT ->write(nn_addr);
188	// in_EVENT_ADDRESS_NEXT_VAL->write(0);
189	// in_EVENT_IS_DS_TAKE ->write(0);
190	// SC_START(1);
191	// } while (out_EVENT_ACK->read() == false);
192	// in_EVENT_VAL ->write(0);
193
194	n_val = 1;
195
196	LABEL("Loop of Test");
197
198	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
199	{
200	LABEL("Iteration %d",iteration);
201
202	// PREDICT
203	{
204	in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict);
205
206	SC_START(0);
207
208	Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read();
209
210	uint32_t begin = addr%_param->_nb_instruction;
211	uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1);
212	Tcontrol_t take = (nb_packet%jump)==0;
213
214	if (take)
215	addr += 0x100;
216	else
217	addr += end-begin+1;
218
219	for (uint32_t i=0; i<_param->_nb_instruction; i++)
220	in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end));
221	in_PREDICT_PC_NEXT ->write(addr);
222	in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take);
223	in_PREDICT_INST_IFETCH_PTR ->write(0);
224	// in_PREDICT_BRANCH_IS_CURRENT ->write(0);
225	in_PREDICT_BRANCH_STATE ->write(0);
226	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
227	}
228
229	// ADDRESS
230	{
231	in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address);
232	}
233
234	in_EVENT_VAL ->write((rand()%100)<percent_transaction_event );
235	in_EVENT_ADDRESS ->write(0x77);
236	in_EVENT_ADDRESS_NEXT ->write(0x171);
237	Tcontrol_t next_val = rand()%2;
238	in_EVENT_ADDRESS_NEXT_VAL->write(next_val);
239	in_EVENT_IS_DS_TAKE ->write(next_val);
240
241	//-------------------------------------------------
242	SC_START(0);
243	//-------------------------------------------------
244
245	if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
246	{
247	LABEL("PREDICT : Transaction accepted");
248
249	if (c_val)
250	TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr );
251	TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr );
252	TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take);
253
254	nn_val = true;
255	nn_addr = in_PREDICT_PC_NEXT ->read();
256	nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read();
257
258	for (uint32_t i=0; i<_param->_nb_instruction; i++)
259	n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
260
261	LABEL(" * nn_addr : %.8x",nn_addr);
262	}
263
264	if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read())
265	{
266	LABEL("ADDRESS : Transaction accepted");
267	LABEL(" * address wait : %.8x",a_addr);
268
269	TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),a_addr);
270	for (uint32_t i=0; i<_param->_nb_instruction; i++)
271	TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),a_enable[i]);
272	if (_param->_have_port_inst_ifetch_ptr)
273	TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0);
274	TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),0);
275	if (_param->_have_port_depth)
276	TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0);
277
278	a_val = 0;
279	nb_packet ++;
280	}
281
282	{
283	string str_a_enable = "";
284	string str_c_enable = "";
285	string str_n_enable = "";
286
287	for (uint32_t i=0; i<_param->_nb_instruction; i++)
288	{
289	str_a_enable += " " + toString(a_enable [i]);
290	str_c_enable += " " + toString(c_enable [i]);
291	str_n_enable += " " + toString(n_enable [i]);
292	}
293
294	LABEL("----[ Before ]---------------------");
295	LABEL(" * nb_packet : %d",nb_packet);
296	LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str());
297	LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str());
298	LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str());
299	LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr);
300	LABEL("-----------------------------------");
301	}
302
303	if (not a_val)
304	{
305	if (c_val and n_val and nn_val)
306	{
307	a_val = 1;
308	c_val = 0;
309	a_addr = c_addr;
310	a_is_ds_take = c_is_ds_take;
311
312	for (uint32_t i=0; i<_param->_nb_instruction; i++)
313	a_enable [i] = c_enable [i];
314	}
315	}
316
317	if (not c_val)
318	{
319	c_val = n_val;
320	if (n_val)
321	{
322	c_addr = n_addr;
323	c_is_ds_take = n_is_ds_take;
324
325	for (uint32_t i=0; i<_param->_nb_instruction; i++)
326	c_enable [i] = n_enable [i];
327	}
328	n_val = 0;
329	}
330
331	if (not n_val)
332	{
333	n_val = nn_val;
334	if (nn_val)
335	{
336	n_addr = nn_addr;
337	n_is_ds_take = nn_is_ds_take;
338
339	// for (uint32_t i=0; i<_param->_nb_instruction; i++)
340	// n_enable [i] = nn_enable [i];
341	}
342	nn_val = 0;
343	}
344
345	if (in_EVENT_VAL->read() and out_EVENT_ACK->read())
346	{
347	LABEL("EVENT : Transaction accepted");
348
349	a_val = false;
350	c_val = false;
351	n_val = true;
352	n_addr = in_EVENT_ADDRESS ->read();
353	n_is_ds_take = in_EVENT_IS_DS_TAKE ->read();
354	nn_val = in_EVENT_ADDRESS_NEXT_VAL->read();
355	nn_addr = in_EVENT_ADDRESS_NEXT ->read();
356	nn_is_ds_take= false;
357	// nn_val = false;
358	// n_is_ds_take = 0;
359
360	n_enable [0] = 1;
361	for (uint32_t i=1; i<_param->_nb_instruction; i++)
362	n_enable [i] = 0;
363	}
364
365
366	{
367	string str_a_enable = "";
368	string str_c_enable = "";
369	string str_n_enable = "";
370
371	for (uint32_t i=0; i<_param->_nb_instruction; i++)
372	{
373	str_a_enable += " " + toString(a_enable [i]);
374	str_c_enable += " " + toString(c_enable [i]);
375	str_n_enable += " " + toString(n_enable [i]);
376	}
377
378	LABEL("----[ After ]----------------------");
379	LABEL(" * nb_packet : %d",nb_packet);
380	LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str());
381	LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str());
382	LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str());
383	LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr);
384	LABEL("-----------------------------------");
385	}
386
387	SC_START(1);
388
389	}
390
391	/********************************************************
392	* Simulation - End
393	********************************************************/
394
395	TEST_OK ("End of Simulation");
396	delete _time;
397
398	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
399
400	delete in_CLOCK;
401	delete in_NRESET;
402
403	delete out_ADDRESS_VAL ;
404	delete in_ADDRESS_ACK ;
405	delete out_ADDRESS_INSTRUCTION_ADDRESS ;
406	delete [] out_ADDRESS_INSTRUCTION_ENABLE ;
407	delete out_ADDRESS_INST_IFETCH_PTR ;
408	delete out_ADDRESS_BRANCH_STATE ;
409	delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
410	delete out_PREDICT_VAL ;
411	delete in_PREDICT_ACK ;
412	delete out_PREDICT_PC_PREVIOUS ;
413	delete out_PREDICT_PC_CURRENT ;
414	delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ;
415	delete in_PREDICT_PC_NEXT ;
416	delete in_PREDICT_PC_NEXT_IS_DS_TAKE ;
417	delete [] in_PREDICT_INSTRUCTION_ENABLE ;
418	delete in_PREDICT_INST_IFETCH_PTR ;
419	//delete in_PREDICT_BRANCH_IS_CURRENT ;
420	delete in_PREDICT_BRANCH_STATE ;
421	delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
422	delete in_EVENT_VAL ;
423	delete out_EVENT_ACK ;
424	delete in_EVENT_ADDRESS ;
425	delete in_EVENT_ADDRESS_NEXT ;
426	delete in_EVENT_ADDRESS_NEXT_VAL ;
427	delete in_EVENT_IS_DS_TAKE ;
428	#endif
429
430	delete _Address_management;
431	#ifdef STATISTICS
432	delete _parameters_statistics;
433	#endif
434	}

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