Changeset 101 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
- Timestamp:
- Jan 15, 2009, 6:19:08 PM (15 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp
r88 r101 67 67 ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction); 68 68 ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t); 69 //ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_IS_CURRENT ," in_PREDICT_BRANCH_IS_CURRENT ",Tcontrol_t ); 69 70 ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t ); 70 71 ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t ); … … 104 105 if (_param->_have_port_inst_ifetch_ptr) 105 106 INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR ); 107 //INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_IS_CURRENT ); 106 108 INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE ); 107 109 if (_param->_have_port_depth) … … 129 131 srand(seed); 130 132 131 const int32_t percent_transaction_address = 75;132 const int32_t percent_transaction_predict = 75;133 const int32_t percent_transaction_event = 5;133 const int32_t percent_transaction_address = 100; 134 const int32_t percent_transaction_predict = 100; 135 const int32_t percent_transaction_event = 0; 134 136 135 137 SC_START(0); … … 155 157 uint32_t nb_packet = 1; 156 158 159 Tcontrol_t a_val = false; 157 160 Tcontrol_t c_val = false; 158 Tcontrol_t n_val = false;161 Tcontrol_t n_val = true ; 159 162 Tcontrol_t nn_val = false; 160 163 164 Tgeneral_data_t a_addr = 0x100>>2; 161 165 Tgeneral_data_t c_addr = 0x100>>2; 162 166 Tgeneral_data_t n_addr = 0x100>>2; 163 167 Tgeneral_data_t nn_addr = 0x100>>2; 164 168 169 Tcontrol_t a_enable [_param->_nb_instruction]; 165 170 Tcontrol_t c_enable [_param->_nb_instruction]; 166 171 Tcontrol_t n_enable [_param->_nb_instruction]; 167 172 173 Tcontrol_t a_is_ds_take = 0; 168 174 Tcontrol_t c_is_ds_take = 0; 169 175 Tcontrol_t n_is_ds_take = 0; 170 176 Tcontrol_t nn_is_ds_take = 0; 171 177 172 c_enable [0] = 1;178 n_enable [0] = 1; 173 179 for (uint32_t i=1; i<_param->_nb_instruction; i++) 174 c_enable [i] = 0;180 n_enable [i] = 0; 175 181 176 182 LABEL("Send Reset"); … … 216 222 in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take); 217 223 in_PREDICT_INST_IFETCH_PTR ->write(0); 224 // in_PREDICT_BRANCH_IS_CURRENT ->write(0); 218 225 in_PREDICT_BRANCH_STATE ->write(0); 219 226 in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0); … … 251 258 for (uint32_t i=0; i<_param->_nb_instruction; i++) 252 259 n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read(); 260 261 LABEL(" * nn_addr : %.8x",nn_addr); 253 262 } 254 263 … … 256 265 { 257 266 LABEL("ADDRESS : Transaction accepted"); 258 LABEL(" * address wait : %.8x", c_addr);259 260 TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(), c_addr);267 LABEL(" * address wait : %.8x",a_addr); 268 269 TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),a_addr); 261 270 for (uint32_t i=0; i<_param->_nb_instruction; i++) 262 TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(), c_enable[i]);271 TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),a_enable[i]); 263 272 if (_param->_have_port_inst_ifetch_ptr) 264 273 TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0); … … 267 276 TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0); 268 277 269 c_val = 0;278 a_val = 0; 270 279 nb_packet ++; 271 280 } 272 281 282 { 283 string str_a_enable = ""; 284 string str_c_enable = ""; 285 string str_n_enable = ""; 286 287 for (uint32_t i=0; i<_param->_nb_instruction; i++) 288 { 289 str_a_enable += " " + toString(a_enable [i]); 290 str_c_enable += " " + toString(c_enable [i]); 291 str_n_enable += " " + toString(n_enable [i]); 292 } 293 294 LABEL("----[ Before ]---------------------"); 295 LABEL(" * nb_packet : %d",nb_packet); 296 LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str()); 297 LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str()); 298 LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str()); 299 LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr); 300 LABEL("-----------------------------------"); 301 } 302 303 if (not a_val) 304 { 305 if (c_val and n_val and nn_val) 306 { 307 a_val = 1; 308 c_val = 0; 309 a_addr = c_addr; 310 a_is_ds_take = c_is_ds_take; 311 312 for (uint32_t i=0; i<_param->_nb_instruction; i++) 313 a_enable [i] = c_enable [i]; 314 } 315 } 273 316 274 317 if (not c_val) 275 { 276 if (n_val and nn_val) 277 { 278 c_val = 1; 279 c_addr = n_addr; 280 c_is_ds_take = n_is_ds_take; 281 282 for (uint32_t i=0; i<_param->_nb_instruction; i++) 283 c_enable [i] = n_enable [i]; 284 285 n_val = 1; 286 n_addr = nn_addr; 287 n_is_ds_take = nn_is_ds_take; 288 289 nn_val = 0; 290 } 291 } 318 { 319 c_val = n_val; 320 if (n_val) 321 { 322 c_addr = n_addr; 323 c_is_ds_take = n_is_ds_take; 324 325 for (uint32_t i=0; i<_param->_nb_instruction; i++) 326 c_enable [i] = n_enable [i]; 327 } 328 n_val = 0; 329 } 330 331 if (not n_val) 332 { 333 n_val = nn_val; 334 if (nn_val) 335 { 336 n_addr = nn_addr; 337 n_is_ds_take = nn_is_ds_take; 338 339 // for (uint32_t i=0; i<_param->_nb_instruction; i++) 340 // n_enable [i] = nn_enable [i]; 341 } 342 nn_val = 0; 343 } 292 344 293 345 if (in_EVENT_VAL->read() and out_EVENT_ACK->read()) … … 295 347 LABEL("EVENT : Transaction accepted"); 296 348 349 a_val = false; 297 350 c_val = false; 298 351 n_val = true; … … 312 365 313 366 { 367 string str_a_enable = ""; 314 368 string str_c_enable = ""; 315 369 string str_n_enable = ""; … … 317 371 for (uint32_t i=0; i<_param->_nb_instruction; i++) 318 372 { 373 str_a_enable += " " + toString(a_enable [i]); 319 374 str_c_enable += " " + toString(c_enable [i]); 320 375 str_n_enable += " " + toString(n_enable [i]); 321 376 } 322 377 323 LABEL("---- -------------------------------");378 LABEL("----[ After ]----------------------"); 324 379 LABEL(" * nb_packet : %d",nb_packet); 325 LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str()); 326 if (nn_val) 327 { 328 LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str()); 329 } 330 else 331 { 332 LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr ); 333 } 334 LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr); 380 LABEL(" * pc a : %d %d %.8x %s",a_val ,a_is_ds_take ,a_addr ,str_a_enable.c_str()); 381 LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take ,c_addr ,str_c_enable.c_str()); 382 LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take ,n_addr ,str_n_enable.c_str()); 383 LABEL(" * pc+8 : %d %d %.8x" ,nn_val,nn_is_ds_take,nn_addr); 335 384 LABEL("-----------------------------------"); 336 385 } … … 368 417 delete [] in_PREDICT_INSTRUCTION_ENABLE ; 369 418 delete in_PREDICT_INST_IFETCH_PTR ; 419 //delete in_PREDICT_BRANCH_IS_CURRENT ; 370 420 delete in_PREDICT_BRANCH_STATE ; 371 421 delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
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