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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp @ 82

Last change on this file since 82 was 82, checked in by rosiere, 16 years ago
support locale (now must "just" translate) update all component with new test format update all component with usage New component : decod queue and prediction_unit
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File size: 14.3 KB

Line
1	/*
2	* $Id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9
10	#define NB_ITERATION 1024
11	#define CYCLE_MAX (128*NB_ITERATION)
12
13	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/include/test.h"
14	#include "Common/include/Test.h"
15	#include "Behavioural/include/Allocation.h"
16
17	void test (string name,
18	morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param)
19	{
20	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
21
22	#ifdef STATISTICS
23	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
24	#endif
25
26	Address_management * _Address_management = new Address_management
27	(name.c_str(),
28	#ifdef STATISTICS
29	_parameters_statistics,
30	#endif
31	_param,
32	USE_ALL);
33
34	#ifdef SYSTEMC
35	/*********************************************************************
36	* Déclarations des signaux
37	*********************************************************************/
38	string rename;
39
40	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
41	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
42
43	ALLOC_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t );
44	ALLOC_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t );
45	ALLOC_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t);
46	ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
47	ALLOC_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t);
48	ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t );
49	ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
50	ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t );
51	ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t );
52	ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t);
53	ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t);
54	ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t );
55	ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t);
56	ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t );
57	ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
58	ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t);
59	ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t );
60	ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
61	ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t );
62	ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t );
63	ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t);
64
65	/********************************************************
66	* Instanciation
67	********************************************************/
68
69	msg(_("<%s> : Instanciation of _Address_management.\n"),name.c_str());
70
71	((_Address_management->in_CLOCK)) ((in_CLOCK));
72	((_Address_management->in_NRESET)) ((in_NRESET));
73
74	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_VAL );
75	INSTANCE_SC_SIGNAL (_Address_management, in_ADDRESS_ACK );
76	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS );
77	INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction);
78	if (_param->_have_port_instruction_ptr)
79	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR );
80	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE );
81	if (_param->_have_port_branch_update_prediction_id)
82	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
83	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL );
84	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_ACK );
85	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS );
86	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT );
87	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE );
88	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT );
89	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE );
90	INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction);
91	if (_param->_have_port_instruction_ptr)
92	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR );
93	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE );
94	if (_param->_have_port_branch_update_prediction_id)
95	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
96	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL );
97	INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK );
98	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS );
99
100	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
101
102	Time * _time = new Time();
103
104	/********************************************************
105	* Simulation - Begin
106	********************************************************/
107
108	// Initialisation
109
110	const uint32_t seed = 0;
111	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
112
113	srand(seed);
114
115	const int32_t percent_transaction_address = 75;
116	const int32_t percent_transaction_predict = 75;
117	const int32_t percent_transaction_event = 10;
118
119	SC_START(0);
120	LABEL("Initialisation");
121
122	LABEL("Reset");
123
124	in_ADDRESS_ACK->write(0);
125	out_PREDICT_VAL->write(0);
126	in_EVENT_VAL ->write(0);
127
128	in_NRESET->write(0);
129	SC_START(5);
130	in_NRESET->write(1);
131
132	LABEL("Test Reset");
133
134	TEST(Tcontrol_t, out_ADDRESS_VAL->read(), false);
135	TEST(Tcontrol_t, in_PREDICT_ACK->read(), false); // can't send a prediction
136	TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event
137
138	Tcontrol_t p_val = false;
139	Tcontrol_t c_val = false;
140	Tcontrol_t n_val = false;
141
142	Tgeneral_data_t p_addr = 0x100;
143	Tgeneral_data_t c_addr = 0x100;
144	Tgeneral_data_t n_addr = 0x100;
145	Tcontrol_t c_enable [_param->_nb_instruction];
146	Tcontrol_t n_enable [_param->_nb_instruction];
147
148	Tcontrol_t c_is_ds_take = 0;
149	Tinst_ifetch_ptr_t c_ifetch_ptr = 0;
150	Tbranch_state_t c_branch_state = BRANCH_STATE_NONE;
151	Tprediction_ptr_t c_branch_ptr = 0;
152
153	Tcontrol_t n_is_ds_take = 0;
154	Tinst_ifetch_ptr_t n_ifetch_ptr = 0;
155	Tbranch_state_t n_branch_state = BRANCH_STATE_NONE;
156	Tprediction_ptr_t n_branch_ptr = 0;
157
158	c_enable [0] = 1;
159	for (uint32_t i=1; i<_param->_nb_instruction; i++)
160	c_enable [i] = 0;
161
162	LABEL("Send Reset");
163	do
164	{
165	in_EVENT_VAL ->write(1);
166	in_EVENT_ADDRESS->write(c_addr);
167	SC_START(1);
168	} while (out_EVENT_ACK->read() == false);
169	in_EVENT_VAL ->write(0);
170
171	LABEL("Loop of Test");
172
173	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
174	{
175	LABEL("Iteration %d",iteration);
176
177	in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address);
178	in_EVENT_VAL ->write((rand()%100)<percent_transaction_event );
179	in_EVENT_ADDRESS->write(rand() << 2);
180
181	uint32_t begin = rand() % _param->_nb_instruction;
182	uint32_t end = (begin + (rand() % _param->_nb_instruction));
183	end = (end > _param->_nb_instruction)?_param->_nb_instruction:end;
184
185	in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict);
186	for (uint32_t i=0; i<_param->_nb_instruction; i++)
187	in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end));
188	in_PREDICT_PC_NEXT ->write(rand() << 2);
189	in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(rand()%2);
190	in_PREDICT_INST_IFETCH_PTR ->write(begin);
191	in_PREDICT_BRANCH_STATE ->write(c_addr%SIZE_BRANCH_STATE);
192	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(c_addr%_param->_size_branch_update_prediction);
193
194	SC_START(0);
195
196	LABEL("---------------------");
197	LABEL(" * pc-4 : %d %.8x",p_val, p_addr);
198	LABEL(" * pc : %d %.8x",c_val, c_addr);
199	LABEL(" * pc+4 : %d %.8x",n_val, n_addr);
200	LABEL("---------------------");
201
202	if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
203	{
204	LABEL("PREDICT : Transaction accepted");
205
206	TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),p_addr);
207	TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),c_addr);
208	TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),c_is_ds_take);
209	}
210
211	if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read())
212	{
213	LABEL("ADDRESS : Transaction accepted");
214	LABEL(" * address wait : %.8x",c_addr);
215
216	TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),c_addr);
217	for (uint32_t i=0; i<_param->_nb_instruction; i++)
218	TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),c_enable[i]);
219	if (_param->_have_port_instruction_ptr)
220	TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),c_ifetch_ptr );
221	TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),c_branch_state);
222	if (_param->_have_port_branch_update_prediction_id)
223	TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),c_branch_ptr );
224
225	p_val = true;
226	c_val = n_val;
227
228	p_addr = c_addr;
229
230	if (n_val)
231	{
232	c_addr = n_addr;
233
234	c_ifetch_ptr = n_ifetch_ptr ;
235	c_branch_state = n_branch_state;
236	c_branch_ptr = n_branch_ptr ;
237	c_is_ds_take = n_is_ds_take ;
238
239	for (uint32_t i=0; i<_param->_nb_instruction; i++)
240	c_enable [i] = n_enable [i];
241	}
242
243	n_val = false;
244
245	LABEL(" * pc-4 : %d %.8x",p_val, p_addr);
246	LABEL(" * pc : %d %.8x",c_val, c_addr);
247	LABEL(" * pc+4 : %d %.8x",n_val, n_addr);
248	}
249
250	if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
251	{
252	LABEL("PREDICT : Update information");
253
254	if (c_val)
255	{
256	LABEL(" * current is valid -> new next");
257	n_val = true;
258
259	for (uint32_t i=0; i<_param->_nb_instruction; i++)
260	n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i] ->read();
261	n_addr = in_PREDICT_PC_NEXT ->read();
262	n_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE ->read();
263	n_ifetch_ptr = in_PREDICT_INST_IFETCH_PTR ->read();
264	n_branch_state = in_PREDICT_BRANCH_STATE ->read();
265	n_branch_ptr = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read();
266	}
267	else
268	{
269	LABEL(" * current is not valid -> new current");
270	c_val = true;
271
272	for (uint32_t i=0; i<_param->_nb_instruction; i++)
273	c_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i] ->read();
274	c_addr = in_PREDICT_PC_NEXT ->read();
275	c_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE ->read();
276	c_ifetch_ptr = in_PREDICT_INST_IFETCH_PTR ->read();
277	c_branch_state = in_PREDICT_BRANCH_STATE ->read();
278	c_branch_ptr = in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->read();
279	}
280
281	LABEL(" * pc-4 : %d %.8x",p_val, p_addr);
282	LABEL(" * pc : %d %.8x",c_val, c_addr);
283	LABEL(" * pc+4 : %d %.8x",n_val, n_addr);
284
285	}
286
287	if (in_EVENT_VAL->read() and out_EVENT_ACK->read())
288	{
289	LABEL("EVENT : Transaction accepted");
290
291	c_val = true;
292	n_val = false;
293
294	c_addr = in_EVENT_ADDRESS->read();
295	c_ifetch_ptr = 0;
296	c_branch_state = BRANCH_STATE_NONE;
297	c_branch_ptr = 0;
298	c_is_ds_take = 0;
299
300	c_enable [0] = 1;
301	for (uint32_t i=1; i<_param->_nb_instruction; i++)
302	c_enable [i] = 0;
303
304	LABEL(" * pc-4 : %d %.8x",p_val, p_addr);
305	LABEL(" * pc : %d %.8x",c_val, c_addr);
306	LABEL(" * pc+4 : %d %.8x",n_val, n_addr);
307	}
308	SC_START(1);
309	}
310
311	/********************************************************
312	* Simulation - End
313	********************************************************/
314
315	TEST_OK ("End of Simulation");
316	delete _time;
317
318	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
319
320	delete in_CLOCK;
321	delete in_NRESET;
322
323	delete out_ADDRESS_VAL ;
324	delete in_ADDRESS_ACK ;
325	delete out_ADDRESS_INSTRUCTION_ADDRESS ;
326	delete [] out_ADDRESS_INSTRUCTION_ENABLE ;
327	delete out_ADDRESS_INST_IFETCH_PTR ;
328	delete out_ADDRESS_BRANCH_STATE ;
329	delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
330	delete out_PREDICT_VAL ;
331	delete in_PREDICT_ACK ;
332	delete out_PREDICT_PC_PREVIOUS ;
333	delete out_PREDICT_PC_CURRENT ;
334	delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ;
335	delete in_PREDICT_PC_NEXT ;
336	delete in_PREDICT_PC_NEXT_IS_DS_TAKE ;
337	delete [] in_PREDICT_INSTRUCTION_ENABLE ;
338	delete in_PREDICT_INST_IFETCH_PTR ;
339	delete in_PREDICT_BRANCH_STATE ;
340	delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
341	delete in_EVENT_VAL ;
342	delete out_EVENT_ACK ;
343	delete in_EVENT_ADDRESS ;
344	#endif
345
346	delete _Address_management;
347	#ifdef STATISTICS
348	delete _parameters_statistics;
349	#endif
350	}

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