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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/src/test.cpp @ 84

Last change on this file since 84 was 84, checked in by rosiere, 16 years ago

Change Address_manager :

before : pc_previous, pc_current, pc_next
now : pc_current, pc_next, pc_next_next.

pc_next is send at the prediction_unit, it return the instruction_enable and pc_next_next

Property svn:keywords set to Id

File size: 13.4 KB

Line
1	/*
2	* $Id: test.cpp 84 2008-05-13 18:04:50Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9
10	#define NB_ITERATION 1024
11	#define CYCLE_MAX (128*NB_ITERATION)
12
13	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/SelfTest/include/test.h"
14	#include "Common/include/Test.h"
15	#include "Behavioural/include/Allocation.h"
16
17	void test (string name,
18	morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Parameters * _param)
19	{
20	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
21
22	#ifdef STATISTICS
23	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
24	#endif
25
26	Address_management * _Address_management = new Address_management
27	(name.c_str(),
28	#ifdef STATISTICS
29	_parameters_statistics,
30	#endif
31	_param,
32	USE_ALL);
33
34	#ifdef SYSTEMC
35	/*********************************************************************
36	* Déclarations des signaux
37	*********************************************************************/
38	string rename;
39
40	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
41	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
42
43	ALLOC_SC_SIGNAL (out_ADDRESS_VAL ,"out_ADDRESS_VAL ",Tcontrol_t );
44	ALLOC_SC_SIGNAL ( in_ADDRESS_ACK ," in_ADDRESS_ACK ",Tcontrol_t );
45	ALLOC_SC_SIGNAL (out_ADDRESS_INSTRUCTION_ADDRESS ,"out_ADDRESS_INSTRUCTION_ADDRESS ",Tgeneral_address_t);
46	ALLOC1_SC_SIGNAL(out_ADDRESS_INSTRUCTION_ENABLE ,"out_ADDRESS_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
47	ALLOC_SC_SIGNAL (out_ADDRESS_INST_IFETCH_PTR ,"out_ADDRESS_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t);
48	ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_STATE ,"out_ADDRESS_BRANCH_STATE ",Tbranch_state_t );
49	ALLOC_SC_SIGNAL (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
50	ALLOC_SC_SIGNAL (out_PREDICT_VAL ,"out_PREDICT_VAL ",Tcontrol_t );
51	ALLOC_SC_SIGNAL ( in_PREDICT_ACK ," in_PREDICT_ACK ",Tcontrol_t );
52	ALLOC_SC_SIGNAL (out_PREDICT_PC_PREVIOUS ,"out_PREDICT_PC_PREVIOUS ",Tgeneral_address_t);
53	ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT ,"out_PREDICT_PC_CURRENT ",Tgeneral_address_t);
54	ALLOC_SC_SIGNAL (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE ",Tcontrol_t );
55	ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT ," in_PREDICT_PC_NEXT ",Tgeneral_address_t);
56	ALLOC_SC_SIGNAL ( in_PREDICT_PC_NEXT_IS_DS_TAKE ," in_PREDICT_PC_NEXT_IS_DS_TAKE ",Tcontrol_t );
57	ALLOC1_SC_SIGNAL( in_PREDICT_INSTRUCTION_ENABLE ," in_PREDICT_INSTRUCTION_ENABLE ",Tcontrol_t ,_param->_nb_instruction);
58	ALLOC_SC_SIGNAL ( in_PREDICT_INST_IFETCH_PTR ," in_PREDICT_INST_IFETCH_PTR ",Tinst_ifetch_ptr_t);
59	ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_STATE ," in_PREDICT_BRANCH_STATE ",Tbranch_state_t );
60	ALLOC_SC_SIGNAL ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID," in_PREDICT_BRANCH_UPDATE_PREDICTION_ID",Tprediction_ptr_t );
61	ALLOC_SC_SIGNAL ( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t );
62	ALLOC_SC_SIGNAL (out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t );
63	ALLOC_SC_SIGNAL ( in_EVENT_ADDRESS ," in_EVENT_ADDRESS ",Tgeneral_address_t);
64
65	/********************************************************
66	* Instanciation
67	********************************************************/
68
69	msg(_("<%s> : Instanciation of _Address_management.\n"),name.c_str());
70
71	((_Address_management->in_CLOCK)) ((in_CLOCK));
72	((_Address_management->in_NRESET)) ((in_NRESET));
73
74	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_VAL );
75	INSTANCE_SC_SIGNAL (_Address_management, in_ADDRESS_ACK );
76	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INSTRUCTION_ADDRESS );
77	INSTANCE1_SC_SIGNAL(_Address_management,out_ADDRESS_INSTRUCTION_ENABLE ,_param->_nb_instruction);
78	if (_param->_have_port_instruction_ptr)
79	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_INST_IFETCH_PTR );
80	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_STATE );
81	if (_param->_have_port_branch_update_prediction_id)
82	INSTANCE_SC_SIGNAL (_Address_management,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID);
83	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_VAL );
84	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_ACK );
85	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_PREVIOUS );
86	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT );
87	INSTANCE_SC_SIGNAL (_Address_management,out_PREDICT_PC_CURRENT_IS_DS_TAKE );
88	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT );
89	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_PC_NEXT_IS_DS_TAKE );
90	INSTANCE1_SC_SIGNAL(_Address_management, in_PREDICT_INSTRUCTION_ENABLE ,_param->_nb_instruction);
91	if (_param->_have_port_instruction_ptr)
92	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_INST_IFETCH_PTR );
93	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_STATE );
94	if (_param->_have_port_branch_update_prediction_id)
95	INSTANCE_SC_SIGNAL (_Address_management, in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
96	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_VAL );
97	INSTANCE_SC_SIGNAL (_Address_management,out_EVENT_ACK );
98	INSTANCE_SC_SIGNAL (_Address_management, in_EVENT_ADDRESS );
99
100	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
101
102	Time * _time = new Time();
103
104	/********************************************************
105	* Simulation - Begin
106	********************************************************/
107
108	// Initialisation
109
110	const uint32_t seed = 0;
111	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
112
113	srand(seed);
114
115	const int32_t percent_transaction_address = 75;
116	const int32_t percent_transaction_predict = 75;
117	const int32_t percent_transaction_event = 5;
118
119	SC_START(0);
120	LABEL("Initialisation");
121
122	LABEL("Reset");
123
124	in_ADDRESS_ACK->write(0);
125	out_PREDICT_VAL->write(0);
126	in_EVENT_VAL ->write(0);
127
128	in_NRESET->write(0);
129	SC_START(5);
130	in_NRESET->write(1);
131
132	LABEL("Test Reset");
133
134	TEST(Tcontrol_t, out_ADDRESS_VAL->read(), false);
135	TEST(Tcontrol_t, in_PREDICT_ACK->read(), false); // can't send a prediction
136	TEST(Tcontrol_t, out_EVENT_ACK->read() , true ); // can receveive an event
137
138	uint32_t jump = 7 ;// packet
139	uint32_t nb_packet = 1;
140
141	Tcontrol_t c_val = false;
142	Tcontrol_t n_val = false;
143	Tcontrol_t nn_val = false;
144
145	Tgeneral_data_t c_addr = 0x100;
146	Tgeneral_data_t n_addr = 0x100;
147	Tgeneral_data_t nn_addr = 0x100;
148
149	Tcontrol_t c_enable [_param->_nb_instruction];
150	Tcontrol_t n_enable [_param->_nb_instruction];
151
152	Tcontrol_t c_is_ds_take = 0;
153	Tcontrol_t n_is_ds_take = 0;
154	Tcontrol_t nn_is_ds_take = 0;
155
156	c_enable [0] = 1;
157	for (uint32_t i=1; i<_param->_nb_instruction; i++)
158	c_enable [i] = 0;
159
160	LABEL("Send Reset");
161	do
162	{
163	in_EVENT_VAL ->write(1);
164	in_EVENT_ADDRESS->write(n_addr);
165	SC_START(1);
166	} while (out_EVENT_ACK->read() == false);
167	in_EVENT_VAL ->write(0);
168
169	n_val = 1;
170
171	LABEL("Loop of Test");
172
173	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
174	{
175	LABEL("Iteration %d",iteration);
176
177	// PREDICT
178	{
179	in_PREDICT_ACK ->write((rand()%100)<percent_transaction_predict);
180
181	SC_START(0);
182
183	Taddress_t addr = (out_PREDICT_PC_CURRENT_IS_DS_TAKE->read())?out_PREDICT_PC_PREVIOUS->read():out_PREDICT_PC_CURRENT->read();
184
185	uint32_t begin = addr%_param->_nb_instruction;
186	uint32_t end = ((begin<<1)>_param->_nb_instruction)?(_param->_nb_instruction-1):(begin<<1);
187	Tcontrol_t take = (nb_packet%jump)==0;
188
189	if (take)
190	addr += 0x100;
191	else
192	addr += end-begin+1;
193
194	for (uint32_t i=0; i<_param->_nb_instruction; i++)
195	in_PREDICT_INSTRUCTION_ENABLE [i] ->write((i>=begin) and (i<=end));
196	in_PREDICT_PC_NEXT ->write(addr);
197	in_PREDICT_PC_NEXT_IS_DS_TAKE ->write(take);
198	in_PREDICT_INST_IFETCH_PTR ->write(0);
199	in_PREDICT_BRANCH_STATE ->write(0);
200	in_PREDICT_BRANCH_UPDATE_PREDICTION_ID->write(0);
201	}
202
203	// ADDRESS
204	{
205	in_ADDRESS_ACK ->write((rand()%100)<percent_transaction_address);
206	}
207
208	in_EVENT_VAL ->write((rand()%100)<percent_transaction_event );
209	in_EVENT_ADDRESS->write(0x100);
210
211	//-------------------------------------------------
212	SC_START(0);
213	//-------------------------------------------------
214
215	if (out_PREDICT_VAL->read() and in_PREDICT_ACK->read())
216	{
217	LABEL("PREDICT : Transaction accepted");
218
219	if (c_val)
220	TEST(Tgeneral_address_t,out_PREDICT_PC_PREVIOUS ->read(),c_addr );
221	TEST(Tgeneral_address_t,out_PREDICT_PC_CURRENT ->read(),n_addr );
222	TEST(Tcontrol_t ,out_PREDICT_PC_CURRENT_IS_DS_TAKE->read(),n_is_ds_take);
223
224	nn_val = true;
225	nn_addr = in_PREDICT_PC_NEXT ->read();
226	nn_is_ds_take = in_PREDICT_PC_NEXT_IS_DS_TAKE->read();
227
228	for (uint32_t i=0; i<_param->_nb_instruction; i++)
229	n_enable [i] = in_PREDICT_INSTRUCTION_ENABLE [i]->read();
230	}
231
232	if (out_ADDRESS_VAL->read() and in_ADDRESS_ACK->read())
233	{
234	LABEL("ADDRESS : Transaction accepted");
235	LABEL(" * address wait : %.8x",c_addr);
236
237	TEST(Tgeneral_address_t,out_ADDRESS_INSTRUCTION_ADDRESS ->read(),c_addr);
238	for (uint32_t i=0; i<_param->_nb_instruction; i++)
239	TEST(Tcontrol_t ,out_ADDRESS_INSTRUCTION_ENABLE [i] ->read(),c_enable[i]);
240	if (_param->_have_port_instruction_ptr)
241	TEST(Tinst_ifetch_ptr_t,out_ADDRESS_INST_IFETCH_PTR ->read(),0);
242	TEST(Tbranch_state_t ,out_ADDRESS_BRANCH_STATE ->read(),0);
243	if (_param->_have_port_branch_update_prediction_id)
244	TEST(Tprediction_ptr_t ,out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID->read(),0);
245
246	c_val = 0;
247	nb_packet ++;
248	}
249
250
251	if (not c_val)
252	{
253	if (n_val and nn_val)
254	{
255	c_val = 1;
256	c_addr = n_addr;
257	c_is_ds_take = n_is_ds_take;
258
259	for (uint32_t i=0; i<_param->_nb_instruction; i++)
260	c_enable [i] = n_enable [i];
261
262	n_val = 1;
263	n_addr = nn_addr;
264	n_is_ds_take = nn_is_ds_take;
265
266	nn_val = 0;
267	}
268	}
269
270	if (in_EVENT_VAL->read() and out_EVENT_ACK->read())
271	{
272	LABEL("EVENT : Transaction accepted");
273
274	c_val = false;
275	n_val = true;
276	nn_val = false;
277
278	n_addr = in_EVENT_ADDRESS->read();
279	n_is_ds_take = 0;
280
281	n_enable [0] = 1;
282	for (uint32_t i=1; i<_param->_nb_instruction; i++)
283	n_enable [i] = 0;
284	}
285
286
287	{
288	string str_c_enable = "";
289	string str_n_enable = "";
290
291	for (uint32_t i=0; i<_param->_nb_instruction; i++)
292	{
293	str_c_enable += " " + toString(c_enable [i]);
294	str_n_enable += " " + toString(n_enable [i]);
295	}
296
297	LABEL("-----------------------------------");
298	LABEL(" * nb_packet : %d",nb_packet);
299	LABEL(" * pc : %d %d %.8x %s",c_val ,c_is_ds_take , c_addr ,str_c_enable.c_str());
300	if (nn_val)
301	{
302	LABEL(" * pc+4 : %d %d %.8x %s",n_val ,n_is_ds_take , n_addr ,str_n_enable.c_str());
303	}
304	else
305	{
306	LABEL(" * pc+4 : %d %d %.8x" ,n_val ,n_is_ds_take , n_addr );
307	}
308	LABEL(" * pc+8 : %d %d %.8x" ,nn_val ,nn_is_ds_take, nn_addr);
309	LABEL("-----------------------------------");
310	}
311
312	SC_START(1);
313
314	}
315
316	/********************************************************
317	* Simulation - End
318	********************************************************/
319
320	TEST_OK ("End of Simulation");
321	delete _time;
322
323	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
324
325	delete in_CLOCK;
326	delete in_NRESET;
327
328	delete out_ADDRESS_VAL ;
329	delete in_ADDRESS_ACK ;
330	delete out_ADDRESS_INSTRUCTION_ADDRESS ;
331	delete [] out_ADDRESS_INSTRUCTION_ENABLE ;
332	delete out_ADDRESS_INST_IFETCH_PTR ;
333	delete out_ADDRESS_BRANCH_STATE ;
334	delete out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID;
335	delete out_PREDICT_VAL ;
336	delete in_PREDICT_ACK ;
337	delete out_PREDICT_PC_PREVIOUS ;
338	delete out_PREDICT_PC_CURRENT ;
339	delete out_PREDICT_PC_CURRENT_IS_DS_TAKE ;
340	delete in_PREDICT_PC_NEXT ;
341	delete in_PREDICT_PC_NEXT_IS_DS_TAKE ;
342	delete [] in_PREDICT_INSTRUCTION_ENABLE ;
343	delete in_PREDICT_INST_IFETCH_PTR ;
344	delete in_PREDICT_BRANCH_STATE ;
345	delete in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;
346	delete in_EVENT_VAL ;
347	delete out_EVENT_ACK ;
348	delete in_EVENT_ADDRESS ;
349	#endif
350
351	delete _Address_management;
352	#ifdef STATISTICS
353	delete _parameters_statistics;
354	#endif
355	}

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