source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp @ 101

Last change on this file since 101 was 101, checked in by rosiere, 15 years ago

1) Add soc test
2) fix bug (Pc management, Decod and execute, Update prediction ...)

  • Property svn:keywords set to Id
File size: 5.7 KB
Line 
1/*
2 * $Id: Address_management_allocation.cpp 101 2009-01-15 17:19:08Z rosiere $
3 *
4 * [ Description ]
5 *
6 */
7
8#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h"
9#include "Behavioural/include/Allocation.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_front_end {
15namespace front_end {
16namespace ifetch_unit {
17namespace address_management {
18
19
20
21#undef  FUNCTION
22#define FUNCTION "Address_management::allocation"
23  void Address_management::allocation (
24#ifdef STATISTICS
25                                       morpheo::behavioural::Parameters_Statistics * param_statistics
26#else
27                                       void
28#endif
29                                       )
30  {
31    log_printf(FUNC,Address_management,FUNCTION,"Begin");
32
33    _component   = new Component (_usage);
34
35    Entity * entity = _component->set_entity (_name       
36                                              ,"Address_management"
37#ifdef POSITION
38                                              ,COMBINATORY
39#endif
40                                              );
41
42    _interfaces = entity->set_interfaces();
43
44    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
45    {
46      Interface * interface = _interfaces->set_interface(""
47#ifdef POSITION
48                                                         ,IN
49                                                         ,SOUTH,
50                                                         "Generalist interface"
51#endif
52                                                         );
53     
54      in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
55      in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
56    }
57
58    // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
59    {
60      ALLOC_INTERFACE("address", OUT, SOUTH, "Access at request icache.");
61
62      ALLOC_VALACK_OUT (out_ADDRESS_VAL                        ,VAL);
63      ALLOC_VALACK_IN  ( in_ADDRESS_ACK                        ,ACK);
64      ALLOC_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t,_param->_size_instruction_address     );
65      ALLOC_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr         );
66      ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state            );
67      ALLOC_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
68    }
69
70    {
71      ALLOC1_INTERFACE("address", OUT, SOUTH, "Access at request icache.",_param->_nb_instruction);
72
73      ALLOC1_SIGNAL_OUT(out_ADDRESS_INSTRUCTION_ENABLE         ,"instruction_enable"         ,Tcontrol_t        ,1);
74    }
75
76    // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
77    {
78      ALLOC_INTERFACE("predict", IN, NORTH, "Request the prediction unit.");
79
80      ALLOC_VALACK_OUT (out_PREDICT_VAL                        ,VAL);
81      ALLOC_VALACK_IN  ( in_PREDICT_ACK                        ,ACK);
82      ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_instruction_address);
83      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_instruction_address);
84      ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"pc_current_is_ds_take"      ,Tcontrol_t        ,1);
85      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_instruction_address);
86      ALLOC_SIGNAL_IN  ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,"pc_next_is_ds_take"         ,Tcontrol_t        ,1);
87//    ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_IS_CURRENT          ,"branch_is_current"          ,Tcontrol_t        ,1);
88      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
89      ALLOC_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
90      ALLOC_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
91    }
92    {
93      ALLOC1_INTERFACE("predict", IN, NORTH, "Request the prediction unit.",_param->_nb_instruction);
94
95      ALLOC1_SIGNAL_IN (in_PREDICT_INSTRUCTION_ENABLE          ,"instruction_enable"         ,Tcontrol_t        ,1);
96    }
97
98    // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
99    {
100      ALLOC_INTERFACE("event", IN, SOUTH, "Event (miss, exception ...)");
101
102      ALLOC_VALACK_IN ( in_EVENT_VAL          ,VAL);
103      ALLOC_VALACK_OUT(out_EVENT_ACK          ,ACK);
104      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS         ,"address"         ,Tgeneral_address_t,_param->_size_instruction_address);
105      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT    ,"address_next"    ,Tgeneral_address_t,_param->_size_instruction_address);
106      ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"address_next_val",Tcontrol_t,1);
107      ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE      ,"is_ds_take"      ,Tcontrol_t,1);
108    }
109
110    // ~~~~~[ Internal  ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
111    if (usage_is_set(_usage,USE_SYSTEMC))
112      {
113        ALLOC1(reg_PC_ACCESS_INSTRUCTION_ENABLE ,Tcontrol_t,_param->_nb_instruction);
114        ALLOC1(reg_PC_CURRENT_INSTRUCTION_ENABLE,Tcontrol_t,_param->_nb_instruction);
115        ALLOC1(reg_PC_NEXT_INSTRUCTION_ENABLE   ,Tcontrol_t,_param->_nb_instruction);
116      }
117
118    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
119#ifdef POSITION
120     if (usage_is_set(_usage,USE_POSITION))
121       _component->generate_file();
122#endif
123
124    log_printf(FUNC,Address_management,FUNCTION,"End");
125  };
126
127}; // end namespace address_management
128}; // end namespace ifetch_unit
129}; // end namespace front_end
130}; // end namespace multi_front_end
131}; // end namespace core
132
133}; // end namespace behavioural
134}; // end namespace morpheo             
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