source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_allocation.cpp @ 112

Last change on this file since 112 was 112, checked in by rosiere, 15 years ago

1) Stat_list : fix retire old and new register bug
2) Stat_list : remove read_counter and valid flag, because validation of destination is in retire step (not in commit step)
3) Model : add class Model (cf Morpheo.sim)
4) Allocation : alloc_interface_begin and alloc_interface_end to delete temporary array.
5) Script : add distexe.sh
6) Add Comparator, Multiplier, Divider. But this component are not implemented
7) Software : add Dhrystone
  • Property svn:keywords set to Id
File size: 6.0 KB
Line 
1/*
2 * $Id: Address_management_allocation.cpp 112 2009-03-18 22:36:26Z rosiere $
3 *
4 * [ Description ]
5 *
6 */
7
8#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/include/Address_management.h"
9#include "Behavioural/include/Allocation.h"
10
11namespace morpheo                    {
12namespace behavioural {
13namespace core {
14namespace multi_front_end {
15namespace front_end {
16namespace ifetch_unit {
17namespace address_management {
18
19#undef  FUNCTION
20#define FUNCTION "Address_management::allocation"
21  void Address_management::allocation (
22#ifdef STATISTICS
23                                       morpheo::behavioural::Parameters_Statistics * param_statistics
24#else
25                                       void
26#endif
27                                       )
28  {
29    log_printf(FUNC,Address_management,FUNCTION,"Begin");
30
31    _component   = new Component (_usage);
32
33    Entity * entity = _component->set_entity (_name       
34                                              ,"Address_management"
35#ifdef POSITION
36                                              ,COMBINATORY
37#endif
38                                              );
39
40    _interfaces = entity->set_interfaces();
41
42    // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
43    {
44      Interface * interface = _interfaces->set_interface(""
45#ifdef POSITION
46                                                         ,IN
47                                                         ,SOUTH,
48                                                         "Generalist interface"
49#endif
50                                                         );
51     
52      in_CLOCK        = interface->set_signal_clk              ("clock" ,1, CLOCK_VHDL_YES);
53      in_NRESET       = interface->set_signal_in  <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
54    }
55
56    // ~~~~~[ Interface : "address" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
57    {
58      ALLOC0_INTERFACE_BEGIN("address", OUT, SOUTH, _("Access at request icache."));
59
60      ALLOC0_VALACK_OUT (out_ADDRESS_VAL                        ,VAL);
61      ALLOC0_VALACK_IN  ( in_ADDRESS_ACK                        ,ACK);
62      ALLOC0_SIGNAL_OUT (out_ADDRESS_INSTRUCTION_ADDRESS        ,"instruction_address"        ,Tgeneral_address_t,_param->_size_instruction_address     );
63      ALLOC0_SIGNAL_OUT (out_ADDRESS_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr         );
64      ALLOC0_SIGNAL_OUT (out_ADDRESS_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state            );
65      ALLOC0_SIGNAL_OUT (out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
66
67      ALLOC0_INTERFACE_END();
68    }
69
70    {
71      ALLOC1_INTERFACE_BEGIN("address", OUT, SOUTH, _("Access at request icache."),_param->_nb_instruction);
72
73      ALLOC1_SIGNAL_OUT(out_ADDRESS_INSTRUCTION_ENABLE         ,"instruction_enable"         ,Tcontrol_t        ,1);
74
75      ALLOC1_INTERFACE_END(_param->_nb_instruction);
76    }
77
78    // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
79    {
80      ALLOC0_INTERFACE_BEGIN("predict", IN, NORTH, _("Request the prediction unit."));
81
82      ALLOC0_VALACK_OUT (out_PREDICT_VAL                        ,VAL);
83      ALLOC0_VALACK_IN  ( in_PREDICT_ACK                        ,ACK);
84      ALLOC0_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS                ,"pc_previous"                ,Tgeneral_address_t,_param->_size_instruction_address);
85      ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT                 ,"pc_current"                 ,Tgeneral_address_t,_param->_size_instruction_address);
86      ALLOC0_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE      ,"pc_current_is_ds_take"      ,Tcontrol_t        ,1);
87      ALLOC0_SIGNAL_IN  ( in_PREDICT_PC_NEXT                    ,"pc_next"                    ,Tgeneral_address_t,_param->_size_instruction_address);
88      ALLOC0_SIGNAL_IN  ( in_PREDICT_PC_NEXT_IS_DS_TAKE         ,"pc_next_is_ds_take"         ,Tcontrol_t        ,1);
89//    ALLOC0_SIGNAL_IN  ( in_PREDICT_BRANCH_IS_CURRENT          ,"branch_is_current"          ,Tcontrol_t        ,1);
90      ALLOC0_SIGNAL_IN  ( in_PREDICT_BRANCH_STATE               ,"branch_state"               ,Tbranch_state_t   ,_param->_size_branch_state);
91      ALLOC0_SIGNAL_IN  ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
92      ALLOC0_SIGNAL_IN  ( in_PREDICT_INST_IFETCH_PTR            ,"inst_ifetch_ptr"            ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
93
94      ALLOC0_INTERFACE_END();
95    }
96    {
97      ALLOC1_INTERFACE_BEGIN("predict", IN, NORTH, _("Request the prediction unit."),_param->_nb_instruction);
98
99      ALLOC1_SIGNAL_IN (in_PREDICT_INSTRUCTION_ENABLE          ,"instruction_enable"         ,Tcontrol_t        ,1);
100
101      ALLOC1_INTERFACE_END(_param->_nb_instruction);
102    }
103
104    // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
105    {
106      ALLOC0_INTERFACE_BEGIN("event", IN, SOUTH, _("Event (miss, exception ...)"));
107
108      ALLOC0_VALACK_IN ( in_EVENT_VAL          ,VAL);
109      ALLOC0_VALACK_OUT(out_EVENT_ACK          ,ACK);
110      ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS         ,"address"         ,Tgeneral_address_t,_param->_size_instruction_address);
111      ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT    ,"address_next"    ,Tgeneral_address_t,_param->_size_instruction_address);
112      ALLOC0_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL,"address_next_val",Tcontrol_t,1);
113      ALLOC0_SIGNAL_IN ( in_EVENT_IS_DS_TAKE      ,"is_ds_take"      ,Tcontrol_t,1);
114
115      ALLOC0_INTERFACE_END();
116    }
117
118    // ~~~~~[ Internal  ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
119    if (usage_is_set(_usage,USE_SYSTEMC))
120      {
121        ALLOC1(reg_PC_ACCESS_INSTRUCTION_ENABLE ,Tcontrol_t,_param->_nb_instruction);
122        ALLOC1(reg_PC_CURRENT_INSTRUCTION_ENABLE,Tcontrol_t,_param->_nb_instruction);
123        ALLOC1(reg_PC_NEXT_INSTRUCTION_ENABLE   ,Tcontrol_t,_param->_nb_instruction);
124      }
125
126    // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   
127#ifdef POSITION
128     if (usage_is_set(_usage,USE_POSITION))
129       _component->generate_file();
130#endif
131
132    log_printf(FUNC,Address_management,FUNCTION,"End");
133  };
134
135}; // end namespace address_management
136}; // end namespace ifetch_unit
137}; // end namespace front_end
138}; // end namespace multi_front_end
139}; // end namespace core
140
141}; // end namespace behavioural
142}; // end namespace morpheo             
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