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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 15 years ago
Almost complete design with Test and test platform
Property svn:keywords set to `Id`
File size: 19.3 KB

Line
1	/*
2	* $Id: Ifetch_unit_allocation.cpp 88 2008-12-10 18:31:39Z rosiere $
3	*
4	* [ Description ]
5	*
6	*/
7
8	#include "Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/include/Ifetch_unit.h"
9	#include "Behavioural/include/Allocation.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace ifetch_unit {
17
18
19
20	#undef FUNCTION
21	#define FUNCTION "Ifetch_unit::allocation"
22	void Ifetch_unit::allocation (
23	#ifdef STATISTICS
24	morpheo::behavioural::Parameters_Statistics * param_statistics
25	#else
26	void
27	#endif
28	)
29	{
30	log_printf(FUNC,Ifetch_unit,FUNCTION,"Begin");
31
32	_component = new Component (_usage);
33
34	Entity * entity = _component->set_entity (_name
35	,"Ifetch_unit"
36	#ifdef POSITION
37	,COMBINATORY
38	#endif
39	);
40
41	_interfaces = entity->set_interfaces();
42
43	// ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
44	{
45	Interface * interface = _interfaces->set_interface(""
46	#ifdef POSITION
47	,IN
48	,SOUTH,
49	"Generalist interface"
50	#endif
51	);
52
53	in_CLOCK = interface->set_signal_clk ("clock" ,1, CLOCK_VHDL_YES);
54	in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES);
55	}
56
57	// ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
58	{
59	ALLOC_INTERFACE("icache_req",OUT, WEST, _("Instruction cache request."));
60
61	ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL);
62	ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK);
63	//ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id );
64	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr );
65	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address );
66	ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type);
67	}
68
69	// ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
70	{
71	ALLOC_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."));
72
73	ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL);
74	ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK);
75	//ALLOC_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id );
76	ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr );
77	ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error);
78	}
79	{
80	ALLOC1_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction);
81
82	ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction );
83	}
84
85	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
86	{
87	ALLOC_INTERFACE("predict",OUT, NORTH, _("Predict the next pc."));
88
89	ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL);
90	ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK);
91	ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address);
92	ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address);
93	ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1);
94	ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address);
95	ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1);
96	ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
97	ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);
98	ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
99	}
100	{
101	ALLOC1_INTERFACE("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction);
102
103	ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1);
104	}
105
106	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
107	{
108	ALLOC_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."));
109
110	//ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id);
111	ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address);
112	ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr);
113	ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state);
114	ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth);
115	ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch);
116	}
117	{
118	ALLOC1_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction);
119
120	ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL);
121	ALLOC1_VALACK_IN ( in_DECOD_ACK ,ACK);
122	ALLOC1_SIGNAL_OUT(out_DECOD_INSTRUCTION ,"instruction" ,Tinstruction_t ,_param->_size_instruction);
123	}
124
125	// ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
126	{
127	ALLOC_INTERFACE("event",IN , NORTH, _("Event interface."));
128
129	ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL);
130	ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK);
131	ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address);
132	ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address);
133	ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1);
134	ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1);
135	}
136
137	// ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
138	std::string name;
139
140	{
141	name = _name+"_address_management";
142	log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str());
143
144	_component_address_management = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Address_management
145	(name.c_str()
146	#ifdef STATISTICS
147	,param_statistics
148	#endif
149	,_param->_param_address_management
150	,_usage);
151
152	_component->set_component (_component_address_management->_component
153	#ifdef POSITION
154	, 50, 50, 10, 10
155	#endif
156	);
157	}
158
159	{
160	name = _name+"_ifetch_queue";
161	log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str());
162
163	_component_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue
164	(name.c_str()
165	#ifdef STATISTICS
166	,param_statistics
167	#endif
168	,_param->_param_ifetch_queue
169	,_usage);
170
171	_component->set_component (_component_ifetch_queue->_component
172	#ifdef POSITION
173	, 50, 50, 10, 10
174	#endif
175	);
176	}
177
178	{
179	name = _name+"_ifetch_unit_glue";
180	log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str());
181
182	_component_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Ifetch_unit_Glue
183	(name.c_str()
184	#ifdef STATISTICS
185	,param_statistics
186	#endif
187	,_param->_param_ifetch_unit_glue
188	,_usage);
189
190	_component->set_component (_component_ifetch_unit_glue->_component
191	#ifdef POSITION
192	, 50, 50, 10, 10
193	#endif
194	);
195	}
196
197	// ~~~~~[ Instanciation ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
198	std::string src,dest;
199
200	// ===================================================================
201	// =====[ address_management ]========================================
202	// ===================================================================
203	{
204	src = _name+"_address_management";
205	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
206
207	{
208	dest = _name;
209	#ifdef POSITION
210	_component->interface_map (src ,"",
211	dest,"");
212	#endif
213	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
214	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
215	}
216
217	{
218	dest = _name+"_ifetch_queue";
219
220	for (uint32_t i=0; i<_param->_nb_instruction; i++)
221	{
222	#ifdef POSITION
223	_component->interface_map (src ,"address_"+toString(i),
224	dest,"address_"+toString(i));
225	#endif
226	COMPONENT_MAP(_component,src ,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE",
227	dest, "in_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE");
228	}
229
230	if (_param->_have_port_inst_ifetch_ptr)
231	COMPONENT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" ,
232	dest, "in_ADDRESS_INST_IFETCH_PTR" );
233	COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" ,
234	dest, "in_ADDRESS_BRANCH_STATE" );
235	if (_param->_have_port_depth)
236	COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID",
237	dest, "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID");
238
239	dest = _name+"_ifetch_unit_glue";
240
241	#ifdef POSITION
242	_component->interface_map (src ,"address",
243	dest,"address");
244	#endif
245
246	COMPONENT_MAP(_component,src ,"out_ADDRESS_VAL" ,
247	dest, "in_ICACHE_REQ_ADDRESS_VAL");
248	COMPONENT_MAP(_component,src , "in_ADDRESS_ACK" ,
249	dest,"out_ICACHE_REQ_ADDRESS_ACK");
250	COMPONENT_MAP(_component,src ,"out_ADDRESS_INSTRUCTION_ADDRESS",
251	dest, "in_ICACHE_REQ_ADDRESS_ADDRESS");
252	}
253
254	{
255	dest = _name;
256
257	#ifdef POSITION
258	_component->interface_map (src ,"predict",
259	dest,"predict");
260	#endif
261
262	for (uint32_t i=0; i<_param->_nb_instruction; i++)
263	{
264	#ifdef POSITION
265	_component->interface_map (src ,"predict_"+toString(i),
266	dest,"predict_"+toString(i));
267	#endif
268	PORT_MAP(_component,src , "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE"
269	,dest, "in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE" );
270	}
271
272	PORT_MAP(_component,src ,"out_PREDICT_VAL"
273	,dest,"out_PREDICT_VAL" );
274	PORT_MAP(_component,src , "in_PREDICT_ACK"
275	,dest, "in_PREDICT_ACK" );
276	PORT_MAP(_component,src ,"out_PREDICT_PC_PREVIOUS"
277	,dest,"out_PREDICT_PC_PREVIOUS" );
278	PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT"
279	,dest,"out_PREDICT_PC_CURRENT" );
280	PORT_MAP(_component,src ,"out_PREDICT_PC_CURRENT_IS_DS_TAKE"
281	,dest,"out_PREDICT_PC_CURRENT_IS_DS_TAKE" );
282	PORT_MAP(_component,src , "in_PREDICT_PC_NEXT"
283	,dest, "in_PREDICT_PC_NEXT" );
284	PORT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE"
285	,dest, "in_PREDICT_PC_NEXT_IS_DS_TAKE" );
286	if (_param->_have_port_inst_ifetch_ptr)
287	PORT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR"
288	,dest, "in_PREDICT_INST_IFETCH_PTR" );
289	PORT_MAP(_component,src , "in_PREDICT_BRANCH_STATE"
290	,dest, "in_PREDICT_BRANCH_STATE" );
291	if (_param->_have_port_depth)
292	PORT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID"
293	,dest, "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID");
294	}
295
296	{
297	dest = _name+"_ifetch_unit_glue";
298
299	#ifdef POSITION
300	_component->interface_map (src ,"event",
301	dest,"event");
302	_component->interface_map (src ,"event",
303	_name,"event");
304	#endif
305
306	COMPONENT_MAP(_component,src , "in_EVENT_VAL" ,dest ,"out_EVENT_ADDRESS_VAL");
307	COMPONENT_MAP(_component,src ,"out_EVENT_ACK" ,dest , "in_EVENT_ADDRESS_ACK");
308
309
310	dest = _name;
311	PORT_MAP(_component,src , "in_EVENT_ADDRESS" ,dest , "in_EVENT_ADDRESS" );
312	PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT" ,dest , "in_EVENT_ADDRESS_NEXT" );
313	PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT_VAL",dest , "in_EVENT_ADDRESS_NEXT_VAL" );
314	PORT_MAP(_component,src , "in_EVENT_IS_DS_TAKE" ,dest , "in_EVENT_IS_DS_TAKE" );
315	}
316	}
317
318	// ===================================================================
319	// =====[ ifetch_queue ]==============================================
320	// ===================================================================
321	{
322	src = _name+"_ifetch_queue";
323	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
324
325	{
326	dest = _name;
327	#ifdef POSITION
328	_component->interface_map (src ,"",
329	dest,"");
330	#endif
331	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
332	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
333	}
334
335	{
336	dest = _name;
337
338	#ifdef POSITION
339	_component->interface_map (src ,"address",
340	dest,"address");
341	#endif
342
343	if (_param->_have_port_ifetch_queue_ptr)
344	PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" ,
345	dest,"out_ICACHE_REQ_PACKET_ID" );
346
347	for (uint32_t i=0; i<_param->_nb_instruction; i++)
348	{
349	#ifdef POSITION
350	_component->interface_map (src ,"address_"+toString(i),
351	dest+"_address_management","address_"+toString(i));
352	#endif
353
354	//out_ADDRESS_INSTRUCTION_ENABLE - address_management
355	}
356
357	dest = _name+"_ifetch_unit_glue";
358
359	COMPONENT_MAP(_component,src , "in_ADDRESS_VAL" ,
360	dest,"out_ICACHE_REQ_QUEUE_VAL");
361	COMPONENT_MAP(_component,src ,"out_ADDRESS_ACK" ,
362	dest, "in_ICACHE_REQ_QUEUE_ACK");
363	COMPONENT_MAP(_component,src , "in_ADDRESS_INSTRUCTION_ADDRESS",
364	dest,"out_ICACHE_REQ_QUEUE_ADDRESS");
365	// in_ADDRESS_INST_IFETCH_PTR - address_management
366	// in_ADDRESS_BRANCH_STATE - address_management
367	// in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID - address_management
368	}
369
370	{
371	dest = _name;
372
373	#ifdef POSITION
374	_component->interface_map (src ,"icache_rsp",
375	dest,"icache_rsp");
376	#endif
377
378	for (uint32_t i=0; i<_param->_nb_instruction; i++)
379	{
380	#ifdef POSITION
381	_component->interface_map (src ,"icache_rsp_"+toString(i),
382	dest,"icache_rsp_"+toString(i));
383	#endif
384
385	PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_VAL" ,
386	dest,"out_DECOD_"+toString(i)+"_VAL" );
387	PORT_MAP(_component,src , "in_DECOD_"+toString(i)+"_ACK" ,
388	dest, "in_DECOD_"+toString(i)+"_ACK" );
389	PORT_MAP(_component,src ,"out_DECOD_"+toString(i)+"_INSTRUCTION" ,
390	dest,"out_DECOD_"+toString(i)+"_INSTRUCTION" );
391	}
392
393	PORT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest,"out_DECOD_ADDRESS" );
394	if (_param->_have_port_inst_ifetch_ptr)
395	PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest,"out_DECOD_INST_IFETCH_PTR" );
396	PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest,"out_DECOD_BRANCH_STATE" );
397	if (_param->_have_port_depth)
398	PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID");
399	PORT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest,"out_DECOD_EXCEPTION" );
400	}
401
402	{
403	dest = _name;
404
405	#ifdef POSITION
406	_component->interface_map (src ,"icache_rsp",
407	dest,"icache_rsp");
408	#endif
409
410	PORT_MAP(_component,src , "in_ICACHE_RSP_VAL" ,dest, "in_ICACHE_RSP_VAL" );
411	PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK" ,dest,"out_ICACHE_RSP_ACK" );
412	if (_param->_have_port_ifetch_queue_ptr)
413	PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID",dest, "in_ICACHE_RSP_PACKET_ID");
414	PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR" ,dest, "in_ICACHE_RSP_ERROR" );
415
416	for (uint32_t i=0; i<_param->_nb_instruction; i++)
417	{
418	#ifdef POSITION
419	_component->interface_map (src ,"icache_rsp_"+toString(i),
420	dest,"icache_rsp_"+toString(i));
421	#endif
422	PORT_MAP(_component,src , "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION",
423	dest, "in_ICACHE_RSP_"+toString(i)+"_INSTRUCTION");
424	}
425	}
426
427	{
428	dest = _name+"_ifetch_unit_glue";
429
430	#ifdef POSITION
431	_component->interface_map (src ,"event_reset",
432	dest,"event");
433	#endif
434
435	COMPONENT_MAP(_component,src , "in_EVENT_RESET_VAL",dest,"out_EVENT_QUEUE_VAL");
436	COMPONENT_MAP(_component,src ,"out_EVENT_RESET_ACK",dest, "in_EVENT_QUEUE_ACK");
437	}
438	}
439
440	// ===================================================================
441	// =====[ ifetch_unit_glue ]==========================================
442	// ===================================================================
443	{
444	src = _name+"_ifetch_unit_glue";
445	log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str());
446
447	{
448	dest = _name;
449	#ifdef POSITION
450	_component->interface_map (src ,"",
451	dest,"");
452	#endif
453	PORT_MAP(_component,src , "in_CLOCK" ,dest, "in_CLOCK");
454	PORT_MAP(_component,src , "in_NRESET",dest, "in_NRESET");
455	}
456
457	{
458	dest = _name;
459
460	#ifdef POSITION
461	_component->interface_map (src ,"icache_req",
462	dest,"icache_req");
463	#endif
464
465	PORT_MAP(_component,src ,"out_ICACHE_REQ_VAL" ,dest,"out_ICACHE_REQ_VAL");
466	PORT_MAP(_component,src , "in_ICACHE_REQ_ACK" ,dest, "in_ICACHE_REQ_ACK");
467	PORT_MAP(_component,src ,"out_ICACHE_REQ_TYPE" ,dest,"out_ICACHE_REQ_TYPE");
468	PORT_MAP(_component,src ,"out_ICACHE_REQ_ADDRESS",dest,"out_ICACHE_REQ_ADDRESS");
469
470	// in_ICACHE_REQ_ADDRESS_VAL - address_management
471	//out_ICACHE_REQ_QUEUE_VAL - ifetch_queue
472	//out_ICACHE_REQ_ADDRESS_ACK - address_management
473	// in_ICACHE_REQ_QUEUE_ACK - ifetch_queue
474	// in_ICACHE_REQ_ADDRESS_ADDRESS - address_management
475	//out_ICACHE_REQ_QUEUE_ADDRESS - ifetch_queue
476
477	}
478
479	{
480	dest = _name;
481
482	#ifdef POSITION
483	_component->interface_map (src ,"event",
484	dest,"event");
485	#endif
486
487	PORT_MAP(_component,src , "in_EVENT_VAL" ,dest , "in_EVENT_VAL" );
488	PORT_MAP(_component,src ,"out_EVENT_ACK" ,dest ,"out_EVENT_ACK" );
489
490	//out_EVENT_ADDRESS_VAL - address_management
491	//out_EVENT_QUEUE_VAL - ifetch_queue
492	// in_EVENT_ADDRESS_ACK - address_management
493	// in_EVENT_QUEUE_ACK - ifetch_queue
494	}
495	}
496
497	// ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
498	#if DEBUG_Ifetch_unit == true
499	_component->test_map();
500	#endif
501
502	#ifdef POSITION
503	if (usage_is_set(_usage,USE_POSITION))
504	_component->generate_file();
505	#endif
506
507	log_printf(FUNC,Ifetch_unit,FUNCTION,"End");
508	};
509
510	}; // end namespace ifetch_unit
511	}; // end namespace front_end
512	}; // end namespace multi_front_end
513	}; // end namespace core
514
515	}; // end namespace behavioural
516	}; // end namespace morpheo

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