Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (15 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/src/Ifetch_unit_allocation.cpp
r85 r88 57 57 // ~~~~~[ Interface "icache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 58 58 { 59 ALLOC_INTERFACE("icache_req",OUT, WEST, "Instruction cache request.");59 ALLOC_INTERFACE("icache_req",OUT, WEST, _("Instruction cache request.")); 60 60 61 61 ALLOC_VALACK_OUT(out_ICACHE_REQ_VAL ,VAL); 62 62 ALLOC_VALACK_IN ( in_ICACHE_REQ_ACK ,ACK); 63 63 //ALLOC_SIGNAL_OUT(out_ICACHE_REQ_THREAD_ID,"thread_id",Tcontext_t ,_param->_size_context_id ); 64 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ queue_ptr );65 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_ address );64 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_PACKET_ID,"packet_id",Tpacket_t ,_param->_size_ifetch_queue_ptr ); 65 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_ADDRESS ,"address" ,Ticache_instruction_t,_param->_size_instruction_address ); 66 66 ALLOC_SIGNAL_OUT(out_ICACHE_REQ_TYPE ,"type" ,Ticache_type_t ,_param->_size_icache_type); 67 67 } … … 69 69 // ~~~~~[ Interface "icache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 70 70 { 71 ALLOC_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.");71 ALLOC_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons.")); 72 72 73 73 ALLOC_VALACK_IN ( in_ICACHE_RSP_VAL ,VAL); 74 74 ALLOC_VALACK_OUT (out_ICACHE_RSP_ACK ,ACK); 75 75 //ALLOC_SIGNAL_IN ( in_ICACHE_RSP_THREAD_ID ,"thread_id" ,Tcontext_t ,_param->_size_context_id ); 76 ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ queue_ptr );76 ALLOC_SIGNAL_IN ( in_ICACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_ifetch_queue_ptr ); 77 77 ALLOC_SIGNAL_IN ( in_ICACHE_RSP_ERROR ,"error" ,Ticache_error_t ,_param->_size_icache_error); 78 78 } 79 79 { 80 ALLOC1_INTERFACE("icache_rsp",IN , WEST, "Instruction cache respons.",_param->_nb_instruction);80 ALLOC1_INTERFACE("icache_rsp",IN , WEST, _("Instruction cache respons."),_param->_nb_instruction); 81 81 82 82 ALLOC1_SIGNAL_IN ( in_ICACHE_RSP_INSTRUCTION,"instruction",Ticache_instruction_t,_param->_size_instruction ); … … 85 85 // ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 86 86 { 87 ALLOC_INTERFACE("predict",OUT, NORTH, "Acces Instruction cache respons.");87 ALLOC_INTERFACE("predict",OUT, NORTH, _("Predict the next pc.")); 88 88 89 89 ALLOC_VALACK_OUT (out_PREDICT_VAL ,VAL); 90 90 ALLOC_VALACK_IN ( in_PREDICT_ACK ,ACK); 91 ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_ address);92 ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_ address);91 ALLOC_SIGNAL_OUT (out_PREDICT_PC_PREVIOUS ,"pc_previous" ,Tgeneral_address_t,_param->_size_instruction_address); 92 ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT ,"pc_current" ,Tgeneral_address_t,_param->_size_instruction_address); 93 93 ALLOC_SIGNAL_OUT (out_PREDICT_PC_CURRENT_IS_DS_TAKE ,"pc_current_is_ds_take" ,Tcontrol_t ,1); 94 ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_ address);94 ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT ,"pc_next" ,Tgeneral_address_t,_param->_size_instruction_address); 95 95 ALLOC_SIGNAL_IN ( in_PREDICT_PC_NEXT_IS_DS_TAKE ,"pc_next_is_ds_take" ,Tcontrol_t ,1); 96 ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst ruction_ptr);96 ALLOC_SIGNAL_IN ( in_PREDICT_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); 97 97 ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); 98 ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_ branch_update_prediction);99 } 100 { 101 ALLOC1_INTERFACE("predict",IN , NORTH, "Acces Instruction cache respons.",_param->_nb_instruction);98 ALLOC_SIGNAL_IN ( in_PREDICT_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 99 } 100 { 101 ALLOC1_INTERFACE("predict",IN , NORTH, _("Predict the next pc."),_param->_nb_instruction); 102 102 103 103 ALLOC1_SIGNAL_IN ( in_PREDICT_INSTRUCTION_ENABLE ,"instruction_enable" ,Tcontrol_t ,1); … … 106 106 // ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 107 107 { 108 ALLOC_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.");108 ALLOC_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit.")); 109 109 110 110 //ALLOC_SIGNAL_OUT (out_DECOD_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id); 111 ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_ address);112 ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst ruction_ptr);111 ALLOC_SIGNAL_OUT (out_DECOD_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); 112 ALLOC_SIGNAL_OUT (out_DECOD_INST_IFETCH_PTR ,"inst_ifetch_ptr" ,Tinst_ifetch_ptr_t,_param->_size_inst_ifetch_ptr); 113 113 ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_STATE ,"branch_state" ,Tbranch_state_t ,_param->_size_branch_state); 114 ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_ branch_update_prediction);114 ALLOC_SIGNAL_OUT (out_DECOD_BRANCH_UPDATE_PREDICTION_ID,"branch_update_prediction_id",Tprediction_ptr_t ,_param->_size_depth); 115 115 ALLOC_SIGNAL_OUT (out_DECOD_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception_ifetch); 116 116 } 117 117 { 118 ALLOC1_INTERFACE("decod",OUT , EAST, "Send bundle to the decod unit.",_param->_nb_instruction);118 ALLOC1_INTERFACE("decod",OUT , EAST, _("Send bundle to the decod unit."),_param->_nb_instruction); 119 119 120 120 ALLOC1_VALACK_OUT(out_DECOD_VAL ,VAL); … … 125 125 // ~~~~~[ Interface "event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 126 126 { 127 ALLOC_INTERFACE("event",IN , NORTH, "Event interface."); 128 129 ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); 130 ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); 131 ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS,"address",Tgeneral_address_t,_param->_size_address); 127 ALLOC_INTERFACE("event",IN , NORTH, _("Event interface.")); 128 129 ALLOC_VALACK_IN ( in_EVENT_VAL ,VAL); 130 ALLOC_VALACK_OUT(out_EVENT_ACK ,ACK); 131 ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS ,"address" ,Tgeneral_address_t,_param->_size_instruction_address); 132 ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT ,"address_next" ,Tgeneral_address_t,_param->_size_instruction_address); 133 ALLOC_SIGNAL_IN ( in_EVENT_ADDRESS_NEXT_VAL ,"address_next_val",Tcontrol_t,1); 134 ALLOC_SIGNAL_IN ( in_EVENT_IS_DS_TAKE ,"is_ds_take" ,Tcontrol_t,1); 132 135 } 133 136 … … 137 140 { 138 141 name = _name+"_address_management"; 139 std::cout << "Create : " << name << std::endl;142 log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); 140 143 141 144 _component_address_management = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::address_management::Address_management … … 156 159 { 157 160 name = _name+"_ifetch_queue"; 158 std::cout << "Create : " << name << std::endl;161 log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); 159 162 160 163 _component_ifetch_queue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_queue::Ifetch_queue … … 175 178 { 176 179 name = _name+"_ifetch_unit_glue"; 177 std::cout << "Create : " << name << std::endl;180 log_printf(Ifetch_unit,Core,FUNCTION,_("Create : %s"),name.c_str()); 178 181 179 182 _component_ifetch_unit_glue = new morpheo::behavioural::core::multi_front_end::front_end::ifetch_unit::ifetch_unit_glue::Ifetch_unit_Glue … … 200 203 { 201 204 src = _name+"_address_management"; 202 std::cout << "Instance : " << src << std::endl;205 log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); 203 206 204 207 { … … 225 228 } 226 229 227 if (_param->_have_port_inst ruction_ptr)230 if (_param->_have_port_inst_ifetch_ptr) 228 231 COMPONENT_MAP(_component,src ,"out_ADDRESS_INST_IFETCH_PTR" , 229 232 dest, "in_ADDRESS_INST_IFETCH_PTR" ); 230 233 COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_STATE" , 231 234 dest, "in_ADDRESS_BRANCH_STATE" ); 232 if (_param->_have_port_ branch_update_prediction_id)235 if (_param->_have_port_depth) 233 236 COMPONENT_MAP(_component,src ,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID", 234 237 dest, "in_ADDRESS_BRANCH_UPDATE_PREDICTION_ID"); … … 281 284 PORT_MAP(_component,src , "in_PREDICT_PC_NEXT_IS_DS_TAKE" 282 285 ,dest, "in_PREDICT_PC_NEXT_IS_DS_TAKE" ); 283 if (_param->_have_port_inst ruction_ptr)286 if (_param->_have_port_inst_ifetch_ptr) 284 287 PORT_MAP(_component,src , "in_PREDICT_INST_IFETCH_PTR" 285 288 ,dest, "in_PREDICT_INST_IFETCH_PTR" ); 286 289 PORT_MAP(_component,src , "in_PREDICT_BRANCH_STATE" 287 290 ,dest, "in_PREDICT_BRANCH_STATE" ); 288 if (_param->_have_port_ branch_update_prediction_id)291 if (_param->_have_port_depth) 289 292 PORT_MAP(_component,src , "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID" 290 293 ,dest, "in_PREDICT_BRANCH_UPDATE_PREDICTION_ID"); … … 306 309 307 310 dest = _name; 308 PORT_MAP(_component,src , "in_EVENT_ADDRESS",dest, "in_EVENT_ADDRESS"); 311 PORT_MAP(_component,src , "in_EVENT_ADDRESS" ,dest , "in_EVENT_ADDRESS" ); 312 PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT" ,dest , "in_EVENT_ADDRESS_NEXT" ); 313 PORT_MAP(_component,src , "in_EVENT_ADDRESS_NEXT_VAL",dest , "in_EVENT_ADDRESS_NEXT_VAL" ); 314 PORT_MAP(_component,src , "in_EVENT_IS_DS_TAKE" ,dest , "in_EVENT_IS_DS_TAKE" ); 309 315 } 310 316 } … … 315 321 { 316 322 src = _name+"_ifetch_queue"; 317 std::cout << "Instance : " << src << std::endl;323 log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); 318 324 319 325 { … … 335 341 #endif 336 342 337 if (_param->_have_port_ queue_ptr)343 if (_param->_have_port_ifetch_queue_ptr) 338 344 PORT_MAP(_component,src ,"out_ADDRESS_IFETCH_QUEUE_ID" , 339 345 dest,"out_ICACHE_REQ_PACKET_ID" ); … … 386 392 387 393 PORT_MAP(_component,src ,"out_DECOD_ADDRESS" ,dest,"out_DECOD_ADDRESS" ); 388 if (_param->_have_port_inst ruction_ptr)394 if (_param->_have_port_inst_ifetch_ptr) 389 395 PORT_MAP(_component,src ,"out_DECOD_INST_IFETCH_PTR" ,dest,"out_DECOD_INST_IFETCH_PTR" ); 390 396 PORT_MAP(_component,src ,"out_DECOD_BRANCH_STATE" ,dest,"out_DECOD_BRANCH_STATE" ); 391 if (_param->_have_port_ branch_update_prediction_id)397 if (_param->_have_port_depth) 392 398 PORT_MAP(_component,src ,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID",dest,"out_DECOD_BRANCH_UPDATE_PREDICTION_ID"); 393 399 PORT_MAP(_component,src ,"out_DECOD_EXCEPTION" ,dest,"out_DECOD_EXCEPTION" ); … … 404 410 PORT_MAP(_component,src , "in_ICACHE_RSP_VAL" ,dest, "in_ICACHE_RSP_VAL" ); 405 411 PORT_MAP(_component,src ,"out_ICACHE_RSP_ACK" ,dest,"out_ICACHE_RSP_ACK" ); 406 if (_param->_have_port_ queue_ptr)412 if (_param->_have_port_ifetch_queue_ptr) 407 413 PORT_MAP(_component,src , "in_ICACHE_RSP_PACKET_ID",dest, "in_ICACHE_RSP_PACKET_ID"); 408 414 PORT_MAP(_component,src , "in_ICACHE_RSP_ERROR" ,dest, "in_ICACHE_RSP_ERROR" ); … … 437 443 { 438 444 src = _name+"_ifetch_unit_glue"; 439 std::cout << "Instance : " << src << std::endl;445 log_printf(INFO,Core,FUNCTION,_("Instance : %s"),src.c_str()); 440 446 441 447 { … … 490 496 491 497 // ~~~~~[ Others ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 492 if (DEBUG_Ifetch_unit == true) 493 _component->test_map(); 494 495 #ifdef POSITION 496 _component->generate_file(); 498 #if DEBUG_Ifetch_unit == true 499 _component->test_map(); 500 #endif 501 502 #ifdef POSITION 503 if (usage_is_set(_usage,USE_POSITION)) 504 _component->generate_file(); 497 505 #endif 498 506
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