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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp @ 101

Last change on this file since 101 was 101, checked in by rosiere, 15 years ago
1) Add soc test 2) fix bug (Pc management, Decod and execute, Update prediction ...)
Property svn:keywords set to `Id`
File size: 108.6 KB

Line
1	/*
2	* $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10	#define CYCLE_MAX (1024*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	typedef struct
17	{
18	uint32_t ufpt_ptr ;
19	uint32_t upt_ptr ;
20
21	Tcontext_t context ;
22	Taddress_t address_src ;
23	Taddress_t address_dest;
24	Taddress_t address_good;
25	Tbranch_condition_t condition ;
26	Tcontrol_t take ;
27	Tcontrol_t take_good ;
28	Tcontrol_t flag ;
29	Tcontrol_t no_sequence ;
30	Tcontrol_t is_accurate ;
31	Thistory_t history ;
32	Taddress_t ras_address ;
33	Tptr_t ras_index ;
34	Tcontrol_t miss_ifetch ;
35	Tcontrol_t miss_decod ;
36	Tcontrol_t miss_commit ;
37	} request_t;
38
39	void test (string name,
40	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * _param)
41	{
42	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
43
44	#ifdef STATISTICS
45	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
46	#endif
47
48	Tusage_t _usage = USE_ALL;
49
50	// _usage = usage_unset(_usage,USE_SYSTEMC );
51	// _usage = usage_unset(_usage,USE_VHDL );
52	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
53	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
54	// _usage = usage_unset(_usage,USE_POSITION );
55	// _usage = usage_unset(_usage,USE_STATISTICS );
56	// _usage = usage_unset(_usage,USE_INFORMATION );
57
58	Update_Prediction_Table * _Update_Prediction_Table = new Update_Prediction_Table
59	(name.c_str(),
60	#ifdef STATISTICS
61	_parameters_statistics,
62	#endif
63	_param,
64	_usage);
65
66	#ifdef SYSTEMC
67	/*********************************************************************
68	* Déclarations des signaux
69	*********************************************************************/
70	string rename;
71
72	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
73	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
74
75	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
76	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
77	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
78	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ," in_PREDICT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_predict);
79	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ," in_PREDICT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_predict);
80	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_CONDITION ," in_PREDICT_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict);
81	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_LAST_TAKE ," in_PREDICT_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict);
82	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ," in_PREDICT_BTB_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict);
83	ALLOC1_SC_SIGNAL( in_PREDICT_DIR_HISTORY ," in_PREDICT_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_predict);
84	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict);
85	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict);
86	ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict);
87	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ," in_DECOD_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ," in_DECOD_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL( in_DECOD_BTB_CONDITION ," in_DECOD_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL( in_DECOD_BTB_LAST_TAKE ," in_DECOD_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL( in_DECOD_RAS_ADDRESS ," in_DECOD_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_decod);
95	ALLOC1_SC_SIGNAL( in_DECOD_RAS_INDEX ," in_DECOD_RAS_INDEX ",Tptr_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL( in_DECOD_MISS_IFETCH ," in_DECOD_MISS_IFETCH ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL( in_DECOD_MISS_DECOD ," in_DECOD_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_decod);
98	ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod);
99	//ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
100	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
101
102	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
103	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
104	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
105	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
106	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
107	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
108	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
109	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
110	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
111	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
112
113	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
114	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
115	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
116	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
117	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context);
118	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context);
120	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
121
122	ALLOC1_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
123	ALLOC1_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
124	ALLOC1_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
125	ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update);
126	ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update);
127	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update);
128	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update);
129	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,"out_UPDATE_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_update);
130	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_CONDITION ,"out_UPDATE_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
131	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_VAL ,"out_UPDATE_DIR_VAL ",Tcontrol_t ,_param->_nb_inst_update);
132	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update);
133	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update);
134	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update);
135	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update);
136	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update);
137	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update);
138	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);
139
140	ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
141	ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
142	ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context);
143	ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
144
145	ALLOC1_SC_SIGNAL(out_DEPTH_VAL ,"out_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
146	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
147	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
148	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
149	ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
150
151	/********************************************************
152	* Instanciation
153	********************************************************/
154
155	msg(_("<%s> : Instanciation of _Update_Prediction_Table.\n"),name.c_str());
156
157	((_Update_Prediction_Table->in_CLOCK)) ((in_CLOCK));
158	((_Update_Prediction_Table->in_NRESET)) ((in_NRESET));
159
160	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_VAL ,_param->_nb_inst_predict);
161	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_ACK ,_param->_nb_inst_predict);
162	if (_param->_have_port_context_id)
163	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
164	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict);
165	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict);
166	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict);
167	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict);
168	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict);
169	if (_param->_have_port_history)
170	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict);
171	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict);
172	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict);
173	if (_param->_have_port_depth)
174	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict);
175	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod);
176	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod);
177	if (_param->_have_port_context_id)
178	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
179	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod);
180	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod);
181	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod);
182	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod);
183	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod);
184	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_INDEX ,_param->_nb_inst_decod);
185	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod);
186	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod);
187	if (_param->_have_port_depth)
188	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod);
189	//if (_param->_have_port_depth)
190	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod);
191	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
192	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
193	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
194	if (_param->_have_port_context_id)
195	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
196	if (_param->_have_port_depth)
197	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
198	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
199	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
200	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
201	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
202	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
203	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
204
205	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context);
206	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context);
207	//if (_param->_have_port_context_id)
208	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
209	if (_param->_have_port_depth)
210	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_DEPTH ,_param->_nb_context);
211	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
212	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
213	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
214	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
215
216	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_VAL ,_param->_nb_inst_update);
217	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_UPDATE_ACK ,_param->_nb_inst_update);
218	if (_param->_have_port_context_id)
219	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
220	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update);
221	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update);
222	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update);
223	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update);
224	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update);
225	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update);
226	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_VAL ,_param->_nb_inst_update);
227	if (_param->_have_port_history)
228	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update);
229	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update);
230	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update);
231	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update);
232	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update);
233	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update);
234	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update);
235	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context);
236	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context);
237	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context);
238	if (_param->_have_port_depth)
239	{
240	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context);
241	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context);
242	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context);
243	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context);
244	}
245	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_VAL ,_param->_nb_context);
246	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_FULL ,_param->_nb_context);
247
248	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
249
250	Time * _time = new Time();
251
252	/********************************************************
253	* Simulation - Begin
254	********************************************************/
255
256	// Initialisation
257
258	const uint32_t seed = 0;
259	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
260
261	srand(seed);
262
263	const int32_t percent_transaction_predict = 75;
264	const int32_t percent_transaction_decod = 75;
265	const int32_t percent_transaction_branch_complete = 75;
266	const int32_t percent_transaction_update = 75;
267	const int32_t percent_transaction_branch_event = 75;
268
269	const bool test1 = true;
270	const bool test2 = true;
271	const bool test3 = true;
272	const bool test4 = true;
273
274	std::list<request_t> ufpt;
275	std::list<request_t> upt;
276	request_t event;
277
278	SC_START(0);
279	LABEL("Initialisation");
280
281	LABEL("Reset");
282	in_NRESET->write(0);
283	SC_START(5);
284	in_NRESET->write(1);
285
286	Tdepth_t ufpt_bottom [_param->_nb_context];
287	Tdepth_t ufpt_top [_param->_nb_context];
288
289	Tdepth_t upt_bottom [_param->_nb_context];
290	Tdepth_t upt_top [_param->_nb_context];
291	Tdepth_t upt_top_event[_param->_nb_context];
292
293	for (uint32_t i=0; i<_param->_nb_context; ++i)
294	{
295	ufpt_bottom [i] = 0;
296	ufpt_top [i] = 0;
297	upt_bottom [i] = 0;
298	upt_top [i] = 0;
299	upt_top_event[i] = 0;
300	}
301
302	for (uint32_t i=0; i<_param->_nb_context; ++i)
303	{
304	TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]);
305	TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]);
306	TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]);
307	}
308
309	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
310	{
311	LABEL("Iteration %d",iteration);
312
313	for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
314	in_PREDICT_VAL [i]->write(0);
315	for (uint32_t i=0; i<_param->_nb_inst_decod; ++i)
316	in_DECOD_VAL [i]->write(0);
317	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
318	in_BRANCH_COMPLETE_VAL [i]->write(0);
319	for (uint32_t i=0; i<_param->_nb_context; ++i)
320	in_BRANCH_EVENT_ACK [i]->write(0);
321	for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
322	in_UPDATE_ACK [i]->write(0);
323	for (uint32_t i=0; i<_param->_nb_context; ++i)
324	in_EVENT_VAL [i]->write(0);
325
326	//---------------------------------------------------------------------
327	//---------------------------------------------------------------------
328	// COMMON CASE
329	//---------------------------------------------------------------------
330	//---------------------------------------------------------------------
331	if (test1)
332	{
333	uint32_t context = rand() % _param->_nb_context;
334
335	{
336	LABEL("PREDICT - fill the queue");
337	uint32_t port = rand() % _param->_nb_inst_predict;
338
339	LABEL(" * context : %d",context);
340	LABEL(" * port : %d",port);
341
342	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
343	{
344	request_t request;
345	request.context = context;
346	request.address_src = 0xdeadbeef+i;
347	request.address_dest = 0x21071981+i;
348	request.address_good = request.address_dest;
349	request.condition = BRANCH_CONDITION_FLAG_SET;
350	request.take = 1;
351	request.take_good = 1;
352	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
353	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
354	request.is_accurate = true;
355	request.miss_ifetch = false;
356	request.miss_decod = false;
357	request.miss_commit = false;
358	request.history = i;
359	request.ras_address = 0xdeaddead+i;
360	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
361	request.ufpt_ptr = ufpt_top [context];
362	// request.upt_ptr;
363
364	bool have_transaction = false;
365	do
366	{
367	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
368	in_PREDICT_CONTEXT_ID [port]->write(request.context );
369	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
370	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
371	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
372	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
373	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
374	in_PREDICT_DIR_HISTORY [port]->write(request.history );
375	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
376	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
377
378	if (_param->_have_port_depth)
379	{
380	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
381	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
382	}
383	SC_START(0); // fct melay
384
385	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
386	port,
387	in_PREDICT_VAL [port]->read(),
388	out_PREDICT_ACK [port]->read(),
389	in_PREDICT_BTB_IS_ACCURATE [port]->read());
390
391	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
392	{
393	LABEL("PREDICT [%d] - Transaction accepted",port);
394	have_transaction = true;
395
396	if (_param->_have_port_depth)
397	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
398
399	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
400	}
401
402	SC_START(1); // transition
403
404	} while (not have_transaction);
405
406	ufpt.push_back(request);
407
408	in_PREDICT_VAL [port]->write(0);
409
410	if (_param->_have_port_depth)
411	{
412	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
413	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
414	}
415	}
416	}
417
418	{
419	LABEL("DECOD");
420	uint32_t port = rand() % _param->_nb_inst_decod;
421
422	LABEL(" * context : %d",context);
423	LABEL(" * port : %d",port);
424
425	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
426	{
427	request_t request = ufpt.front();
428
429	bool have_transaction = false;
430	do
431	{
432	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
433	in_DECOD_CONTEXT_ID [port]->write(request.context );
434	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
435	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
436	in_DECOD_BTB_CONDITION [port]->write(request.condition );
437	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
438	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
439	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
440	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
441	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
442	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
443	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
444
445	SC_START(0); // fct melay
446
447	LABEL("DECOD [%d] %d - %d",
448	port,
449	in_PREDICT_VAL [port]->read(),
450	out_PREDICT_ACK [port]->read());
451
452	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
453	{
454	LABEL("DECOD [%d] - Transaction accepted",port);
455	have_transaction = true;
456
457	request.upt_ptr = upt_top [context];
458	upt.push_back(request);
459	ufpt.pop_front();
460
461	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
462	}
463
464	SC_START(1); // transition
465
466	} while (not have_transaction);
467
468	in_DECOD_VAL [port]->write(0);
469
470	if (_param->_have_port_depth)
471	{
472	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
473	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
474	}
475	}
476	}
477
478	{
479	LABEL("BRANCH_COMPLETE - hit ifetch");
480
481	uint32_t port = rand() % _param->_nb_inst_branch_complete;
482
483	LABEL(" * port : %d",port);
484
485	std::list<request_t>::iterator it_upt = upt.begin();
486
487	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
488	for (uint32_t i=0; i<upt.size(); i++)
489	{
490	bool have_transaction = false;
491
492	do
493	{
494	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
495	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
496	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
497	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
498	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
499
500	if (_param->_have_port_depth)
501	{
502	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
503	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
504	}
505
506	SC_START(0);
507
508	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
509
510	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
511	{
512	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
513	have_transaction = true;
514
515	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
516	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
517	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
518	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
519
520	it_upt ++;
521	}
522
523	SC_START(1);
524	} while (not have_transaction);
525
526	in_BRANCH_COMPLETE_VAL [port]->write(0);
527
528	if (_param->_have_port_depth)
529	{
530	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
531	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
532	}
533	}
534	}
535
536	{
537	LABEL("UPDATE - hit ifetch");
538
539	uint32_t port = 0;
540
541	LABEL(" * port : %d",port);
542	std::list<request_t>::iterator it_upt = upt.begin();
543
544	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
545	for (uint32_t i=0; i<upt.size(); i++)
546	{
547	bool have_transaction = false;
548
549	do
550	{
551	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
552
553	// if (_param->_have_port_depth)
554	// {
555	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
556	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
557	// }
558
559	SC_START(0);
560
561	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
562
563	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
564	{
565	LABEL("UPDATE [%d] - Transaction accepted",port);
566	have_transaction = true;
567
568	if (_param->_have_port_context_id)
569	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
570	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
571	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
572	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
573	if (update_btb(it_upt->condition))
574	{
575	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
576	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
577	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
578	}
579	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
580	if (update_dir(it_upt->condition))
581	if (_param->_have_port_history)
582	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
583	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
584	if (update_ras(it_upt->condition))
585	{
586	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
587	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
588	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
589	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
590	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
591	}
592	++ it_upt;
593	}
594
595	SC_START(1);
596	} while (not have_transaction);
597
598	in_UPDATE_ACK [port]->write(0);
599	// if (_param->_have_port_depth)
600	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
601	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
602	}
603	upt.clear();
604	}
605
606	// Wait Garbage Collector
607	{
608	upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context];
609	// upt_top [context] = (upt_top [context]);
610
611	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
612	(upt_top [context] != out_DEPTH_MAX [context]->read()))
613	SC_START(1);
614
615	}
616	}
617
618	//---------------------------------------------------------------------
619	//---------------------------------------------------------------------
620	// DECOD MISS : no RAS in ifetch
621	//---------------------------------------------------------------------
622	//---------------------------------------------------------------------
623	if (test2)
624	{
625	uint32_t context = rand() % _param->_nb_context;
626
627	{
628	LABEL("PREDICT - fill the queue");
629	uint32_t port = rand() % _param->_nb_inst_predict;
630
631	LABEL(" * context : %d",context);
632	LABEL(" * port : %d",port);
633
634	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
635	{
636	request_t request;
637	request.context = context;
638	request.address_src = 0xdeadbeef+i;
639	request.address_dest = 0x21071981+i;
640	request.address_good = request.address_dest;
641	request.condition = BRANCH_CONDITION_FLAG_SET;
642	request.take = 1;
643	request.take_good = 1;
644	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
645	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
646	request.is_accurate = true;
647	request.miss_ifetch = false;
648	request.miss_decod = false;
649	request.miss_commit = false;
650	request.history = i;
651	request.ras_address = 0xdeaddead+i;
652	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
653	request.ufpt_ptr = ufpt_top [context];
654	// request.upt_ptr;
655
656	bool have_transaction = false;
657	do
658	{
659	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
660	in_PREDICT_CONTEXT_ID [port]->write(request.context );
661	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
662	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
663	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
664	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
665	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
666	in_PREDICT_DIR_HISTORY [port]->write(request.history );
667	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
668	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
669
670	if (_param->_have_port_depth)
671	{
672	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
673	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
674	}
675	SC_START(0); // fct melay
676
677	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
678	port,
679	in_PREDICT_VAL [port]->read(),
680	out_PREDICT_ACK [port]->read(),
681	in_PREDICT_BTB_IS_ACCURATE [port]->read());
682
683	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
684	{
685	LABEL("PREDICT [%d] - Transaction accepted",port);
686	have_transaction = true;
687
688	if (_param->_have_port_depth)
689	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
690
691	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
692	}
693
694	SC_START(1); // transition
695
696	} while (not have_transaction);
697
698	// ufpt.push_back(request);
699
700	in_PREDICT_VAL [port]->write(0);
701
702	if (_param->_have_port_depth)
703	{
704	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
705	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
706	}
707	}
708	}
709
710	{
711	LABEL("DECOD - Miss");
712	uint32_t port = rand() % _param->_nb_inst_decod;
713
714	LABEL(" * context : %d",context);
715	LABEL(" * port : %d",port);
716
717	request_t request;
718	request.context = context;
719	request.address_src = 0x14011959;
720	request.address_dest = 0x25071959; // after = not take
721	request.address_good = request.address_dest;
722	request.condition = BRANCH_CONDITION_FLAG_SET;
723	request.take = 0;
724	request.take_good = 0;
725	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
726	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
727	request.is_accurate = true;
728	request.miss_ifetch = false;
729	request.miss_decod = true ;
730	request.miss_commit = false;
731	request.history = 1;
732	request.ras_address = 0xbabababa;
733	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
734	request.ufpt_ptr = ufpt_top [context];
735	request.upt_ptr = upt_top [context];
736
737	event = request;
738
739	// for (uint32_t i=0; i<upt.size(); i++)
740	// just one
741	{
742	bool have_transaction = false;
743	do
744	{
745	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
746	in_DECOD_CONTEXT_ID [port]->write(request.context );
747	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
748	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
749	in_DECOD_BTB_CONDITION [port]->write(request.condition );
750	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
751	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
752	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
753	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
754	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
755	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
756	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
757
758	SC_START(0); // fct melay
759
760	LABEL("DECOD [%d] %d - %d",
761	port,
762	in_PREDICT_VAL [port]->read(),
763	out_PREDICT_ACK [port]->read());
764
765	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
766	{
767	LABEL("DECOD [%d] - Transaction accepted",port);
768	have_transaction = true;
769
770	request.upt_ptr = upt_top [context];
771	upt.push_back(request);
772	// ufpt.pop_front();
773
774	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
775	}
776
777	SC_START(1); // transition
778
779	} while (not have_transaction);
780
781	in_DECOD_VAL [port]->write(0);
782
783	if (_param->_have_port_depth)
784	{
785	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
786	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
787	}
788	}
789	}
790
791	{
792	LABEL("BRANCH_COMPLETE - hit ifetch");
793
794	uint32_t port = rand() % _param->_nb_inst_branch_complete;
795
796	LABEL(" * port : %d",port);
797
798	std::list<request_t>::iterator it_upt = upt.begin();
799
800	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
801	// for (uint32_t i=0; i<upt.size(); i++)
802	// just one
803	{
804	bool have_transaction = false;
805
806	do
807	{
808	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
809	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
810	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
811	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
812	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
813
814	if (_param->_have_port_depth)
815	{
816	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
817	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
818	}
819	SC_START(0);
820
821	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
822
823	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
824	{
825	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
826	have_transaction = true;
827
828	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
829	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
830	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
831	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
832
833	it_upt ++;
834	}
835
836	SC_START(1);
837	} while (not have_transaction);
838
839	in_BRANCH_COMPLETE_VAL [port]->write(0);
840
841	if (_param->_have_port_depth)
842	{
843	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
844	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
845	}
846	}
847	}
848
849	{
850	LABEL("UPDATE - hit ifetch");
851
852	uint32_t port = 0;
853
854	LABEL(" * port : %d",port);
855	std::list<request_t>::iterator it_upt = upt.begin();
856
857	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
858	// for (uint32_t i=0; i<upt.size(); i++)
859	// just one
860	{
861	bool have_transaction = false;
862
863	do
864	{
865	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
866
867	// if (_param->_have_port_depth)
868	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
869	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
870
871	SC_START(0);
872
873	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
874
875	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
876	{
877	LABEL("UPDATE [%d] - Transaction accepted",port);
878	have_transaction = true;
879
880	if (_param->_have_port_context_id)
881	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
882	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
883	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
884	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
885	if (update_btb(it_upt->condition))
886	{
887	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
888	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
889	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
890	}
891	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
892
893	if (update_dir(it_upt->condition))
894	if (_param->_have_port_history)
895	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
896	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
897	if (update_ras(it_upt->condition))
898	{
899	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
900	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
901	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
902	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
903	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
904	}
905	++ it_upt;
906	}
907
908	SC_START(1);
909	} while (not have_transaction);
910
911	in_UPDATE_ACK [port]->write(0);
912	// if (_param->_have_port_depth)
913	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
914	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
915	}
916	upt.clear();
917	}
918
919	{
920	LABEL("BRANCH_EVENT - have miss decod");
921
922	uint32_t port = context;
923
924	{
925	bool have_transaction = false;
926
927	do
928	{
929	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
930
931	SC_START(0);
932
933	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
934
935	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
936	{
937	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
938	have_transaction = true;
939
940	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
941	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
942	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
943	if (event.take)
944	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
945
946	event.address_src = 0;
947	event.take = 0;
948	event.address_dest = 0;
949	}
950
951	SC_START(1);
952	} while (not have_transaction);
953
954	in_BRANCH_EVENT_ACK [port]->write(0);
955	}
956	}
957
958	{
959	LABEL("EVENT_STATE");
960
961	SC_START(1);
962	in_EVENT_VAL [context]->write(1);
963	in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION);
964
965	SC_START(1);
966	in_EVENT_VAL [context]->write(0);
967	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
968	}
969
970	// Wait Garbage Collector
971	{
972	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
973	// upt_top [context] = (upt_top [context]);
974
975	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
976	(upt_top [context] != out_DEPTH_MAX [context]->read()))
977	SC_START(1);
978
979	}
980	}
981
982	//---------------------------------------------------------------------
983	//---------------------------------------------------------------------
984	// DECOD MISS : with RAS in ifetch
985	//---------------------------------------------------------------------
986	//---------------------------------------------------------------------
987	if (test3)
988	{
989	uint32_t context = rand() % _param->_nb_context;
990	uint32_t have_ras = false;
991	{
992	LABEL("PREDICT - fill the queue");
993	uint32_t port = rand() % _param->_nb_inst_predict;
994
995	LABEL(" * context : %d",context);
996	LABEL(" * port : %d",port);
997
998	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
999	{
1000	request_t request;
1001	request.context = context;
1002	request.address_src = 0xdeadbeef+i;
1003	request.address_dest = 0x21071981+i;
1004	request.address_good = request.address_dest;
1005	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
1006
1007	have_ras \|= (update_ras(request.condition));
1008
1009	request.take = 1;
1010	request.take_good = 1;
1011	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1012	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1013	request.is_accurate = true;
1014	request.miss_ifetch = false;
1015	request.miss_decod = true ;
1016	request.miss_commit = false;
1017	request.history = i;
1018	request.ras_address = 0x12344321+i;
1019	request.ras_index = (043211234+i)%_param->_size_ras_index[context];
1020	request.ufpt_ptr = ufpt_top [context];
1021	// request.upt_ptr;
1022
1023	bool have_transaction = false;
1024	do
1025	{
1026	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1027	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1028	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1029	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1030	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1031	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1032	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1033	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1034	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1035	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1036
1037	if (_param->_have_port_depth)
1038	{
1039	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1040	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1041	}
1042	SC_START(0); // fct melay
1043
1044	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1045	port,
1046	in_PREDICT_VAL [port]->read(),
1047	out_PREDICT_ACK [port]->read(),
1048	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1049
1050	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1051	{
1052	LABEL("PREDICT [%d] - Transaction accepted",port);
1053	have_transaction = true;
1054
1055	if (_param->_have_port_depth)
1056	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1057
1058	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1059	}
1060
1061	SC_START(1); // transition
1062
1063	} while (not have_transaction);
1064
1065	ufpt.push_back(request); // to update
1066
1067	in_PREDICT_VAL [port]->write(0);
1068
1069	if (_param->_have_port_depth)
1070	{
1071	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1072	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1073	}
1074	}
1075	}
1076
1077	{
1078	LABEL("DECOD - Miss");
1079	uint32_t port = rand() % _param->_nb_inst_decod;
1080
1081	LABEL(" * context : %d",context);
1082	LABEL(" * port : %d",port);
1083
1084	request_t request;
1085	request.context = context;
1086	request.address_src = 0x14011959;
1087	request.address_dest = 0x25071959; // after = not take
1088	request.address_good = request.address_dest;
1089	request.condition = BRANCH_CONDITION_FLAG_SET;
1090	request.take = 0;
1091	request.take_good = 0;
1092	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1093	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1094	request.is_accurate = true;
1095	request.miss_ifetch = false;
1096	request.miss_decod = true ;
1097	request.miss_commit = false;
1098	request.history = 1;
1099	request.ras_address = 0xbabababa;
1100	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
1101	request.ufpt_ptr = ufpt_top [context];
1102	request.upt_ptr = upt_top [context];
1103
1104	event = request;
1105
1106	// for (uint32_t i=0; i<upt.size(); i++)
1107	// just one
1108	{
1109	bool have_transaction = false;
1110	do
1111	{
1112	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1113	in_DECOD_CONTEXT_ID [port]->write(request.context );
1114	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1115	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1116	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1117	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1118	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1119	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1120	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1121	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1122	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1123	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1124
1125	SC_START(0); // fct melay
1126
1127	LABEL("DECOD [%d] %d - %d",
1128	port,
1129	in_PREDICT_VAL [port]->read(),
1130	out_PREDICT_ACK [port]->read());
1131
1132	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1133	{
1134	LABEL("DECOD [%d] - Transaction accepted",port);
1135	have_transaction = true;
1136
1137	request.upt_ptr = upt_top [context];
1138	upt.push_back(request);
1139	// ufpt.pop_front();
1140
1141	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1142	}
1143
1144	SC_START(1); // transition
1145
1146	} while (not have_transaction);
1147
1148	in_DECOD_VAL [port]->write(0);
1149
1150	if (_param->_have_port_depth)
1151	{
1152	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1153	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1154	}
1155	}
1156	}
1157
1158	{
1159	LABEL("BRANCH_COMPLETE - hit ifetch");
1160
1161	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1162
1163	LABEL(" * port : %d",port);
1164
1165	std::list<request_t>::iterator it_upt = upt.begin();
1166
1167	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1168	// for (uint32_t i=0; i<upt.size(); i++)
1169	// just one
1170	{
1171	bool have_transaction = false;
1172
1173	do
1174	{
1175	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1176	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1177	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1178	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
1179	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1180
1181	if (_param->_have_port_depth)
1182	{
1183	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1184	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1185	}
1186	SC_START(0);
1187
1188	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1189
1190	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1191	{
1192	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1193	have_transaction = true;
1194
1195	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1196	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
1197	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1198	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
1199
1200	it_upt ++;
1201	}
1202
1203	SC_START(1);
1204	} while (not have_transaction);
1205
1206	in_BRANCH_COMPLETE_VAL [port]->write(0);
1207
1208	if (_param->_have_port_depth)
1209	{
1210	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1211	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1212	}
1213	}
1214	}
1215
1216	if (have_ras)
1217	{
1218	LABEL("UPDATE - Update UPFT");
1219
1220	uint32_t port = 0;
1221
1222	LABEL(" * port : %d",port);
1223	std::list<request_t>::iterator it_ufpt = ufpt.end();
1224	-- it_ufpt;
1225
1226	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1227	{
1228	bool have_transaction = false;
1229
1230	do
1231	{
1232	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1233
1234	// if (_param->_have_port_depth)
1235	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1236	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1237
1238	SC_START(0);
1239
1240	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1241
1242	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1243	{
1244	LABEL("UPDATE [%d] - Transaction accepted",port);
1245	have_transaction = true;
1246
1247	if (_param->_have_port_context_id)
1248	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1249	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1250	it_ufpt->miss_decod or
1251	it_ufpt->miss_commit ));
1252	// if (update_btb(it_ufpt->condition) or
1253	// update_dir(it_ufpt->condition))
1254	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1255	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1256	// if (update_btb(it_ufpt->condition))
1257	// {
1258	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1259	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1260	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1261	// }
1262	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1263
1264	// if (update_dir(it_ufpt->condition))
1265	// if (_param->_have_port_history)
1266	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1267	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1268	if (update_ras(it_ufpt->condition))
1269	{
1270	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1271	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1272	LABEL("KANE : out_UPDATE_RAS_ADDRESS [port]->read() : %.8x",out_UPDATE_RAS_ADDRESS [port]->read());
1273	LABEL("KANE : it_ufpt->ras_address : %.8x",it_ufpt->ras_address);
1274
1275	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1276	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1277	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1278	}
1279	}
1280
1281	SC_START(1);
1282	} while (not have_transaction);
1283
1284	-- it_ufpt;
1285
1286
1287	in_UPDATE_ACK [port]->write(0);
1288	// if (_param->_have_port_depth)
1289	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1290	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1291	}
1292	}
1293	ufpt.clear();
1294
1295	{
1296	LABEL("UPDATE - hit ifetch");
1297
1298	uint32_t port = 0;
1299
1300	LABEL(" * port : %d",port);
1301	std::list<request_t>::iterator it_upt = upt.begin();
1302
1303	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1304	// for (uint32_t i=0; i<upt.size(); i++)
1305	// just one
1306	{
1307	bool have_transaction = false;
1308
1309	do
1310	{
1311	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1312
1313	// if (_param->_have_port_depth)
1314	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1315	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1316
1317	SC_START(0);
1318
1319	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1320
1321	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1322	{
1323	LABEL("UPDATE [%d] - Transaction accepted",port);
1324	have_transaction = true;
1325
1326	if (_param->_have_port_context_id)
1327	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1328	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1329	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1330	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1331	if (update_btb(it_upt->condition))
1332	{
1333	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1334	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1335	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1336	}
1337	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1338
1339	if (update_dir(it_upt->condition))
1340	if (_param->_have_port_history)
1341	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1342	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1343	if (update_ras(it_upt->condition))
1344	{
1345	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1346	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1347	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1348	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1349	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1350	}
1351	++ it_upt;
1352	}
1353
1354	SC_START(1);
1355	} while (not have_transaction);
1356
1357	in_UPDATE_ACK [port]->write(0);
1358	// if (_param->_have_port_depth)
1359	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1360	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1361	}
1362	}
1363	upt.clear();
1364
1365	{
1366	LABEL("BRANCH_EVENT - have miss decod");
1367
1368	uint32_t port = context;
1369
1370	{
1371	bool have_transaction = false;
1372
1373	do
1374	{
1375	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1376
1377	SC_START(0);
1378
1379	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1380
1381	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1382	{
1383	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1384	have_transaction = true;
1385
1386	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
1387	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1388	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
1389	if (event.take)
1390	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1391
1392	event.address_src = 0;
1393	event.take = 0;
1394	event.address_dest = 0;
1395	}
1396
1397	SC_START(1);
1398	} while (not have_transaction);
1399
1400	in_BRANCH_EVENT_ACK [port]->write(0);
1401	}
1402	}
1403
1404	{
1405	LABEL("EVENT_STATE");
1406
1407	SC_START(1);
1408	in_EVENT_VAL [context]->write(1);
1409	in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION);
1410
1411	SC_START(1);
1412	in_EVENT_VAL [context]->write(0);
1413	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
1414	}
1415
1416	// Wait Garbage Collector
1417	{
1418	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
1419	// upt_top [context] = (upt_top [context]);
1420
1421	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
1422	(upt_top [context] != out_DEPTH_MAX [context]->read()))
1423	SC_START(1);
1424
1425	}
1426	}
1427
1428	//---------------------------------------------------------------------
1429	//---------------------------------------------------------------------
1430	// COMMIT MISS : with RAS in UPFT and UPT
1431	//---------------------------------------------------------------------
1432	//---------------------------------------------------------------------
1433	if (test4)
1434	{
1435	uint32_t context = rand() % _param->_nb_context;
1436	uint32_t have_ufpt_ras = false;
1437	uint32_t have_upt_ras = false;
1438	{
1439	LABEL("PREDICT - fill the queue");
1440	uint32_t port = rand() % _param->_nb_inst_predict;
1441
1442	LABEL(" * context : %d",context);
1443	LABEL(" * port : %d",port);
1444
1445	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1446	{
1447	request_t request;
1448	request.context = context;
1449	request.address_src = rand();
1450	request.address_dest = rand();
1451
1452	request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET;
1453
1454	request.take = 1;
1455	request.take_good = 1;
1456	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1457	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1458	request.is_accurate = true ;
1459	request.miss_ifetch = false;
1460	request.miss_decod = false;
1461	request.miss_commit = false;
1462	request.history = i;
1463	request.ras_address = rand();
1464	request.ras_index = rand()%_param->_size_ras_index[context];
1465	request.ufpt_ptr = ufpt_top [context];
1466	// request.upt_ptr;
1467
1468	bool have_transaction = false;
1469	do
1470	{
1471	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1472	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1473	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1474	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1475	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1476	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1477	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1478	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1479	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1480	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1481
1482	if (_param->_have_port_depth)
1483	{
1484	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1485	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1486	}
1487	SC_START(0); // fct melay
1488
1489	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1490	port,
1491	in_PREDICT_VAL [port]->read(),
1492	out_PREDICT_ACK [port]->read(),
1493	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1494
1495	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1496	{
1497	LABEL("PREDICT [%d] - Transaction accepted",port);
1498	have_transaction = true;
1499
1500	if (_param->_have_port_depth)
1501	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1502
1503	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1504	}
1505
1506	SC_START(1); // transition
1507
1508	} while (not have_transaction);
1509
1510	ufpt.push_back(request); // to update
1511
1512	in_PREDICT_VAL [port]->write(0);
1513
1514	if (_param->_have_port_depth)
1515	{
1516	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1517	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1518	}
1519	}
1520	}
1521
1522	{
1523	LABEL("DECOD");
1524	uint32_t port = rand() % _param->_nb_inst_decod;
1525
1526	LABEL(" * context : %d",context);
1527	LABEL(" * port : %d",port);
1528
1529	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1530	{
1531	request_t request = ufpt.front();
1532
1533	bool have_transaction = false;
1534	do
1535	{
1536	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1537	in_DECOD_CONTEXT_ID [port]->write(request.context );
1538	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1539	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1540	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1541	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1542	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1543	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1544	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1545	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1546	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1547	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1548
1549	have_upt_ras \|= (update_ras(request.condition));
1550
1551	SC_START(0); // fct melay
1552
1553	LABEL("DECOD [%d] %d - %d",
1554	port,
1555	in_DECOD_VAL [port]->read(),
1556	out_DECOD_ACK [port]->read());
1557
1558	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1559	{
1560	LABEL("DECOD [%d] - Transaction accepted",port);
1561	have_transaction = true;
1562
1563	request.upt_ptr = upt_top [context];
1564	upt.push_back(request);
1565	ufpt.pop_front();
1566
1567	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1568	}
1569
1570	SC_START(1); // transition
1571
1572	} while (not have_transaction);
1573
1574	in_DECOD_VAL [port]->write(0);
1575
1576	if (_param->_have_port_depth)
1577	{
1578	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1579	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1580	}
1581	}
1582	}
1583
1584	{
1585	LABEL("PREDICT - fill the queue");
1586	uint32_t port = rand() % _param->_nb_inst_predict;
1587
1588	LABEL(" * context : %d",context);
1589	LABEL(" * port : %d",port);
1590
1591	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1592	{
1593	request_t request;
1594	request.context = context;
1595	request.address_src = rand();
1596	request.address_dest = rand();
1597	request.address_good = request.address_dest;
1598	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
1599
1600	have_ufpt_ras \|= (update_ras(request.condition));
1601
1602	request.take = 1;
1603	request.take_good = 1;
1604	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1605	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1606	request.is_accurate = true ;
1607	request.miss_ifetch = false;
1608	request.miss_decod = false;
1609	request.miss_commit = true;
1610	request.history = i;
1611	request.ras_address = rand();
1612	request.ras_index = rand()%_param->_size_ras_index[context];
1613	request.ufpt_ptr = ufpt_top [context];
1614	// request.upt_ptr;
1615
1616	bool have_transaction = false;
1617	do
1618	{
1619	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1620	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1621	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1622	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1623	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1624	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1625	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1626	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1627	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1628	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1629
1630	if (_param->_have_port_depth)
1631	{
1632	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1633	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1634	}
1635	SC_START(0); // fct melay
1636
1637	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1638	port,
1639	in_PREDICT_VAL [port]->read(),
1640	out_PREDICT_ACK [port]->read(),
1641	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1642
1643	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1644	{
1645	LABEL("PREDICT [%d] - Transaction accepted",port);
1646	have_transaction = true;
1647
1648	if (_param->_have_port_depth)
1649	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1650
1651	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1652	}
1653
1654	SC_START(1); // transition
1655
1656	} while (not have_transaction);
1657
1658	ufpt.push_back(request); // to update
1659
1660	in_PREDICT_VAL [port]->write(0);
1661
1662	if (_param->_have_port_depth)
1663	{
1664	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1665	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1666	}
1667	}
1668	}
1669
1670	std::list<request_t>::iterator it_event;
1671	{
1672	LABEL("BRANCH_COMPLETE - Miss ifetch");
1673
1674	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1675
1676	LABEL(" * port : %d",port);
1677
1678	// middle
1679	it_event = upt.begin();
1680	for (uint32_t i=0; i < (upt.size()>>1); ++i)
1681	it_event ++;
1682
1683	for (std::list<request_t>::iterator it_upt = it_event;
1684	it_upt != upt.end();
1685	++it_upt)
1686	it_upt->miss_commit = true;
1687
1688	if (update_ras(it_event->condition))
1689	{
1690	it_event->address_good = ~(it_event->address_dest);
1691	}
1692	else
1693	{
1694	it_event->address_good = it_event->address_dest;
1695	it_event->flag = not it_event->flag;
1696	it_event->no_sequence = not it_event->no_sequence;
1697	it_event->take_good = not it_event->take_good;
1698	}
1699
1700	event = *it_event;
1701
1702
1703	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1704	// for (uint32_t i=0; i<upt.size(); i++)
1705	// just one
1706	{
1707	bool have_transaction = false;
1708
1709	do
1710	{
1711	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1712	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context );
1713	in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr );
1714	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good);
1715	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_event->no_sequence );
1716
1717	if (_param->_have_port_depth)
1718	{
1719	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1720	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1721	}
1722
1723	SC_START(0);
1724
1725	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1726
1727	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1728	{
1729	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1730	LABEL(" * CONTEXT_ID : %d" ,it_event->context );
1731	LABEL(" * DEPTH : %d" ,it_event->upt_ptr );
1732	LABEL(" * CONDITION : %d" ,it_event->condition );
1733	LABEL(" * ADDRESS : %.8x",it_event->address_good);
1734	LABEL(" * FLAG : %d" ,it_event->flag );
1735	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1736
1737	have_transaction = true;
1738
1739	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
1740	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good );
1741	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src );
1742	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good);
1743
1744	upt_top_event [it_event->context] = upt_top [it_event->context];
1745	upt_top [it_event->context] = it_event->upt_ptr;
1746	}
1747
1748	SC_START(1);
1749	} while (not have_transaction);
1750
1751	in_BRANCH_COMPLETE_VAL [port]->write(0);
1752
1753	if (_param->_have_port_depth)
1754	{
1755	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1756	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1757	}
1758	}
1759	}
1760
1761	{
1762	LABEL("BRANCH_COMPLETE - Hit ifetch");
1763
1764	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1765
1766	LABEL(" * port : %d",port);
1767
1768	std::list<request_t>::iterator it_upt = upt.begin();
1769
1770	while (it_upt != it_event)
1771	{
1772	bool have_transaction = false;
1773
1774	do
1775	{
1776	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1777	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1778	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1779	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
1780	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1781
1782	if (_param->_have_port_depth)
1783	{
1784	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1785	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1786	}
1787	SC_START(0);
1788
1789	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1790
1791	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1792	{
1793	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1794	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
1795	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
1796	LABEL(" * CONDITION : %d" ,it_upt->condition );
1797	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
1798	LABEL(" * FLAG : %d" ,it_upt->flag );
1799	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1800
1801	have_transaction = true;
1802
1803	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1804	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
1805	it_upt->take_good = it_upt->take;
1806	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1807	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1808
1809	it_upt++;
1810	}
1811
1812	SC_START(1);
1813	} while (not have_transaction);
1814
1815	in_BRANCH_COMPLETE_VAL [port]->write(0);
1816
1817	if (_param->_have_port_depth)
1818	{
1819	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1820	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1821	}
1822	}
1823	}
1824
1825	if (have_ufpt_ras)
1826	{
1827	LABEL("UPDATE - Update UPFT");
1828
1829	uint32_t port = 0;
1830
1831	LABEL(" * port : %d",port);
1832	std::list<request_t>::iterator it_ufpt = ufpt.end();
1833	-- it_ufpt;
1834
1835	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1836	{
1837	bool have_transaction = false;
1838
1839	do
1840	{
1841	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1842
1843	// if (_param->_have_port_depth)
1844	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1845	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1846
1847	SC_START(0);
1848
1849	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1850
1851	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1852	{
1853	LABEL("UPDATE [%d] - Transaction accepted",port);
1854	have_transaction = true;
1855
1856	if (_param->_have_port_context_id)
1857	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1858	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1859	it_ufpt->miss_decod or
1860	it_ufpt->miss_commit ));
1861	// if (update_btb(it_ufpt->condition) or
1862	// update_dir(it_ufpt->condition))
1863	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1864	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1865	// if (update_btb(it_ufpt->condition))
1866	// {
1867	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1868	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1869	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1870	// }
1871	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1872
1873	// if (update_dir(it_ufpt->condition))
1874	// if (_param->_have_port_history)
1875	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1876	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1877	if (update_ras(it_ufpt->condition))
1878	{
1879	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1880	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1881	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1882	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1883	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1884	}
1885	}
1886
1887	SC_START(1);
1888	} while (not have_transaction);
1889
1890	-- it_ufpt;
1891
1892
1893	in_UPDATE_ACK [port]->write(0);
1894	// if (_param->_have_port_depth)
1895	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1896	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1897	}
1898	}
1899	ufpt.clear();
1900
1901	{
1902	LABEL("UPDATE - upt (after event)");
1903
1904	uint32_t port = 0;
1905
1906	LABEL(" * port : %d",port);
1907	std::list<request_t>::iterator it_upt = upt.end();
1908
1909	// for (uint32_t i=0; i<upt.size(); i++)
1910	do
1911	{
1912	--it_upt;
1913
1914	bool have_transaction = false;
1915
1916	if (need_update(it_upt->condition))
1917	do
1918	{
1919	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1920
1921	// if (_param->_have_port_depth)
1922	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1923	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1924
1925	SC_START(0);
1926
1927	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1928
1929	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1930	{
1931	LABEL("UPDATE [%d] - Transaction accepted",port);
1932	LABEL(" * address_src : %.8x",it_upt->address_src);
1933	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
1934
1935	have_transaction = true;
1936
1937	bool btb_val = ((it_upt == it_event) and
1938	(update_btb(it_upt->condition)));
1939	bool dir_val = ((it_upt == it_event) and
1940	update_dir(it_upt->condition) and
1941	not (it_upt->miss_ifetch or it_upt->miss_decod));
1942	bool ras_val = update_ras(it_upt->condition);
1943
1944	if (_param->_have_port_context_id)
1945	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1946	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1947	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
1948
1949	if (btb_val)
1950	{
1951	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1952	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1953	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1954	}
1955	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
1956
1957	if (dir_val)
1958	{
1959	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1960	if (_param->_have_port_history)
1961	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1962	}
1963	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
1964
1965	if (ras_val)
1966	{
1967	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1968	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1969	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1970	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1971	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1972	}
1973
1974	// -- it_upt;
1975	}
1976
1977	SC_START(1);
1978	} while (not have_transaction);
1979
1980	upt.pop_back();
1981	in_UPDATE_ACK [port]->write(0);
1982	// if (_param->_have_port_depth)
1983	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1984	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1985	}
1986	while (it_upt != it_event);
1987
1988	}
1989
1990	{
1991	LABEL("BRANCH_EVENT - have miss decod");
1992
1993	uint32_t port = context;
1994
1995	{
1996	bool have_transaction = false;
1997
1998	do
1999	{
2000	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2001
2002	SC_START(0);
2003
2004	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2005
2006	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2007	{
2008	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2009	have_transaction = true;
2010
2011	LABEL(" * event.address_src : %.8x,",event.address_src );
2012	LABEL(" * event.address_good : %.8x,",event.address_good);
2013	LABEL(" * event.take : %.8x,",event.take );
2014
2015	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2016	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2017	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2018	if (event.take_good)
2019	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2020
2021	event.address_src = 0;
2022	event.take = 0;
2023	event.address_dest = 0;
2024	}
2025
2026	SC_START(1);
2027	} while (not have_transaction);
2028
2029	in_BRANCH_EVENT_ACK [port]->write(0);
2030	}
2031	}
2032
2033	{
2034	LABEL("EVENT_STATE");
2035
2036	SC_START(1);
2037	in_EVENT_VAL [context]->write(1);
2038	in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION);
2039
2040	SC_START(1);
2041	in_EVENT_VAL [context]->write(0);
2042	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2043	}
2044
2045	{
2046	LABEL("UPDATE - upt (before event)");
2047
2048	uint32_t port = 0;
2049
2050	LABEL(" * port : %d",port);
2051	LABEL(" * size : %d",upt.size());
2052	std::list<request_t>::iterator it_upt = upt.begin();
2053
2054	for (uint32_t i=0; i<upt.size(); i++)
2055	{
2056	bool have_transaction = false;
2057
2058	do
2059	{
2060	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2061
2062	// if (_param->_have_port_depth)
2063	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2064	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2065
2066	SC_START(0);
2067
2068	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2069
2070	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2071	{
2072	LABEL("UPDATE [%d] - Transaction accepted",port);
2073	have_transaction = true;
2074
2075	if (_param->_have_port_context_id)
2076	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2077	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2078	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2079	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2080	if (update_btb(it_upt->condition))
2081	{
2082	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2083	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2084	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2085	}
2086	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2087
2088	if (update_dir(it_upt->condition))
2089	if (_param->_have_port_history)
2090	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2091	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2092	if (update_ras(it_upt->condition))
2093	{
2094	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2095	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2096	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2097	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2098	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2099	}
2100
2101	++ it_upt;
2102	}
2103
2104	SC_START(1);
2105	} while (not have_transaction);
2106
2107	in_UPDATE_ACK [port]->write(0);
2108	// if (_param->_have_port_depth)
2109	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2110	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2111	}
2112	}
2113	upt.clear();
2114
2115	// Wait Garbage Collector
2116	{
2117	LABEL("GARBAGE COLLECTOR");
2118	LABEL(" * upt bottom : %d",upt_bottom [context]);
2119	LABEL(" * upt top : %d",upt_top [context]);
2120
2121	upt_top [context] = (upt_top_event [context]);
2122	upt_bottom [context] = (upt_top [context]);
2123
2124	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2125	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2126	{
2127	SC_START(1);
2128	}
2129
2130	}
2131	}
2132
2133	}// ITERATION
2134
2135	/********************************************************
2136	* Simulation - End
2137	********************************************************/
2138
2139	TEST_OK ("End of Simulation");
2140	delete _time;
2141
2142	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
2143
2144	delete in_CLOCK;
2145	delete in_NRESET;
2146
2147	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2148	delete [] in_PREDICT_VAL ;
2149	delete [] out_PREDICT_ACK ;
2150	delete [] in_PREDICT_CONTEXT_ID ;
2151	delete [] in_PREDICT_BTB_ADDRESS_SRC ;
2152	delete [] in_PREDICT_BTB_ADDRESS_DEST ;
2153	delete [] in_PREDICT_BTB_CONDITION ;
2154	delete [] in_PREDICT_BTB_LAST_TAKE ;
2155	delete [] in_PREDICT_BTB_IS_ACCURATE ;
2156	delete [] in_PREDICT_DIR_HISTORY ;
2157	delete [] in_PREDICT_RAS_ADDRESS ;
2158	delete [] in_PREDICT_RAS_INDEX ;
2159	delete [] out_PREDICT_UPDATE_PREDICTION_ID;
2160
2161	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2162	delete [] in_DECOD_VAL ;
2163	delete [] out_DECOD_ACK ;
2164	delete [] in_DECOD_CONTEXT_ID ;
2165	delete [] in_DECOD_BTB_ADDRESS_SRC ;
2166	delete [] in_DECOD_BTB_ADDRESS_DEST ;
2167	delete [] in_DECOD_BTB_CONDITION ;
2168	delete [] in_DECOD_BTB_LAST_TAKE ;
2169	delete [] in_DECOD_RAS_ADDRESS ;
2170	delete [] in_DECOD_RAS_INDEX ;
2171	delete [] in_DECOD_MISS_IFETCH ;
2172	delete [] in_DECOD_MISS_DECOD ;
2173	delete [] in_DECOD_UPDATE_PREDICTION_ID ;
2174	//delete [] out_DECOD_DEPTH ;
2175	delete [] in_DECOD_IS_ACCURATE ;
2176
2177	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2178	delete [] in_BRANCH_COMPLETE_VAL ;
2179	delete [] out_BRANCH_COMPLETE_ACK ;
2180	delete [] in_BRANCH_COMPLETE_CONTEXT_ID ;
2181	delete [] in_BRANCH_COMPLETE_DEPTH ;
2182	delete [] in_BRANCH_COMPLETE_ADDRESS ;
2183	delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ;
2184	delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
2185	delete [] out_BRANCH_COMPLETE_TAKE ;
2186	delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ;
2187	delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ;
2188
2189	// ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2190	delete [] out_BRANCH_EVENT_VAL ;
2191	delete [] in_BRANCH_EVENT_ACK ;
2192	//delete [] out_BRANCH_EVENT_CONTEXT_ID ;
2193	delete [] out_BRANCH_EVENT_DEPTH ;
2194	//delete [] out_BRANCH_EVENT_MISS_PREDICTION;
2195	delete [] out_BRANCH_EVENT_ADDRESS_SRC ;
2196	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
2197	delete [] out_BRANCH_EVENT_ADDRESS_DEST ;
2198
2199	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2200	delete [] out_UPDATE_VAL ;
2201	delete [] in_UPDATE_ACK ;
2202	delete [] out_UPDATE_CONTEXT_ID ;
2203	delete [] out_UPDATE_MISS_PREDICTION ;
2204	delete [] out_UPDATE_DIRECTION_GOOD ;
2205	delete [] out_UPDATE_BTB_VAL ;
2206	delete [] out_UPDATE_BTB_ADDRESS_SRC ;
2207	delete [] out_UPDATE_BTB_ADDRESS_DEST ;
2208	delete [] out_UPDATE_BTB_CONDITION ;
2209	delete [] out_UPDATE_DIR_VAL ;
2210	delete [] out_UPDATE_DIR_HISTORY ;
2211	delete [] out_UPDATE_RAS_VAL ;
2212	delete [] out_UPDATE_RAS_FLUSH ;
2213	delete [] out_UPDATE_RAS_PUSH ;
2214	delete [] out_UPDATE_RAS_ADDRESS ;
2215	delete [] out_UPDATE_RAS_INDEX ;
2216	delete [] out_UPDATE_RAS_PREDICTION_IFETCH;
2217
2218	DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context);
2219	DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context);
2220	DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context);
2221	DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context);
2222
2223	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2224	delete [] out_DEPTH_VAL;
2225	delete [] out_DEPTH_CURRENT;
2226	delete [] out_DEPTH_MIN;
2227	delete [] out_DEPTH_MAX;
2228	delete [] out_DEPTH_FULL;
2229
2230	#endif
2231
2232	delete _Update_Prediction_Table;
2233	#ifdef STATISTICS
2234	delete _parameters_statistics;
2235	#endif
2236	}

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