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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp @ 105

Last change on this file since 105 was 105, checked in by rosiere, 15 years ago
1) Bug fix : Load Miss Speculation (in Commit_unit, Update Prediction Table and Context State) 2) Change address, in rob write address_next. 3) Move Meta_Predictor in save directory
Property svn:keywords set to `Id`
File size: 141.0 KB

Line
1	/*
2	* $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10	#define CYCLE_MAX (1024*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	typedef struct
17	{
18	uint32_t ufpt_ptr ;
19	uint32_t upt_ptr ;
20
21	Tcontext_t context ;
22	Taddress_t address_src ;
23	Taddress_t address_dest;
24	Taddress_t address_good;
25	Tbranch_condition_t condition ;
26	Tcontrol_t take ;
27	Tcontrol_t take_good ;
28	Tcontrol_t flag ;
29	Tcontrol_t no_sequence ;
30	Tcontrol_t is_accurate ;
31	Thistory_t history ;
32	Taddress_t ras_address ;
33	Tptr_t ras_index ;
34	Tcontrol_t miss_ifetch ;
35	Tcontrol_t miss_decod ;
36	Tcontrol_t miss_commit ;
37	} request_t;
38
39	void test (string name,
40	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * _param)
41	{
42	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
43
44	#ifdef STATISTICS
45	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
46	#endif
47
48	Tusage_t _usage = USE_ALL;
49
50	// _usage = usage_unset(_usage,USE_SYSTEMC );
51	// _usage = usage_unset(_usage,USE_VHDL );
52	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
53	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
54	// _usage = usage_unset(_usage,USE_POSITION );
55	// _usage = usage_unset(_usage,USE_STATISTICS );
56	// _usage = usage_unset(_usage,USE_INFORMATION );
57
58	Update_Prediction_Table * _Update_Prediction_Table = new Update_Prediction_Table
59	(name.c_str(),
60	#ifdef STATISTICS
61	_parameters_statistics,
62	#endif
63	_param,
64	_usage);
65
66	#ifdef SYSTEMC
67	/*********************************************************************
68	* Déclarations des signaux
69	*********************************************************************/
70	string rename;
71
72	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
73	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
74
75	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
76	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
77	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
78	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ," in_PREDICT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_predict);
79	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ," in_PREDICT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_predict);
80	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_CONDITION ," in_PREDICT_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict);
81	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_LAST_TAKE ," in_PREDICT_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict);
82	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ," in_PREDICT_BTB_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict);
83	ALLOC1_SC_SIGNAL( in_PREDICT_DIR_HISTORY ," in_PREDICT_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_predict);
84	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict);
85	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict);
86	ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict);
87	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ," in_DECOD_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ," in_DECOD_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL( in_DECOD_BTB_CONDITION ," in_DECOD_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL( in_DECOD_BTB_LAST_TAKE ," in_DECOD_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL( in_DECOD_RAS_ADDRESS ," in_DECOD_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_decod);
95	ALLOC1_SC_SIGNAL( in_DECOD_RAS_INDEX ," in_DECOD_RAS_INDEX ",Tptr_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL( in_DECOD_MISS_IFETCH ," in_DECOD_MISS_IFETCH ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL( in_DECOD_MISS_DECOD ," in_DECOD_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_decod);
98	ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod);
99	//ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
100	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
101
102	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
103	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
104	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
105	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
106	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
107	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_NO_SEQUENCE ," in_BRANCH_COMPLETE_NO_SEQUENCE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
108	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
109	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
110	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
111	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
112
113	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
114	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
115	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_CONTEXT_ID ,"out_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
116	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_DEPTH ,"out_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
117	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context);
118	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context);
120	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
121
122	ALLOC1_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
123	ALLOC1_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
124	ALLOC1_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
125	ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update);
126	ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update);
127	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update);
128	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update);
129	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,"out_UPDATE_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_update);
130	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_CONDITION ,"out_UPDATE_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
131	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_VAL ,"out_UPDATE_DIR_VAL ",Tcontrol_t ,_param->_nb_inst_update);
132	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update);
133	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update);
134	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update);
135	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update);
136	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update);
137	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update);
138	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);
139
140	ALLOC1_SC_SIGNAL( in_EVENT_VAL ," in_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
141	ALLOC1_SC_SIGNAL(out_EVENT_ACK ,"out_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
142	ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context);
143	ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
144
145	ALLOC1_SC_SIGNAL(out_DEPTH_VAL ,"out_DEPTH_VAL ",Tcontrol_t ,_param->_nb_context);
146	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
147	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
148	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
149	ALLOC1_SC_SIGNAL(out_DEPTH_FULL ,"out_DEPTH_FULL ",Tcontrol_t ,_param->_nb_context);
150
151	/********************************************************
152	* Instanciation
153	********************************************************/
154
155	msg(_("<%s> : Instanciation of _Update_Prediction_Table.\n"),name.c_str());
156
157	((_Update_Prediction_Table->in_CLOCK)) ((in_CLOCK));
158	((_Update_Prediction_Table->in_NRESET)) ((in_NRESET));
159
160	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_VAL ,_param->_nb_inst_predict);
161	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_ACK ,_param->_nb_inst_predict);
162	if (_param->_have_port_context_id)
163	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
164	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict);
165	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict);
166	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict);
167	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict);
168	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict);
169	if (_param->_have_port_history)
170	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict);
171	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict);
172	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict);
173	if (_param->_have_port_depth)
174	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict);
175	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod);
176	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod);
177	if (_param->_have_port_context_id)
178	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
179	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod);
180	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod);
181	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod);
182	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod);
183	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod);
184	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_INDEX ,_param->_nb_inst_decod);
185	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod);
186	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod);
187	if (_param->_have_port_depth)
188	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod);
189	//if (_param->_have_port_depth)
190	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod);
191	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
192	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
193	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
194	if (_param->_have_port_context_id)
195	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
196	if (_param->_have_port_depth)
197	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
198	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
199	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_NO_SEQUENCE ,_param->_nb_inst_branch_complete);
200	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
201	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
202	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
203	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
204
205	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context);
206	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context);
207	//if (_param->_have_port_context_id)
208	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
209	if (_param->_have_port_depth)
210	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_DEPTH ,_param->_nb_context);
211	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
212	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
213	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
214	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
215
216	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_VAL ,_param->_nb_inst_update);
217	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_UPDATE_ACK ,_param->_nb_inst_update);
218	if (_param->_have_port_context_id)
219	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
220	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update);
221	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update);
222	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update);
223	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update);
224	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update);
225	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update);
226	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_VAL ,_param->_nb_inst_update);
227	if (_param->_have_port_history)
228	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update);
229	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update);
230	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update);
231	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update);
232	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update);
233	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update);
234	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update);
235	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_VAL ,_param->_nb_context);
236	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_EVENT_ACK ,_param->_nb_context);
237	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context);
238	if (_param->_have_port_depth)
239	{
240	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context);
241	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context);
242	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context);
243	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context);
244	}
245	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_VAL ,_param->_nb_context);
246	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_FULL ,_param->_nb_context);
247
248	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
249
250	Time * _time = new Time();
251
252	/********************************************************
253	* Simulation - Begin
254	********************************************************/
255
256	// Initialisation
257
258	const uint32_t seed = 0;
259	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
260
261	srand(seed);
262
263	const int32_t percent_transaction_predict = 75;
264	const int32_t percent_transaction_decod = 75;
265	const int32_t percent_transaction_branch_complete = 75;
266	const int32_t percent_transaction_update = 75;
267	const int32_t percent_transaction_branch_event = 75;
268	const int32_t percent_transaction_event = 75;
269
270	const bool test1 = true;
271	const bool test2 = true;
272	const bool test3 = true;
273	const bool test4 = true;
274	const bool test5 = true;
275
276	std::list<request_t> ufpt;
277	std::list<request_t> upt;
278	request_t event;
279
280	SC_START(0);
281	LABEL("Initialisation");
282
283	LABEL("Reset");
284	in_NRESET->write(0);
285	SC_START(5);
286	in_NRESET->write(1);
287
288	Tdepth_t ufpt_bottom [_param->_nb_context];
289	Tdepth_t ufpt_top [_param->_nb_context];
290
291	Tdepth_t upt_bottom [_param->_nb_context];
292	Tdepth_t upt_top [_param->_nb_context];
293	Tdepth_t upt_top_event[_param->_nb_context];
294
295	for (uint32_t i=0; i<_param->_nb_context; ++i)
296	{
297	ufpt_bottom [i] = 0;
298	ufpt_top [i] = 0;
299	upt_bottom [i] = 0;
300	upt_top [i] = 0;
301	upt_top_event[i] = 0;
302	}
303
304	for (uint32_t i=0; i<_param->_nb_context; ++i)
305	{
306	TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]);
307	TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]);
308	TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]);
309	}
310
311	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
312	{
313	LABEL("Iteration %d",iteration);
314
315	for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
316	in_PREDICT_VAL [i]->write(0);
317	for (uint32_t i=0; i<_param->_nb_inst_decod; ++i)
318	in_DECOD_VAL [i]->write(0);
319	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
320	in_BRANCH_COMPLETE_VAL [i]->write(0);
321	for (uint32_t i=0; i<_param->_nb_context; ++i)
322	in_BRANCH_EVENT_ACK [i]->write(0);
323	for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
324	in_UPDATE_ACK [i]->write(0);
325	for (uint32_t i=0; i<_param->_nb_context; ++i)
326	in_EVENT_VAL [i]->write(0);
327
328	//---------------------------------------------------------------------
329	//---------------------------------------------------------------------
330	// COMMON CASE
331	//---------------------------------------------------------------------
332	//---------------------------------------------------------------------
333	if (test1)
334	{
335	uint32_t context = rand() % _param->_nb_context;
336
337	{
338	LABEL("PREDICT - fill the queue");
339	uint32_t port = rand() % _param->_nb_inst_predict;
340
341	LABEL(" * context : %d",context);
342	LABEL(" * port : %d",port);
343
344	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
345	{
346	request_t request;
347	request.context = context;
348	request.address_src = 0xdeadbeef+i;
349	request.address_dest = 0x21071981+i;
350	request.address_good = request.address_dest;
351	request.condition = BRANCH_CONDITION_FLAG_SET;
352	request.take = 1;
353	request.take_good = 1;
354	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
355	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
356	request.is_accurate = true;
357	request.miss_ifetch = false;
358	request.miss_decod = false;
359	request.miss_commit = false;
360	request.history = i;
361	request.ras_address = 0xdeaddead+i;
362	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
363	request.ufpt_ptr = ufpt_top [context];
364	// request.upt_ptr;
365
366	bool have_transaction = false;
367	do
368	{
369	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
370	in_PREDICT_CONTEXT_ID [port]->write(request.context );
371	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
372	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
373	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
374	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
375	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
376	in_PREDICT_DIR_HISTORY [port]->write(request.history );
377	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
378	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
379
380	if (_param->_have_port_depth)
381	{
382	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
383	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
384	}
385	SC_START(0); // fct melay
386
387	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
388	port,
389	in_PREDICT_VAL [port]->read(),
390	out_PREDICT_ACK [port]->read(),
391	in_PREDICT_BTB_IS_ACCURATE [port]->read());
392
393	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
394	{
395	LABEL("PREDICT [%d] - Transaction accepted",port);
396	have_transaction = true;
397
398	if (_param->_have_port_depth)
399	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
400
401	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
402	}
403
404	SC_START(1); // transition
405
406	} while (not have_transaction);
407
408	ufpt.push_back(request);
409
410	in_PREDICT_VAL [port]->write(0);
411
412	if (_param->_have_port_depth)
413	{
414	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
415	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
416	}
417	}
418	}
419
420	{
421	LABEL("DECOD");
422	uint32_t port = rand() % _param->_nb_inst_decod;
423
424	LABEL(" * context : %d",context);
425	LABEL(" * port : %d",port);
426
427	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
428	{
429	request_t request = ufpt.front();
430
431	bool have_transaction = false;
432	do
433	{
434	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
435	in_DECOD_CONTEXT_ID [port]->write(request.context );
436	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
437	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
438	in_DECOD_BTB_CONDITION [port]->write(request.condition );
439	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
440	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
441	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
442	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
443	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
444	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
445	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
446
447	SC_START(0); // fct melay
448
449	LABEL("DECOD [%d] %d - %d",
450	port,
451	in_PREDICT_VAL [port]->read(),
452	out_PREDICT_ACK [port]->read());
453
454	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
455	{
456	LABEL("DECOD [%d] - Transaction accepted",port);
457	have_transaction = true;
458
459	request.upt_ptr = upt_top [context];
460	upt.push_back(request);
461	ufpt.pop_front();
462
463	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
464	}
465
466	SC_START(1); // transition
467
468	} while (not have_transaction);
469
470	in_DECOD_VAL [port]->write(0);
471
472	if (_param->_have_port_depth)
473	{
474	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
475	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
476	}
477	}
478	}
479
480	{
481	LABEL("BRANCH_COMPLETE - hit ifetch");
482
483	uint32_t port = rand() % _param->_nb_inst_branch_complete;
484
485	LABEL(" * port : %d",port);
486
487	std::list<request_t>::iterator it_upt = upt.begin();
488
489	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
490	for (uint32_t i=0; i<upt.size(); i++)
491	{
492	bool have_transaction = false;
493
494	do
495	{
496	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
497	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
498	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
499	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
500	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
501
502	if (_param->_have_port_depth)
503	{
504	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
505	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
506	}
507
508	SC_START(0);
509
510	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
511
512	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
513	{
514	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
515	have_transaction = true;
516
517	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
518	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
519	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
520	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
521
522	it_upt ++;
523	}
524
525	SC_START(1);
526	} while (not have_transaction);
527
528	in_BRANCH_COMPLETE_VAL [port]->write(0);
529
530	if (_param->_have_port_depth)
531	{
532	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
533	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
534	}
535	}
536	}
537
538	{
539	LABEL("UPDATE - hit ifetch");
540
541	uint32_t port = 0;
542
543	LABEL(" * port : %d",port);
544	std::list<request_t>::iterator it_upt = upt.begin();
545
546	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
547	for (uint32_t i=0; i<upt.size(); i++)
548	{
549	bool have_transaction = false;
550
551	do
552	{
553	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
554
555	// if (_param->_have_port_depth)
556	// {
557	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
558	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
559	// }
560
561	SC_START(0);
562
563	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
564
565	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
566	{
567	LABEL("UPDATE [%d] - Transaction accepted",port);
568	have_transaction = true;
569
570	if (_param->_have_port_context_id)
571	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
572	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
573	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
574	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
575	if (update_btb(it_upt->condition))
576	{
577	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
578	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
579	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
580	}
581	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
582	if (update_dir(it_upt->condition))
583	if (_param->_have_port_history)
584	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
585	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
586	if (update_ras(it_upt->condition))
587	{
588	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
589	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
590	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
591	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
592	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
593	}
594	++ it_upt;
595	}
596
597	SC_START(1);
598	} while (not have_transaction);
599
600	in_UPDATE_ACK [port]->write(0);
601	// if (_param->_have_port_depth)
602	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
603	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
604	}
605	upt.clear();
606	}
607
608	// Wait Garbage Collector
609	{
610	upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context];
611	// upt_top [context] = (upt_top [context]);
612
613	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
614	(upt_top [context] != out_DEPTH_MAX [context]->read()))
615	SC_START(1);
616
617	}
618	}
619
620	//---------------------------------------------------------------------
621	//---------------------------------------------------------------------
622	// DECOD MISS : no RAS in ifetch
623	//---------------------------------------------------------------------
624	//---------------------------------------------------------------------
625	if (test2)
626	{
627	uint32_t context = rand() % _param->_nb_context;
628
629	{
630	LABEL("PREDICT - fill the queue");
631	uint32_t port = rand() % _param->_nb_inst_predict;
632
633	LABEL(" * context : %d",context);
634	LABEL(" * port : %d",port);
635
636	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
637	{
638	request_t request;
639	request.context = context;
640	request.address_src = 0xdeadbeef+i;
641	request.address_dest = 0x21071981+i;
642	request.address_good = request.address_dest;
643	request.condition = BRANCH_CONDITION_FLAG_SET;
644	request.take = 1;
645	request.take_good = 1;
646	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
647	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
648	request.is_accurate = true;
649	request.miss_ifetch = false;
650	request.miss_decod = false;
651	request.miss_commit = false;
652	request.history = i;
653	request.ras_address = 0xdeaddead+i;
654	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
655	request.ufpt_ptr = ufpt_top [context];
656	// request.upt_ptr;
657
658	bool have_transaction = false;
659	do
660	{
661	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
662	in_PREDICT_CONTEXT_ID [port]->write(request.context );
663	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
664	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
665	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
666	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
667	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
668	in_PREDICT_DIR_HISTORY [port]->write(request.history );
669	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
670	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
671
672	if (_param->_have_port_depth)
673	{
674	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
675	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
676	}
677	SC_START(0); // fct melay
678
679	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
680	port,
681	in_PREDICT_VAL [port]->read(),
682	out_PREDICT_ACK [port]->read(),
683	in_PREDICT_BTB_IS_ACCURATE [port]->read());
684
685	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
686	{
687	LABEL("PREDICT [%d] - Transaction accepted",port);
688	have_transaction = true;
689
690	if (_param->_have_port_depth)
691	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
692
693	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
694	}
695
696	SC_START(1); // transition
697
698	} while (not have_transaction);
699
700	// ufpt.push_back(request);
701
702	in_PREDICT_VAL [port]->write(0);
703
704	if (_param->_have_port_depth)
705	{
706	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
707	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
708	}
709	}
710	}
711
712	{
713	LABEL("DECOD - Miss");
714	uint32_t port = rand() % _param->_nb_inst_decod;
715
716	LABEL(" * context : %d",context);
717	LABEL(" * port : %d",port);
718
719	request_t request;
720	request.context = context;
721	request.address_src = 0x14011959;
722	request.address_dest = 0x25071959; // after = not take
723	request.address_good = request.address_dest;
724	request.condition = BRANCH_CONDITION_FLAG_SET;
725	request.take = 0;
726	request.take_good = 0;
727	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
728	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
729	request.is_accurate = true;
730	request.miss_ifetch = false;
731	request.miss_decod = true ;
732	request.miss_commit = false;
733	request.history = 1;
734	request.ras_address = 0xbabababa;
735	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
736	request.ufpt_ptr = ufpt_top [context];
737	request.upt_ptr = upt_top [context];
738
739	event = request;
740
741	// for (uint32_t i=0; i<upt.size(); i++)
742	// just one
743	{
744	bool have_transaction = false;
745	do
746	{
747	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
748	in_DECOD_CONTEXT_ID [port]->write(request.context );
749	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
750	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
751	in_DECOD_BTB_CONDITION [port]->write(request.condition );
752	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
753	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
754	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
755	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
756	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
757	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
758	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
759
760	SC_START(0); // fct melay
761
762	LABEL("DECOD [%d] %d - %d",
763	port,
764	in_PREDICT_VAL [port]->read(),
765	out_PREDICT_ACK [port]->read());
766
767	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
768	{
769	LABEL("DECOD [%d] - Transaction accepted",port);
770	have_transaction = true;
771
772	request.upt_ptr = upt_top [context];
773	upt.push_back(request);
774	// ufpt.pop_front();
775
776	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
777	}
778
779	SC_START(1); // transition
780
781	} while (not have_transaction);
782
783	in_DECOD_VAL [port]->write(0);
784
785	if (_param->_have_port_depth)
786	{
787	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
788	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
789	}
790	}
791	}
792
793	{
794	LABEL("BRANCH_COMPLETE - hit ifetch");
795
796	uint32_t port = rand() % _param->_nb_inst_branch_complete;
797
798	LABEL(" * port : %d",port);
799
800	std::list<request_t>::iterator it_upt = upt.begin();
801
802	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
803	// for (uint32_t i=0; i<upt.size(); i++)
804	// just one
805	{
806	bool have_transaction = false;
807
808	do
809	{
810	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
811	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
812	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
813	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
814	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
815
816	if (_param->_have_port_depth)
817	{
818	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
819	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
820	}
821	SC_START(0);
822
823	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
824
825	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
826	{
827	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
828	have_transaction = true;
829
830	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
831	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
832	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
833	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
834
835	it_upt ++;
836	}
837
838	SC_START(1);
839	} while (not have_transaction);
840
841	in_BRANCH_COMPLETE_VAL [port]->write(0);
842
843	if (_param->_have_port_depth)
844	{
845	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
846	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
847	}
848	}
849	}
850
851	{
852	LABEL("UPDATE - hit ifetch");
853
854	uint32_t port = 0;
855
856	LABEL(" * port : %d",port);
857	std::list<request_t>::iterator it_upt = upt.begin();
858
859	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
860	// for (uint32_t i=0; i<upt.size(); i++)
861	// just one
862	{
863	bool have_transaction = false;
864
865	do
866	{
867	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
868
869	// if (_param->_have_port_depth)
870	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
871	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
872
873	SC_START(0);
874
875	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
876
877	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
878	{
879	LABEL("UPDATE [%d] - Transaction accepted",port);
880	have_transaction = true;
881
882	if (_param->_have_port_context_id)
883	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
884	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
885	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
886	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
887	if (update_btb(it_upt->condition))
888	{
889	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
890	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
891	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
892	}
893	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
894
895	if (update_dir(it_upt->condition))
896	if (_param->_have_port_history)
897	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
898	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
899	if (update_ras(it_upt->condition))
900	{
901	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
902	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
903	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
904	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
905	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
906	}
907	++ it_upt;
908	}
909
910	SC_START(1);
911	} while (not have_transaction);
912
913	in_UPDATE_ACK [port]->write(0);
914	// if (_param->_have_port_depth)
915	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
916	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
917	}
918	upt.clear();
919	}
920
921	{
922	LABEL("BRANCH_EVENT - have miss decod");
923
924	uint32_t port = context;
925
926	{
927	bool have_transaction = false;
928
929	do
930	{
931	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
932
933	SC_START(0);
934
935	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
936
937	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
938	{
939	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
940	have_transaction = true;
941
942	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
943	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
944	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
945	if (event.take)
946	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
947
948	event.address_src = 0;
949	event.take = 0;
950	event.address_dest = 0;
951	}
952
953	SC_START(1);
954	} while (not have_transaction);
955
956	in_BRANCH_EVENT_ACK [port]->write(0);
957	}
958	}
959
960	{
961	LABEL("EVENT_STATE");
962
963	SC_START(1);
964	in_EVENT_VAL [context]->write(1);
965	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
966
967	SC_START(1);
968	in_EVENT_VAL [context]->write(0);
969	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
970	}
971
972	// Wait Garbage Collector
973	{
974	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
975	// upt_top [context] = (upt_top [context]);
976
977	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
978	(upt_top [context] != out_DEPTH_MAX [context]->read()))
979	SC_START(1);
980
981	}
982	}
983
984	//---------------------------------------------------------------------
985	//---------------------------------------------------------------------
986	// DECOD MISS : with RAS in ifetch
987	//---------------------------------------------------------------------
988	//---------------------------------------------------------------------
989	if (test3)
990	{
991	uint32_t context = rand() % _param->_nb_context;
992	uint32_t have_ras = false;
993	{
994	LABEL("PREDICT - fill the queue");
995	uint32_t port = rand() % _param->_nb_inst_predict;
996
997	LABEL(" * context : %d",context);
998	LABEL(" * port : %d",port);
999
1000	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1001	{
1002	request_t request;
1003	request.context = context;
1004	request.address_src = 0xdeadbeef+i;
1005	request.address_dest = 0x21071981+i;
1006	request.address_good = request.address_dest;
1007	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
1008
1009	have_ras \|= (update_ras(request.condition));
1010
1011	request.take = 1;
1012	request.take_good = 1;
1013	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1014	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1015	request.is_accurate = true;
1016	request.miss_ifetch = false;
1017	request.miss_decod = true ;
1018	request.miss_commit = false;
1019	request.history = i;
1020	request.ras_address = 0x12344321+i;
1021	request.ras_index = (043211234+i)%_param->_size_ras_index[context];
1022	request.ufpt_ptr = ufpt_top [context];
1023	// request.upt_ptr;
1024
1025	bool have_transaction = false;
1026	do
1027	{
1028	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1029	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1030	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1031	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1032	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1033	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1034	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1035	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1036	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1037	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1038
1039	if (_param->_have_port_depth)
1040	{
1041	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1042	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1043	}
1044	SC_START(0); // fct melay
1045
1046	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1047	port,
1048	in_PREDICT_VAL [port]->read(),
1049	out_PREDICT_ACK [port]->read(),
1050	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1051
1052	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1053	{
1054	LABEL("PREDICT [%d] - Transaction accepted",port);
1055	have_transaction = true;
1056
1057	if (_param->_have_port_depth)
1058	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1059
1060	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1061	}
1062
1063	SC_START(1); // transition
1064
1065	} while (not have_transaction);
1066
1067	ufpt.push_back(request); // to update
1068
1069	in_PREDICT_VAL [port]->write(0);
1070
1071	if (_param->_have_port_depth)
1072	{
1073	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1074	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1075	}
1076	}
1077	}
1078
1079	{
1080	LABEL("DECOD - Miss");
1081	uint32_t port = rand() % _param->_nb_inst_decod;
1082
1083	LABEL(" * context : %d",context);
1084	LABEL(" * port : %d",port);
1085
1086	request_t request;
1087	request.context = context;
1088	request.address_src = 0x14011959;
1089	request.address_dest = 0x25071959; // after = not take
1090	request.address_good = request.address_dest;
1091	request.condition = BRANCH_CONDITION_FLAG_SET;
1092	request.take = 0;
1093	request.take_good = 0;
1094	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1095	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1096	request.is_accurate = true;
1097	request.miss_ifetch = false;
1098	request.miss_decod = true ;
1099	request.miss_commit = false;
1100	request.history = 1;
1101	request.ras_address = 0xbabababa;
1102	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
1103	request.ufpt_ptr = ufpt_top [context];
1104	request.upt_ptr = upt_top [context];
1105
1106	event = request;
1107
1108	// for (uint32_t i=0; i<upt.size(); i++)
1109	// just one
1110	{
1111	bool have_transaction = false;
1112	do
1113	{
1114	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1115	in_DECOD_CONTEXT_ID [port]->write(request.context );
1116	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1117	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1118	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1119	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1120	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1121	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1122	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1123	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1124	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1125	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1126
1127	SC_START(0); // fct melay
1128
1129	LABEL("DECOD [%d] %d - %d",
1130	port,
1131	in_PREDICT_VAL [port]->read(),
1132	out_PREDICT_ACK [port]->read());
1133
1134	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1135	{
1136	LABEL("DECOD [%d] - Transaction accepted",port);
1137	have_transaction = true;
1138
1139	request.upt_ptr = upt_top [context];
1140	upt.push_back(request);
1141	// ufpt.pop_front();
1142
1143	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1144	}
1145
1146	SC_START(1); // transition
1147
1148	} while (not have_transaction);
1149
1150	in_DECOD_VAL [port]->write(0);
1151
1152	if (_param->_have_port_depth)
1153	{
1154	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1155	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1156	}
1157	}
1158	}
1159
1160	{
1161	LABEL("BRANCH_COMPLETE - hit ifetch");
1162
1163	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1164
1165	LABEL(" * port : %d",port);
1166
1167	std::list<request_t>::iterator it_upt = upt.begin();
1168
1169	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1170	// for (uint32_t i=0; i<upt.size(); i++)
1171	// just one
1172	{
1173	bool have_transaction = false;
1174
1175	do
1176	{
1177	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1178	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1179	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1180	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
1181	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1182
1183	if (_param->_have_port_depth)
1184	{
1185	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1186	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1187	}
1188	SC_START(0);
1189
1190	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1191
1192	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1193	{
1194	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1195	have_transaction = true;
1196
1197	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1198	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
1199	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1200	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
1201
1202	it_upt ++;
1203	}
1204
1205	SC_START(1);
1206	} while (not have_transaction);
1207
1208	in_BRANCH_COMPLETE_VAL [port]->write(0);
1209
1210	if (_param->_have_port_depth)
1211	{
1212	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1213	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1214	}
1215	}
1216	}
1217
1218	if (have_ras)
1219	{
1220	LABEL("UPDATE - Update UPFT");
1221
1222	uint32_t port = 0;
1223
1224	LABEL(" * port : %d",port);
1225	std::list<request_t>::iterator it_ufpt = ufpt.end();
1226	-- it_ufpt;
1227
1228	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1229	{
1230	bool have_transaction = false;
1231
1232	do
1233	{
1234	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1235
1236	// if (_param->_have_port_depth)
1237	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1238	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1239
1240	SC_START(0);
1241
1242	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1243
1244	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1245	{
1246	LABEL("UPDATE [%d] - Transaction accepted",port);
1247	have_transaction = true;
1248
1249	if (_param->_have_port_context_id)
1250	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1251	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1252	it_ufpt->miss_decod or
1253	it_ufpt->miss_commit ));
1254	// if (update_btb(it_ufpt->condition) or
1255	// update_dir(it_ufpt->condition))
1256	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1257	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1258	// if (update_btb(it_ufpt->condition))
1259	// {
1260	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1261	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1262	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1263	// }
1264	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1265
1266	// if (update_dir(it_ufpt->condition))
1267	// if (_param->_have_port_history)
1268	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1269	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1270	if (update_ras(it_ufpt->condition))
1271	{
1272	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1273	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1274	LABEL("KANE : out_UPDATE_RAS_ADDRESS [port]->read() : %.8x",out_UPDATE_RAS_ADDRESS [port]->read());
1275	LABEL("KANE : it_ufpt->ras_address : %.8x",it_ufpt->ras_address);
1276
1277	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1278	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1279	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1280	}
1281	}
1282
1283	SC_START(1);
1284	} while (not have_transaction);
1285
1286	-- it_ufpt;
1287
1288
1289	in_UPDATE_ACK [port]->write(0);
1290	// if (_param->_have_port_depth)
1291	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1292	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1293	}
1294	}
1295	ufpt.clear();
1296
1297	{
1298	LABEL("UPDATE - hit ifetch");
1299
1300	uint32_t port = 0;
1301
1302	LABEL(" * port : %d",port);
1303	std::list<request_t>::iterator it_upt = upt.begin();
1304
1305	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1306	// for (uint32_t i=0; i<upt.size(); i++)
1307	// just one
1308	{
1309	bool have_transaction = false;
1310
1311	do
1312	{
1313	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1314
1315	// if (_param->_have_port_depth)
1316	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1317	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1318
1319	SC_START(0);
1320
1321	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1322
1323	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1324	{
1325	LABEL("UPDATE [%d] - Transaction accepted",port);
1326	have_transaction = true;
1327
1328	if (_param->_have_port_context_id)
1329	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1330	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1331	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1332	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1333	if (update_btb(it_upt->condition))
1334	{
1335	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1336	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1337	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1338	}
1339	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1340
1341	if (update_dir(it_upt->condition))
1342	if (_param->_have_port_history)
1343	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1344	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1345	if (update_ras(it_upt->condition))
1346	{
1347	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1348	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1349	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1350	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1351	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1352	}
1353	++ it_upt;
1354	}
1355
1356	SC_START(1);
1357	} while (not have_transaction);
1358
1359	in_UPDATE_ACK [port]->write(0);
1360	// if (_param->_have_port_depth)
1361	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1362	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1363	}
1364	}
1365	upt.clear();
1366
1367	{
1368	LABEL("BRANCH_EVENT - have miss decod");
1369
1370	uint32_t port = context;
1371
1372	{
1373	bool have_transaction = false;
1374
1375	do
1376	{
1377	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1378
1379	SC_START(0);
1380
1381	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1382
1383	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1384	{
1385	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1386	have_transaction = true;
1387
1388	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
1389	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1390	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
1391	if (event.take)
1392	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1393
1394	event.address_src = 0;
1395	event.take = 0;
1396	event.address_dest = 0;
1397	}
1398
1399	SC_START(1);
1400	} while (not have_transaction);
1401
1402	in_BRANCH_EVENT_ACK [port]->write(0);
1403	}
1404	}
1405
1406	{
1407	LABEL("EVENT_STATE");
1408
1409	SC_START(1);
1410	in_EVENT_VAL [context]->write(1);
1411	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
1412
1413	SC_START(1);
1414	in_EVENT_VAL [context]->write(0);
1415	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
1416	}
1417
1418	// Wait Garbage Collector
1419	{
1420	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
1421	// upt_top [context] = (upt_top [context]);
1422
1423	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
1424	(upt_top [context] != out_DEPTH_MAX [context]->read()))
1425	SC_START(1);
1426
1427	}
1428	}
1429
1430	//---------------------------------------------------------------------
1431	//---------------------------------------------------------------------
1432	// COMMIT MISS : with RAS in UPFT and UPT
1433	//---------------------------------------------------------------------
1434	//---------------------------------------------------------------------
1435	if (test4)
1436	{
1437	uint32_t context = rand() % _param->_nb_context;
1438	uint32_t have_ufpt_ras = false;
1439	uint32_t have_upt_ras = false;
1440	{
1441	LABEL("PREDICT - fill the queue");
1442	uint32_t port = rand() % _param->_nb_inst_predict;
1443
1444	LABEL(" * context : %d",context);
1445	LABEL(" * port : %d",port);
1446
1447	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1448	{
1449	request_t request;
1450	request.context = context;
1451	request.address_src = rand();
1452	request.address_dest = rand();
1453
1454	request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET;
1455
1456	request.take = 1;
1457	request.take_good = 1;
1458	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1459	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1460	request.is_accurate = true ;
1461	request.miss_ifetch = false;
1462	request.miss_decod = false;
1463	request.miss_commit = false;
1464	request.history = i;
1465	request.ras_address = rand();
1466	request.ras_index = rand()%_param->_size_ras_index[context];
1467	request.ufpt_ptr = ufpt_top [context];
1468	// request.upt_ptr;
1469
1470	bool have_transaction = false;
1471	do
1472	{
1473	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1474	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1475	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1476	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1477	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1478	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1479	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1480	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1481	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1482	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1483
1484	if (_param->_have_port_depth)
1485	{
1486	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1487	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1488	}
1489	SC_START(0); // fct melay
1490
1491	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1492	port,
1493	in_PREDICT_VAL [port]->read(),
1494	out_PREDICT_ACK [port]->read(),
1495	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1496
1497	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1498	{
1499	LABEL("PREDICT [%d] - Transaction accepted",port);
1500	have_transaction = true;
1501
1502	if (_param->_have_port_depth)
1503	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1504
1505	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1506	}
1507
1508	SC_START(1); // transition
1509
1510	} while (not have_transaction);
1511
1512	ufpt.push_back(request); // to update
1513
1514	in_PREDICT_VAL [port]->write(0);
1515
1516	if (_param->_have_port_depth)
1517	{
1518	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1519	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1520	}
1521	}
1522	}
1523
1524	{
1525	LABEL("DECOD");
1526	uint32_t port = rand() % _param->_nb_inst_decod;
1527
1528	LABEL(" * context : %d",context);
1529	LABEL(" * port : %d",port);
1530
1531	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1532	{
1533	request_t request = ufpt.front();
1534
1535	bool have_transaction = false;
1536	do
1537	{
1538	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1539	in_DECOD_CONTEXT_ID [port]->write(request.context );
1540	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1541	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1542	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1543	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1544	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1545	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1546	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1547	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1548	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1549	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1550
1551	have_upt_ras \|= (update_ras(request.condition));
1552
1553	SC_START(0); // fct melay
1554
1555	LABEL("DECOD [%d] %d - %d",
1556	port,
1557	in_DECOD_VAL [port]->read(),
1558	out_DECOD_ACK [port]->read());
1559
1560	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1561	{
1562	LABEL("DECOD [%d] - Transaction accepted",port);
1563	have_transaction = true;
1564
1565	request.upt_ptr = upt_top [context];
1566	upt.push_back(request);
1567	ufpt.pop_front();
1568
1569	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1570	}
1571
1572	SC_START(1); // transition
1573
1574	} while (not have_transaction);
1575
1576	in_DECOD_VAL [port]->write(0);
1577
1578	if (_param->_have_port_depth)
1579	{
1580	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1581	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1582	}
1583	}
1584	}
1585
1586	{
1587	LABEL("PREDICT - fill the queue");
1588	uint32_t port = rand() % _param->_nb_inst_predict;
1589
1590	LABEL(" * context : %d",context);
1591	LABEL(" * port : %d",port);
1592
1593	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1594	{
1595	request_t request;
1596	request.context = context;
1597	request.address_src = rand();
1598	request.address_dest = rand();
1599	request.address_good = request.address_dest;
1600	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
1601
1602	have_ufpt_ras \|= (update_ras(request.condition));
1603
1604	request.take = 1;
1605	request.take_good = 1;
1606	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1607	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
1608	request.is_accurate = true ;
1609	request.miss_ifetch = false;
1610	request.miss_decod = false;
1611	request.miss_commit = true;
1612	request.history = i;
1613	request.ras_address = rand();
1614	request.ras_index = rand()%_param->_size_ras_index[context];
1615	request.ufpt_ptr = ufpt_top [context];
1616	// request.upt_ptr;
1617
1618	bool have_transaction = false;
1619	do
1620	{
1621	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1622	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1623	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1624	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1625	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1626	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1627	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1628	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1629	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1630	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1631
1632	if (_param->_have_port_depth)
1633	{
1634	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1635	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1636	}
1637	SC_START(0); // fct melay
1638
1639	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1640	port,
1641	in_PREDICT_VAL [port]->read(),
1642	out_PREDICT_ACK [port]->read(),
1643	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1644
1645	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1646	{
1647	LABEL("PREDICT [%d] - Transaction accepted",port);
1648	have_transaction = true;
1649
1650	if (_param->_have_port_depth)
1651	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1652
1653	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1654	}
1655
1656	SC_START(1); // transition
1657
1658	} while (not have_transaction);
1659
1660	ufpt.push_back(request); // to update
1661
1662	in_PREDICT_VAL [port]->write(0);
1663
1664	if (_param->_have_port_depth)
1665	{
1666	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1667	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1668	}
1669	}
1670	}
1671
1672	std::list<request_t>::iterator it_event;
1673	{
1674	LABEL("BRANCH_COMPLETE - Miss ifetch");
1675
1676	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1677
1678	LABEL(" * port : %d",port);
1679
1680	// middle
1681	it_event = upt.begin();
1682	for (uint32_t i=0; i < (upt.size()>>1); ++i)
1683	it_event ++;
1684
1685	for (std::list<request_t>::iterator it_upt = it_event;
1686	it_upt != upt.end();
1687	++it_upt)
1688	it_upt->miss_commit = true;
1689
1690	if (update_ras(it_event->condition))
1691	{
1692	it_event->address_good = ~(it_event->address_dest);
1693	}
1694	else
1695	{
1696	it_event->address_good = it_event->address_dest;
1697	it_event->flag = not it_event->flag;
1698	it_event->no_sequence = not it_event->no_sequence;
1699	it_event->take_good = not it_event->take_good;
1700	}
1701
1702	event = *it_event;
1703
1704
1705	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1706	// for (uint32_t i=0; i<upt.size(); i++)
1707	// just one
1708	{
1709	bool have_transaction = false;
1710
1711	do
1712	{
1713	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1714	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context );
1715	in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr );
1716	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good);
1717	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_event->no_sequence );
1718
1719	if (_param->_have_port_depth)
1720	{
1721	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1722	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1723	}
1724
1725	SC_START(0);
1726
1727	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1728
1729	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1730	{
1731	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1732	LABEL(" * CONTEXT_ID : %d" ,it_event->context );
1733	LABEL(" * DEPTH : %d" ,it_event->upt_ptr );
1734	LABEL(" * CONDITION : %d" ,it_event->condition );
1735	LABEL(" * ADDRESS : %.8x",it_event->address_good);
1736	LABEL(" * FLAG : %d" ,it_event->flag );
1737	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1738
1739	have_transaction = true;
1740
1741	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
1742	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good );
1743	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src );
1744	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good);
1745
1746	upt_top_event [it_event->context] = upt_top [it_event->context];
1747	upt_top [it_event->context] = it_event->upt_ptr;
1748	}
1749
1750	SC_START(1);
1751	} while (not have_transaction);
1752
1753	in_BRANCH_COMPLETE_VAL [port]->write(0);
1754
1755	if (_param->_have_port_depth)
1756	{
1757	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1758	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1759	}
1760	}
1761	}
1762
1763	{
1764	LABEL("BRANCH_COMPLETE - Hit ifetch");
1765
1766	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1767
1768	LABEL(" * port : %d",port);
1769
1770	std::list<request_t>::iterator it_upt = upt.begin();
1771
1772	while (it_upt != it_event)
1773	{
1774	bool have_transaction = false;
1775
1776	do
1777	{
1778	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1779	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1780	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1781	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
1782	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
1783
1784	if (_param->_have_port_depth)
1785	{
1786	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1787	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1788	}
1789	SC_START(0);
1790
1791	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1792
1793	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1794	{
1795	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1796	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
1797	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
1798	LABEL(" * CONDITION : %d" ,it_upt->condition );
1799	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
1800	LABEL(" * FLAG : %d" ,it_upt->flag );
1801	LABEL(" * NO_SEQUENCE : %d" ,it_event->no_sequence );
1802
1803	have_transaction = true;
1804
1805	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1806	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
1807	it_upt->take_good = it_upt->take;
1808	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1809	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1810
1811	it_upt++;
1812	}
1813
1814	SC_START(1);
1815	} while (not have_transaction);
1816
1817	in_BRANCH_COMPLETE_VAL [port]->write(0);
1818
1819	if (_param->_have_port_depth)
1820	{
1821	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1822	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1823	}
1824	}
1825	}
1826
1827	if (have_ufpt_ras)
1828	{
1829	LABEL("UPDATE - Update UPFT");
1830
1831	uint32_t port = 0;
1832
1833	LABEL(" * port : %d",port);
1834	std::list<request_t>::iterator it_ufpt = ufpt.end();
1835	-- it_ufpt;
1836
1837	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1838	{
1839	bool have_transaction = false;
1840
1841	do
1842	{
1843	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1844
1845	// if (_param->_have_port_depth)
1846	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1847	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1848
1849	SC_START(0);
1850
1851	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1852
1853	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1854	{
1855	LABEL("UPDATE [%d] - Transaction accepted",port);
1856	have_transaction = true;
1857
1858	if (_param->_have_port_context_id)
1859	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1860	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1861	it_ufpt->miss_decod or
1862	it_ufpt->miss_commit ));
1863	// if (update_btb(it_ufpt->condition) or
1864	// update_dir(it_ufpt->condition))
1865	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1866	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1867	// if (update_btb(it_ufpt->condition))
1868	// {
1869	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1870	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1871	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1872	// }
1873	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1874
1875	// if (update_dir(it_ufpt->condition))
1876	// if (_param->_have_port_history)
1877	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1878	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1879	if (update_ras(it_ufpt->condition))
1880	{
1881	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1882	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1883	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1884	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1885	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1886	}
1887	}
1888
1889	SC_START(1);
1890	} while (not have_transaction);
1891
1892	-- it_ufpt;
1893
1894
1895	in_UPDATE_ACK [port]->write(0);
1896	// if (_param->_have_port_depth)
1897	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1898	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1899	}
1900	}
1901	ufpt.clear();
1902
1903	{
1904	LABEL("UPDATE - upt (after event)");
1905
1906	uint32_t port = 0;
1907
1908	LABEL(" * port : %d",port);
1909	std::list<request_t>::iterator it_upt = upt.end();
1910
1911	// for (uint32_t i=0; i<upt.size(); i++)
1912	do
1913	{
1914	--it_upt;
1915
1916	bool have_transaction = false;
1917
1918	if (need_update(it_upt->condition))
1919	do
1920	{
1921	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1922
1923	// if (_param->_have_port_depth)
1924	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1925	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1926
1927	SC_START(0);
1928
1929	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1930
1931	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1932	{
1933	LABEL("UPDATE [%d] - Transaction accepted",port);
1934	LABEL(" * address_src : %.8x",it_upt->address_src);
1935	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
1936
1937	have_transaction = true;
1938
1939	bool btb_val = ((it_upt == it_event) and
1940	(update_btb(it_upt->condition)));
1941	bool dir_val = ((it_upt == it_event) and
1942	update_dir(it_upt->condition) and
1943	not (it_upt->miss_ifetch or it_upt->miss_decod));
1944	bool ras_val = update_ras(it_upt->condition);
1945
1946	if (_param->_have_port_context_id)
1947	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1948	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1949	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
1950
1951	if (btb_val)
1952	{
1953	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1954	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1955	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1956	}
1957	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
1958
1959	if (dir_val)
1960	{
1961	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1962	if (_param->_have_port_history)
1963	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1964	}
1965	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
1966
1967	if (ras_val)
1968	{
1969	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1970	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1971	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1972	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1973	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1974	}
1975
1976	// -- it_upt;
1977	}
1978
1979	SC_START(1);
1980	} while (not have_transaction);
1981
1982	upt.pop_back();
1983	in_UPDATE_ACK [port]->write(0);
1984	// if (_param->_have_port_depth)
1985	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1986	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1987	}
1988	while (it_upt != it_event);
1989
1990	}
1991
1992	{
1993	LABEL("BRANCH_EVENT - have miss decod");
1994
1995	uint32_t port = context;
1996
1997	{
1998	bool have_transaction = false;
1999
2000	do
2001	{
2002	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2003
2004	SC_START(0);
2005
2006	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2007
2008	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2009	{
2010	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2011	have_transaction = true;
2012
2013	LABEL(" * event.address_src : %.8x,",event.address_src );
2014	LABEL(" * event.address_good : %.8x,",event.address_good);
2015	LABEL(" * event.take : %.8x,",event.take );
2016
2017	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2018	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2019	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2020	if (event.take_good)
2021	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2022
2023	event.address_src = 0;
2024	event.take = 0;
2025	event.address_dest = 0;
2026	}
2027
2028	SC_START(1);
2029	} while (not have_transaction);
2030
2031	in_BRANCH_EVENT_ACK [port]->write(0);
2032	}
2033	}
2034
2035	{
2036	LABEL("EVENT_STATE");
2037
2038	SC_START(1);
2039	in_EVENT_VAL [context]->write(1);
2040	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
2041
2042	SC_START(1);
2043	in_EVENT_VAL [context]->write(0);
2044	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2045	}
2046
2047	{
2048	LABEL("UPDATE - upt (before event)");
2049
2050	uint32_t port = 0;
2051
2052	LABEL(" * port : %d",port);
2053	LABEL(" * size : %d",upt.size());
2054	std::list<request_t>::iterator it_upt = upt.begin();
2055
2056	for (uint32_t i=0; i<upt.size(); i++)
2057	{
2058	bool have_transaction = false;
2059
2060	do
2061	{
2062	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2063
2064	// if (_param->_have_port_depth)
2065	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2066	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2067
2068	SC_START(0);
2069
2070	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2071
2072	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2073	{
2074	LABEL("UPDATE [%d] - Transaction accepted",port);
2075	have_transaction = true;
2076
2077	if (_param->_have_port_context_id)
2078	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2079	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2080	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2081	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2082	if (update_btb(it_upt->condition))
2083	{
2084	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2085	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2086	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2087	}
2088	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2089
2090	if (update_dir(it_upt->condition))
2091	if (_param->_have_port_history)
2092	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2093	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2094	if (update_ras(it_upt->condition))
2095	{
2096	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2097	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2098	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2099	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2100	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2101	}
2102
2103	++ it_upt;
2104	}
2105
2106	SC_START(1);
2107	} while (not have_transaction);
2108
2109	in_UPDATE_ACK [port]->write(0);
2110	// if (_param->_have_port_depth)
2111	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2112	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2113	}
2114	}
2115	upt.clear();
2116
2117	// Wait Garbage Collector
2118	{
2119	LABEL("GARBAGE COLLECTOR");
2120	LABEL(" * upt bottom : %d",upt_bottom [context]);
2121	LABEL(" * upt top : %d",upt_top [context]);
2122
2123	upt_top [context] = (upt_top_event [context]);
2124	upt_bottom [context] = (upt_top [context]);
2125
2126	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2127	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2128	{
2129	SC_START(1);
2130	}
2131
2132	}
2133	}
2134
2135	//---------------------------------------------------------------------
2136	//---------------------------------------------------------------------
2137	// COMMIT MISS : with RAS in UPFT and UPT
2138	//---------------------------------------------------------------------
2139	//---------------------------------------------------------------------
2140	if (test5)
2141	{
2142	uint32_t context = rand() % _param->_nb_context;
2143	uint32_t have_ufpt_ras = false;
2144	uint32_t have_upt_ras = false;
2145
2146	{
2147	LABEL("PREDICT - fill the queue");
2148	uint32_t port = rand() % _param->_nb_inst_predict;
2149
2150	LABEL(" * context : %d",context);
2151	LABEL(" * port : %d",port);
2152
2153	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2154	{
2155	request_t request;
2156	request.context = context;
2157	request.address_src = rand();
2158	request.address_dest = rand();
2159
2160	request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET;
2161
2162	request.take = 1;
2163	request.take_good = 1;
2164	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
2165	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
2166	request.is_accurate = true ;
2167	request.miss_ifetch = false;
2168	request.miss_decod = false;
2169	request.miss_commit = false;
2170	request.history = i;
2171	request.ras_address = rand();
2172	request.ras_index = rand()%_param->_size_ras_index[context];
2173	request.ufpt_ptr = ufpt_top [context];
2174	// request.upt_ptr;
2175
2176	bool have_transaction = false;
2177	do
2178	{
2179	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
2180	in_PREDICT_CONTEXT_ID [port]->write(request.context );
2181	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
2182	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2183	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
2184	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
2185	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
2186	in_PREDICT_DIR_HISTORY [port]->write(request.history );
2187	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
2188	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
2189
2190	if (_param->_have_port_depth)
2191	{
2192	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2193	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2194	}
2195	SC_START(0); // fct melay
2196
2197	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
2198	port,
2199	in_PREDICT_VAL [port]->read(),
2200	out_PREDICT_ACK [port]->read(),
2201	in_PREDICT_BTB_IS_ACCURATE [port]->read());
2202
2203	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
2204	{
2205	LABEL("PREDICT [%d] - Transaction accepted",port);
2206	have_transaction = true;
2207
2208	if (_param->_have_port_depth)
2209	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
2210
2211	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
2212	}
2213
2214	SC_START(1); // transition
2215
2216	} while (not have_transaction);
2217
2218	ufpt.push_back(request); // to update
2219
2220	in_PREDICT_VAL [port]->write(0);
2221
2222	if (_param->_have_port_depth)
2223	{
2224	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2225	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2226	}
2227	}
2228	}
2229
2230	{
2231	LABEL("DECOD");
2232	uint32_t port = rand() % _param->_nb_inst_decod;
2233
2234	LABEL(" * context : %d",context);
2235	LABEL(" * port : %d",port);
2236
2237	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2238	{
2239	request_t request = ufpt.front();
2240
2241	bool have_transaction = false;
2242	do
2243	{
2244	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
2245	in_DECOD_CONTEXT_ID [port]->write(request.context );
2246	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
2247	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2248	in_DECOD_BTB_CONDITION [port]->write(request.condition );
2249	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
2250	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
2251	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
2252	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
2253	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
2254	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
2255	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
2256
2257	have_upt_ras \|= (update_ras(request.condition));
2258
2259	SC_START(0); // fct melay
2260
2261	LABEL("DECOD [%d] %d - %d",
2262	port,
2263	in_DECOD_VAL [port]->read(),
2264	out_DECOD_ACK [port]->read());
2265
2266	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
2267	{
2268	LABEL("DECOD [%d] - Transaction accepted",port);
2269	have_transaction = true;
2270
2271	request.upt_ptr = upt_top [context];
2272	upt.push_back(request);
2273	ufpt.pop_front();
2274
2275	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
2276	}
2277
2278	SC_START(1); // transition
2279
2280	} while (not have_transaction);
2281
2282	in_DECOD_VAL [port]->write(0);
2283
2284	if (_param->_have_port_depth)
2285	{
2286	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2287	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2288	}
2289	}
2290	}
2291
2292	{
2293	LABEL("PREDICT - fill the queue");
2294	uint32_t port = rand() % _param->_nb_inst_predict;
2295
2296	LABEL(" * context : %d",context);
2297	LABEL(" * port : %d",port);
2298
2299	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2300	{
2301	request_t request;
2302	request.context = context;
2303	request.address_src = rand();
2304	request.address_dest = rand();
2305	request.address_good = request.address_dest;
2306	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
2307
2308	have_ufpt_ras \|= (update_ras(request.condition));
2309
2310	request.take = 1;
2311	request.take_good = 1;
2312	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
2313	request.no_sequence = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.flag:not request.flag;
2314	request.is_accurate = true ;
2315	request.miss_ifetch = false;
2316	request.miss_decod = false;
2317	request.miss_commit = true;
2318	request.history = i;
2319	request.ras_address = rand();
2320	request.ras_index = rand()%_param->_size_ras_index[context];
2321	request.ufpt_ptr = ufpt_top [context];
2322	// request.upt_ptr;
2323
2324	bool have_transaction = false;
2325	do
2326	{
2327	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
2328	in_PREDICT_CONTEXT_ID [port]->write(request.context );
2329	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
2330	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
2331	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
2332	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
2333	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
2334	in_PREDICT_DIR_HISTORY [port]->write(request.history );
2335	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
2336	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
2337
2338	if (_param->_have_port_depth)
2339	{
2340	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2341	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2342	}
2343	SC_START(0); // fct melay
2344
2345	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
2346	port,
2347	in_PREDICT_VAL [port]->read(),
2348	out_PREDICT_ACK [port]->read(),
2349	in_PREDICT_BTB_IS_ACCURATE [port]->read());
2350
2351	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
2352	{
2353	LABEL("PREDICT [%d] - Transaction accepted",port);
2354	have_transaction = true;
2355
2356	if (_param->_have_port_depth)
2357	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
2358
2359	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
2360	}
2361
2362	SC_START(1); // transition
2363
2364	} while (not have_transaction);
2365
2366	ufpt.push_back(request); // to update
2367
2368	in_PREDICT_VAL [port]->write(0);
2369
2370	if (_param->_have_port_depth)
2371	{
2372	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2373	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2374	}
2375	}
2376	}
2377
2378	uint32_t nb_branch_before_event = 0;
2379	{
2380	// middle
2381	std::list<request_t>::iterator it_event = upt.begin();
2382	for (uint32_t i=0; i < (upt.size()>>1); ++i)
2383	{
2384	nb_branch_before_event ++;
2385	it_event ++;
2386	}
2387	for (std::list<request_t>::iterator it = it_event; it != upt.end(); ++it)
2388	it->miss_commit = true;
2389
2390	bool have_transaction = false;
2391
2392	do
2393	{
2394	PORT_WRITE(in_EVENT_VAL [context],(rand()%100)<percent_transaction_event);
2395	PORT_WRITE(in_EVENT_TYPE [context],EVENT_TYPE_LOAD_MISS_SPECULATION);
2396	PORT_WRITE(in_EVENT_DEPTH [context],it_event->upt_ptr);
2397
2398	SC_START(0);
2399
2400	if (PORT_READ(in_EVENT_VAL [context]) and PORT_READ(out_EVENT_ACK [context]))
2401	{
2402	LABEL("EVENT [%d] - Transaction accepted",context);
2403
2404	have_transaction = true;
2405	}
2406
2407	SC_START(1);
2408	}
2409	while (not have_transaction);
2410	PORT_WRITE(in_EVENT_VAL [context],0);
2411
2412	upt_top_event [it_event->context] = upt_top [it_event->context];
2413	upt_top [it_event->context] = it_event->upt_ptr;
2414	}
2415
2416	{
2417	LABEL("BRANCH_COMPLETE - Hit ifetch");
2418
2419	uint32_t port = rand() % _param->_nb_inst_branch_complete;
2420
2421	LABEL(" * port : %d",port);
2422
2423	std::list<request_t>::iterator it_upt = upt.begin();
2424
2425	for (uint32_t i=0; i<nb_branch_before_event; ++i)
2426	{
2427	bool have_transaction = false;
2428
2429	do
2430	{
2431	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
2432	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
2433	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
2434	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
2435	in_BRANCH_COMPLETE_NO_SEQUENCE[port]->write(it_upt->no_sequence );
2436
2437	if (_param->_have_port_depth)
2438	{
2439	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2440	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2441	}
2442	SC_START(0);
2443
2444	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
2445
2446	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
2447	{
2448	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
2449	LABEL(" * CONTEXT_ID : %d" ,it_upt->context );
2450	LABEL(" * DEPTH : %d" ,it_upt->upt_ptr );
2451	LABEL(" * CONDITION : %d" ,it_upt->condition );
2452	LABEL(" * ADDRESS : %.8x",it_upt->address_dest);
2453	LABEL(" * FLAG : %d" ,it_upt->flag );
2454	LABEL(" * NO_SEQUENCE : %d" ,it_upt->no_sequence );
2455
2456	have_transaction = true;
2457
2458	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
2459	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
2460	it_upt->take_good = it_upt->take;
2461	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
2462	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2463
2464	it_upt++;
2465	}
2466
2467	SC_START(1);
2468
2469	} while (not have_transaction);
2470
2471	in_BRANCH_COMPLETE_VAL [port]->write(0);
2472
2473	if (_param->_have_port_depth)
2474	{
2475	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2476	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2477	}
2478	}
2479	}
2480
2481	if (have_ufpt_ras)
2482	{
2483	LABEL("UPDATE - Update UPFT");
2484
2485	uint32_t port = 0;
2486
2487	LABEL(" * port : %d",port);
2488	std::list<request_t>::iterator it_ufpt = ufpt.end();
2489	-- it_ufpt;
2490
2491	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
2492	{
2493	bool have_transaction = false;
2494
2495	do
2496	{
2497	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2498
2499	// if (_param->_have_port_depth)
2500	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
2501	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
2502
2503	SC_START(0);
2504
2505	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2506
2507	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2508	{
2509	LABEL("UPDATE [%d] - Transaction accepted",port);
2510	have_transaction = true;
2511
2512	if (_param->_have_port_context_id)
2513	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
2514	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
2515	it_ufpt->miss_decod or
2516	it_ufpt->miss_commit ));
2517	// if (update_btb(it_ufpt->condition) or
2518	// update_dir(it_ufpt->condition))
2519	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
2520	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
2521	// if (update_btb(it_ufpt->condition))
2522	// {
2523	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
2524	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
2525	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
2526	// }
2527	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
2528
2529	// if (update_dir(it_ufpt->condition))
2530	// if (_param->_have_port_history)
2531	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
2532	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
2533	if (update_ras(it_ufpt->condition))
2534	{
2535	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2536	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
2537	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
2538	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
2539	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
2540	}
2541	}
2542
2543	SC_START(1);
2544	} while (not have_transaction);
2545
2546	-- it_ufpt;
2547
2548
2549	in_UPDATE_ACK [port]->write(0);
2550	// if (_param->_have_port_depth)
2551	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
2552	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
2553	}
2554	}
2555	ufpt.clear();
2556
2557	{
2558	LABEL("UPDATE - upt (after event)");
2559
2560	uint32_t port = 0;
2561
2562	LABEL(" * port : %d",port);
2563
2564	std::list<request_t>::iterator it_upt = upt.end();
2565
2566	// for (uint32_t i=0; i<upt.size(); i++)
2567
2568	uint32_t size = upt.size();
2569
2570	LABEL(" * size : %d",size);
2571	LABEL(" * nb_branch_before_event : %d",nb_branch_before_event);
2572
2573	for (uint32_t i=nb_branch_before_event; i<size; ++i)
2574	{
2575	--it_upt;
2576
2577	bool have_transaction = false;
2578
2579	if (need_update(it_upt->condition))
2580	do
2581	{
2582	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2583
2584	// if (_param->_have_port_depth)
2585	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2586	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2587
2588	SC_START(0);
2589
2590	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2591
2592	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2593	{
2594	LABEL("UPDATE [%d] - Transaction accepted",port);
2595	LABEL(" * address_src : %.8x",it_upt->address_src);
2596	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
2597
2598	have_transaction = true;
2599
2600	bool btb_val = ((update_btb(it_upt->condition)));
2601	bool dir_val = (update_dir(it_upt->condition) and
2602	not (it_upt->miss_ifetch or it_upt->miss_decod));
2603	bool ras_val = update_ras(it_upt->condition);
2604
2605	if (_param->_have_port_context_id)
2606	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2607	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2608	// TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
2609
2610	// if (btb_val)
2611	// {
2612	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2613	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2614	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2615	// }
2616	// TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
2617
2618	// if (dir_val)
2619	// {
2620	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2621	// if (_param->_have_port_history)
2622	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2623	// }
2624	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
2625
2626	if (ras_val)
2627	{
2628	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2629	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2630	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2631	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2632	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2633	}
2634	// -- it_upt;
2635	}
2636
2637	SC_START(1);
2638	} while (not have_transaction);
2639
2640	upt.pop_back();
2641	in_UPDATE_ACK [port]->write(0);
2642	// if (_param->_have_port_depth)
2643	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2644	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2645	}
2646	}
2647
2648	/*
2649	{
2650	LABEL("BRANCH_EVENT - have miss decod");
2651
2652	uint32_t port = context;
2653
2654	{
2655	bool have_transaction = false;
2656
2657	do
2658	{
2659	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
2660
2661	SC_START(0);
2662
2663	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
2664
2665	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
2666	{
2667	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
2668	have_transaction = true;
2669
2670	LABEL(" * event.address_src : %.8x,",event.address_src );
2671	LABEL(" * event.address_good : %.8x,",event.address_good);
2672	LABEL(" * event.take : %.8x,",event.take );
2673
2674	TEST(Tdepth_t ,out_BRANCH_EVENT_DEPTH [port]->read(),event.upt_ptr);
2675	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
2676	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
2677	if (event.take_good)
2678	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
2679
2680	event.address_src = 0;
2681	event.take = 0;
2682	event.address_dest = 0;
2683	}
2684
2685	SC_START(1);
2686	} while (not have_transaction);
2687
2688	in_BRANCH_EVENT_ACK [port]->write(0);
2689	}
2690	}
2691
2692	{
2693	LABEL("EVENT_STATE");
2694
2695	SC_START(1);
2696	in_EVENT_VAL [context]->write(1);
2697	in_EVENT_TYPE [context]->write(EVENT_TYPE_BRANCH_MISS_SPECULATION);
2698
2699	SC_START(1);
2700	in_EVENT_VAL [context]->write(0);
2701	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
2702	}
2703	*/
2704
2705	{
2706	LABEL("UPDATE - upt (before event)");
2707
2708	uint32_t port = 0;
2709
2710	LABEL(" * port : %d",port);
2711	LABEL(" * size : %d",upt.size());
2712	std::list<request_t>::iterator it_upt = upt.begin();
2713
2714	for (uint32_t i=0; i<upt.size(); i++)
2715	{
2716	bool have_transaction = false;
2717
2718	do
2719	{
2720	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2721
2722	// if (_param->_have_port_depth)
2723	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2724	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2725
2726	SC_START(0);
2727
2728	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2729
2730	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2731	{
2732	LABEL("UPDATE [%d] - Transaction accepted",port);
2733	have_transaction = true;
2734
2735	if (_param->_have_port_context_id)
2736	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2737	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2738	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2739	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2740	if (update_btb(it_upt->condition))
2741	{
2742	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2743	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2744	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2745	}
2746	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2747
2748	if (update_dir(it_upt->condition))
2749	if (_param->_have_port_history)
2750	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2751	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2752	if (update_ras(it_upt->condition))
2753	{
2754	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2755	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2756	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2757	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2758	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2759	}
2760
2761	++ it_upt;
2762	}
2763
2764	SC_START(1);
2765	} while (not have_transaction);
2766
2767	in_UPDATE_ACK [port]->write(0);
2768	// if (_param->_have_port_depth)
2769	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2770	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2771	}
2772	}
2773
2774	upt.clear();
2775
2776	// Wait Garbage Collector
2777	{
2778	LABEL("GARBAGE COLLECTOR");
2779	LABEL(" * upt bottom : %d",upt_bottom [context]);
2780	LABEL(" * upt top : %d",upt_top [context]);
2781
2782	upt_top [context] = (upt_top_event [context]);
2783	upt_bottom [context] = (upt_top [context]);
2784
2785	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2786	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2787	{
2788	SC_START(1);
2789	}
2790	}
2791	}
2792
2793	}// ITERATION
2794
2795	/********************************************************
2796	* Simulation - End
2797	********************************************************/
2798
2799	TEST_OK ("End of Simulation");
2800	delete _time;
2801
2802	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
2803
2804	delete in_CLOCK;
2805	delete in_NRESET;
2806
2807	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2808	delete [] in_PREDICT_VAL ;
2809	delete [] out_PREDICT_ACK ;
2810	delete [] in_PREDICT_CONTEXT_ID ;
2811	delete [] in_PREDICT_BTB_ADDRESS_SRC ;
2812	delete [] in_PREDICT_BTB_ADDRESS_DEST ;
2813	delete [] in_PREDICT_BTB_CONDITION ;
2814	delete [] in_PREDICT_BTB_LAST_TAKE ;
2815	delete [] in_PREDICT_BTB_IS_ACCURATE ;
2816	delete [] in_PREDICT_DIR_HISTORY ;
2817	delete [] in_PREDICT_RAS_ADDRESS ;
2818	delete [] in_PREDICT_RAS_INDEX ;
2819	delete [] out_PREDICT_UPDATE_PREDICTION_ID;
2820
2821	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2822	delete [] in_DECOD_VAL ;
2823	delete [] out_DECOD_ACK ;
2824	delete [] in_DECOD_CONTEXT_ID ;
2825	delete [] in_DECOD_BTB_ADDRESS_SRC ;
2826	delete [] in_DECOD_BTB_ADDRESS_DEST ;
2827	delete [] in_DECOD_BTB_CONDITION ;
2828	delete [] in_DECOD_BTB_LAST_TAKE ;
2829	delete [] in_DECOD_RAS_ADDRESS ;
2830	delete [] in_DECOD_RAS_INDEX ;
2831	delete [] in_DECOD_MISS_IFETCH ;
2832	delete [] in_DECOD_MISS_DECOD ;
2833	delete [] in_DECOD_UPDATE_PREDICTION_ID ;
2834	//delete [] out_DECOD_DEPTH ;
2835	delete [] in_DECOD_IS_ACCURATE ;
2836
2837	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2838	delete [] in_BRANCH_COMPLETE_VAL ;
2839	delete [] out_BRANCH_COMPLETE_ACK ;
2840	delete [] in_BRANCH_COMPLETE_CONTEXT_ID ;
2841	delete [] in_BRANCH_COMPLETE_DEPTH ;
2842	delete [] in_BRANCH_COMPLETE_ADDRESS ;
2843	delete [] in_BRANCH_COMPLETE_NO_SEQUENCE ;
2844	delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
2845	delete [] out_BRANCH_COMPLETE_TAKE ;
2846	delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ;
2847	delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ;
2848
2849	// ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2850	delete [] out_BRANCH_EVENT_VAL ;
2851	delete [] in_BRANCH_EVENT_ACK ;
2852	//delete [] out_BRANCH_EVENT_CONTEXT_ID ;
2853	delete [] out_BRANCH_EVENT_DEPTH ;
2854	//delete [] out_BRANCH_EVENT_MISS_PREDICTION;
2855	delete [] out_BRANCH_EVENT_ADDRESS_SRC ;
2856	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
2857	delete [] out_BRANCH_EVENT_ADDRESS_DEST ;
2858
2859	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2860	delete [] out_UPDATE_VAL ;
2861	delete [] in_UPDATE_ACK ;
2862	delete [] out_UPDATE_CONTEXT_ID ;
2863	delete [] out_UPDATE_MISS_PREDICTION ;
2864	delete [] out_UPDATE_DIRECTION_GOOD ;
2865	delete [] out_UPDATE_BTB_VAL ;
2866	delete [] out_UPDATE_BTB_ADDRESS_SRC ;
2867	delete [] out_UPDATE_BTB_ADDRESS_DEST ;
2868	delete [] out_UPDATE_BTB_CONDITION ;
2869	delete [] out_UPDATE_DIR_VAL ;
2870	delete [] out_UPDATE_DIR_HISTORY ;
2871	delete [] out_UPDATE_RAS_VAL ;
2872	delete [] out_UPDATE_RAS_FLUSH ;
2873	delete [] out_UPDATE_RAS_PUSH ;
2874	delete [] out_UPDATE_RAS_ADDRESS ;
2875	delete [] out_UPDATE_RAS_INDEX ;
2876	delete [] out_UPDATE_RAS_PREDICTION_IFETCH;
2877
2878	DELETE1_SC_SIGNAL( in_EVENT_VAL ,_param->_nb_context);
2879	DELETE1_SC_SIGNAL(out_EVENT_ACK ,_param->_nb_context);
2880	DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context);
2881	DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context);
2882
2883	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2884	delete [] out_DEPTH_VAL;
2885	delete [] out_DEPTH_CURRENT;
2886	delete [] out_DEPTH_MIN;
2887	delete [] out_DEPTH_MAX;
2888	delete [] out_DEPTH_FULL;
2889
2890	#endif
2891
2892	delete _Update_Prediction_Table;
2893	#ifdef STATISTICS
2894	delete _parameters_statistics;
2895	#endif
2896	}

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