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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp @ 94

Last change on this file since 94 was 94, checked in by rosiere, 15 years ago
Update document on Vhdl generation.
Property svn:keywords set to `Id`
File size: 99.8 KB

Line
1	/*
2	* $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 8
10	#define CYCLE_MAX (128*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	typedef struct
17	{
18	uint32_t ufpt_ptr ;
19	uint32_t upt_ptr ;
20
21	Tcontext_t context ;
22	Taddress_t address_src ;
23	Taddress_t address_dest;
24	Taddress_t address_good;
25	Tbranch_condition_t condition ;
26	Tcontrol_t take ;
27	Tcontrol_t take_good ;
28	Tcontrol_t flag ;
29	Tcontrol_t is_accurate ;
30	Thistory_t history ;
31	Taddress_t ras_address ;
32	Tptr_t ras_index ;
33	Tcontrol_t miss_ifetch ;
34	Tcontrol_t miss_decod ;
35	Tcontrol_t miss_commit ;
36	} request_t;
37
38	void test (string name,
39	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * _param)
40	{
41	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
42
43	#ifdef STATISTICS
44	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
45	#endif
46
47	Tusage_t _usage = USE_ALL;
48
49	// _usage = usage_unset(_usage,USE_SYSTEMC );
50	// _usage = usage_unset(_usage,USE_VHDL );
51	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
52	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
53	// _usage = usage_unset(_usage,USE_POSITION );
54	// _usage = usage_unset(_usage,USE_STATISTICS );
55	// _usage = usage_unset(_usage,USE_INFORMATION );
56
57	Update_Prediction_Table * _Update_Prediction_Table = new Update_Prediction_Table
58	(name.c_str(),
59	#ifdef STATISTICS
60	_parameters_statistics,
61	#endif
62	_param,
63	_usage);
64
65	#ifdef SYSTEMC
66	/*********************************************************************
67	* Déclarations des signaux
68	*********************************************************************/
69	string rename;
70
71	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
72	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
73
74	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
75	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
76	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
77	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ," in_PREDICT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_predict);
78	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ," in_PREDICT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_predict);
79	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_CONDITION ," in_PREDICT_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict);
80	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_LAST_TAKE ," in_PREDICT_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict);
81	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ," in_PREDICT_BTB_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict);
82	ALLOC1_SC_SIGNAL( in_PREDICT_DIR_HISTORY ," in_PREDICT_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_predict);
83	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict);
84	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict);
85	ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict);
86	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
87	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ," in_DECOD_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ," in_DECOD_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL( in_DECOD_BTB_CONDITION ," in_DECOD_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL( in_DECOD_BTB_LAST_TAKE ," in_DECOD_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL( in_DECOD_RAS_ADDRESS ," in_DECOD_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL( in_DECOD_RAS_INDEX ," in_DECOD_RAS_INDEX ",Tptr_t ,_param->_nb_inst_decod);
95	ALLOC1_SC_SIGNAL( in_DECOD_MISS_IFETCH ," in_DECOD_MISS_IFETCH ",Tcontrol_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL( in_DECOD_MISS_DECOD ," in_DECOD_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod);
98	//ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
99	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
100
101	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
102	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
103	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
104	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
105	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
106	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_FLAG ," in_BRANCH_COMPLETE_FLAG ",Tcontrol_t ,_param->_nb_inst_branch_complete);
107	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
108	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
109	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
110	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
111
112	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
113	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
114	// ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
115	// ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
116	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context);
117	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
118	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
120
121	ALLOC1_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
122	ALLOC1_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
123	ALLOC1_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
124	ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update);
125	ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update);
126	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update);
127	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update);
128	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,"out_UPDATE_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_update);
129	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_CONDITION ,"out_UPDATE_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
130	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_VAL ,"out_UPDATE_DIR_VAL ",Tcontrol_t ,_param->_nb_inst_update);
131	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update);
132	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update);
133	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update);
134	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update);
135	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update);
136	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update);
137	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);
138	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
139	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
140	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
141
142	/********************************************************
143	* Instanciation
144	********************************************************/
145
146	msg(_("<%s> : Instanciation of _Update_Prediction_Table.\n"),name.c_str());
147
148	((_Update_Prediction_Table->in_CLOCK)) ((in_CLOCK));
149	((_Update_Prediction_Table->in_NRESET)) ((in_NRESET));
150
151	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_VAL ,_param->_nb_inst_predict);
152	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_ACK ,_param->_nb_inst_predict);
153	if (_param->_have_port_context_id)
154	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
155	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict);
156	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict);
157	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict);
158	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict);
159	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict);
160	if (_param->_have_port_history)
161	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict);
162	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict);
163	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict);
164	if (_param->_have_port_depth)
165	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict);
166	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod);
167	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod);
168	if (_param->_have_port_context_id)
169	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
170	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod);
171	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod);
172	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod);
173	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod);
174	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod);
175	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_INDEX ,_param->_nb_inst_decod);
176	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod);
177	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod);
178	if (_param->_have_port_depth)
179	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod);
180	//if (_param->_have_port_depth)
181	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod);
182	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
183	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
184	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
185	if (_param->_have_port_context_id)
186	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
187	if (_param->_have_port_depth)
188	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
189	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
190	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete);
191	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
192	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
193	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
194	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
195
196	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context);
197	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context);
198	// if (_param->_have_port_context_id)
199	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
200	// if (_param->_have_port_depth)
201	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
202	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ADDRESS ,_param->_nb_context);
203	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
204	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
205	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
206	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
207
208	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_VAL ,_param->_nb_inst_update);
209	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_UPDATE_ACK ,_param->_nb_inst_update);
210	if (_param->_have_port_context_id)
211	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
212	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update);
213	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update);
214	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update);
215	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update);
216	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update);
217	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update);
218	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_VAL ,_param->_nb_inst_update);
219	if (_param->_have_port_history)
220	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update);
221	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update);
222	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update);
223	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update);
224	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update);
225	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update);
226	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update);
227	if (_param->_have_port_depth)
228	{
229	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context);
230	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context);
231	}
232	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context);
233
234	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
235
236	Time * _time = new Time();
237
238	/********************************************************
239	* Simulation - Begin
240	********************************************************/
241
242	// Initialisation
243
244	const uint32_t seed = 0;
245	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
246
247	srand(seed);
248
249	const int32_t percent_transaction_predict = 75;
250	const int32_t percent_transaction_decod = 75;
251	const int32_t percent_transaction_branch_complete = 75;
252	const int32_t percent_transaction_update = 75;
253	const int32_t percent_transaction_branch_event = 75;
254
255	const bool test1 = false;
256	const bool test2 = false;
257	const bool test3 = false;
258	const bool test4 = true;
259
260	std::list<request_t> ufpt;
261	std::list<request_t> upt;
262	request_t event;
263
264	SC_START(0);
265	LABEL("Initialisation");
266
267	LABEL("Reset");
268	in_NRESET->write(0);
269	SC_START(5);
270	in_NRESET->write(1);
271
272	Tdepth_t ufpt_bottom [_param->_nb_context];
273	Tdepth_t ufpt_top [_param->_nb_context];
274
275	Tdepth_t upt_bottom [_param->_nb_context];
276	Tdepth_t upt_top [_param->_nb_context];
277
278	for (uint32_t i=0; i<_param->_nb_context; ++i)
279	{
280	ufpt_bottom [i] = 0;
281	ufpt_top [i] = 0;
282	upt_bottom [i] = 0;
283	upt_top [i] = 0;
284	}
285
286	for (uint32_t i=0; i<_param->_nb_context; ++i)
287	{
288	TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]);
289	TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]);
290	TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]);
291	}
292
293	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
294	{
295	LABEL("Iteration %d",iteration);
296
297	for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
298	in_PREDICT_VAL [i]->write(0);
299	for (uint32_t i=0; i<_param->_nb_inst_decod; ++i)
300	in_DECOD_VAL [i]->write(0);
301	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
302	in_BRANCH_COMPLETE_VAL [i]->write(0);
303	for (uint32_t i=0; i<_param->_nb_context; ++i)
304	in_BRANCH_EVENT_ACK [i]->write(0);
305	for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
306	in_UPDATE_ACK [i]->write(0);
307
308	//---------------------------------------------------------------------
309	//---------------------------------------------------------------------
310	// COMMON CASE
311	//---------------------------------------------------------------------
312	//---------------------------------------------------------------------
313	if (test1)
314	{
315	uint32_t context = rand() % _param->_nb_context;
316
317	{
318	LABEL("PREDICT - fill the queue");
319	uint32_t port = rand() % _param->_nb_inst_predict;
320
321	LABEL(" * context : %d",context);
322	LABEL(" * port : %d",port);
323
324	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
325	{
326	request_t request;
327	request.context = context;
328	request.address_src = 0xdeadbeef+i;
329	request.address_dest = 0x21071981+i;
330	request.address_good = request.address_dest;
331	request.condition = BRANCH_CONDITION_FLAG_SET;
332	request.take = 1;
333	request.take_good = 1;
334	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
335	request.is_accurate = true;
336	request.miss_ifetch = false;
337	request.miss_decod = false;
338	request.miss_commit = false;
339	request.history = i;
340	request.ras_address = 0xdeaddead+i;
341	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
342	request.ufpt_ptr = ufpt_top [context];
343	// request.upt_ptr;
344
345	bool have_transaction = false;
346	do
347	{
348	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
349	in_PREDICT_CONTEXT_ID [port]->write(request.context );
350	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
351	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
352	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
353	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
354	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
355	in_PREDICT_DIR_HISTORY [port]->write(request.history );
356	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
357	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
358
359	if (_param->_have_port_depth)
360	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
361	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
362
363	SC_START(0); // fct melay
364
365	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
366	port,
367	in_PREDICT_VAL [port]->read(),
368	out_PREDICT_ACK [port]->read(),
369	in_PREDICT_BTB_IS_ACCURATE [port]->read());
370
371	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
372	{
373	LABEL("PREDICT [%d] - Transaction accepted",port);
374	have_transaction = true;
375
376	if (_param->_have_port_depth)
377	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
378
379	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
380	}
381
382	SC_START(1); // transition
383
384	} while (not have_transaction);
385
386	ufpt.push_back(request);
387
388	in_PREDICT_VAL [port]->write(0);
389
390	if (_param->_have_port_depth)
391	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
392	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
393	}
394	}
395
396	{
397	LABEL("DECOD");
398	uint32_t port = rand() % _param->_nb_inst_decod;
399
400	LABEL(" * context : %d",context);
401	LABEL(" * port : %d",port);
402
403	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
404	{
405	request_t request = ufpt.front();
406
407	bool have_transaction = false;
408	do
409	{
410	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
411	in_DECOD_CONTEXT_ID [port]->write(request.context );
412	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
413	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
414	in_DECOD_BTB_CONDITION [port]->write(request.condition );
415	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
416	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
417	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
418	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
419	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
420	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
421	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
422
423	SC_START(0); // fct melay
424
425	LABEL("DECOD [%d] %d - %d",
426	port,
427	in_PREDICT_VAL [port]->read(),
428	out_PREDICT_ACK [port]->read());
429
430	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
431	{
432	LABEL("DECOD [%d] - Transaction accepted",port);
433	have_transaction = true;
434
435	request.upt_ptr = upt_top [context];
436	upt.push_back(request);
437	ufpt.pop_front();
438
439	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
440	}
441
442	SC_START(1); // transition
443
444	} while (not have_transaction);
445
446	in_DECOD_VAL [port]->write(0);
447
448	if (_param->_have_port_depth)
449	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
450	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
451	}
452	}
453
454	{
455	LABEL("BRANCH_COMPLETE - hit ifetch");
456
457	uint32_t port = rand() % _param->_nb_inst_branch_complete;
458
459	LABEL(" * port : %d",port);
460
461	std::list<request_t>::iterator it_upt = upt.begin();
462
463	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
464	for (uint32_t i=0; i<upt.size(); i++)
465	{
466	bool have_transaction = false;
467
468	do
469	{
470	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
471	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
472	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
473	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
474	in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag );
475
476	if (_param->_have_port_depth)
477	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
478	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
479
480	SC_START(0);
481
482	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
483
484	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
485	{
486	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
487	have_transaction = true;
488
489	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
490	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
491	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
492	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
493
494	it_upt ++;
495	}
496
497	SC_START(1);
498	} while (not have_transaction);
499
500	in_BRANCH_COMPLETE_VAL [port]->write(0);
501
502	if (_param->_have_port_depth)
503	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
504	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
505	}
506	}
507
508	{
509	LABEL("UPDATE - hit ifetch");
510
511	uint32_t port = 0;
512
513	LABEL(" * port : %d",port);
514	std::list<request_t>::iterator it_upt = upt.begin();
515
516	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
517	for (uint32_t i=0; i<upt.size(); i++)
518	{
519	bool have_transaction = false;
520
521	do
522	{
523	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
524
525	// if (_param->_have_port_depth)
526	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
527	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
528
529	SC_START(0);
530
531	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
532
533	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
534	{
535	LABEL("UPDATE [%d] - Transaction accepted",port);
536	have_transaction = true;
537
538	if (_param->_have_port_context_id)
539	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
540	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
541	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
542	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
543	if (update_btb(it_upt->condition))
544	{
545	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
546	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
547	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
548	}
549	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
550	if (update_dir(it_upt->condition))
551	if (_param->_have_port_history)
552	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
553	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
554	if (update_ras(it_upt->condition))
555	{
556	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
557	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
558	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
559	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
560	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
561	}
562	++ it_upt;
563	}
564
565	SC_START(1);
566	} while (not have_transaction);
567
568	in_UPDATE_ACK [port]->write(0);
569	// if (_param->_have_port_depth)
570	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
571	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
572	}
573	upt.clear();
574	}
575
576	// Wait Garbage Collector
577	{
578	upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context];
579	// upt_top [context] = (upt_top [context]);
580
581	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
582	(upt_top [context] != out_DEPTH_MAX [context]->read()))
583	SC_START(1);
584
585	}
586	}
587
588	//---------------------------------------------------------------------
589	//---------------------------------------------------------------------
590	// DECOD MISS : no RAS in ifetch
591	//---------------------------------------------------------------------
592	//---------------------------------------------------------------------
593	if (test2)
594	{
595	uint32_t context = rand() % _param->_nb_context;
596
597	{
598	LABEL("PREDICT - fill the queue");
599	uint32_t port = rand() % _param->_nb_inst_predict;
600
601	LABEL(" * context : %d",context);
602	LABEL(" * port : %d",port);
603
604	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
605	{
606	request_t request;
607	request.context = context;
608	request.address_src = 0xdeadbeef+i;
609	request.address_dest = 0x21071981+i;
610	request.address_good = request.address_dest;
611	request.condition = BRANCH_CONDITION_FLAG_SET;
612	request.take = 1;
613	request.take_good = 1;
614	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
615	request.is_accurate = true;
616	request.miss_ifetch = false;
617	request.miss_decod = false;
618	request.miss_commit = false;
619	request.history = i;
620	request.ras_address = 0xdeaddead+i;
621	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
622	request.ufpt_ptr = ufpt_top [context];
623	// request.upt_ptr;
624
625	bool have_transaction = false;
626	do
627	{
628	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
629	in_PREDICT_CONTEXT_ID [port]->write(request.context );
630	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
631	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
632	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
633	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
634	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
635	in_PREDICT_DIR_HISTORY [port]->write(request.history );
636	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
637	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
638
639	if (_param->_have_port_depth)
640	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
641	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
642
643	SC_START(0); // fct melay
644
645	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
646	port,
647	in_PREDICT_VAL [port]->read(),
648	out_PREDICT_ACK [port]->read(),
649	in_PREDICT_BTB_IS_ACCURATE [port]->read());
650
651	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
652	{
653	LABEL("PREDICT [%d] - Transaction accepted",port);
654	have_transaction = true;
655
656	if (_param->_have_port_depth)
657	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
658
659	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
660	}
661
662	SC_START(1); // transition
663
664	} while (not have_transaction);
665
666	// ufpt.push_back(request);
667
668	in_PREDICT_VAL [port]->write(0);
669
670	if (_param->_have_port_depth)
671	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
672	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
673	}
674	}
675
676	{
677	LABEL("DECOD - Miss");
678	uint32_t port = rand() % _param->_nb_inst_decod;
679
680	LABEL(" * context : %d",context);
681	LABEL(" * port : %d",port);
682
683	request_t request;
684	request.context = context;
685	request.address_src = 0x14011959;
686	request.address_dest = 0x25071959; // after = not take
687	request.address_good = request.address_dest;
688	request.condition = BRANCH_CONDITION_FLAG_SET;
689	request.take = 0;
690	request.take_good = 0;
691	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
692	request.is_accurate = true;
693	request.miss_ifetch = false;
694	request.miss_decod = true ;
695	request.miss_commit = false;
696	request.history = 1;
697	request.ras_address = 0xbabababa;
698	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
699	request.ufpt_ptr = ufpt_top [context];
700
701	event = request;
702
703	// for (uint32_t i=0; i<upt.size(); i++)
704	// just one
705	{
706	bool have_transaction = false;
707	do
708	{
709	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
710	in_DECOD_CONTEXT_ID [port]->write(request.context );
711	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
712	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
713	in_DECOD_BTB_CONDITION [port]->write(request.condition );
714	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
715	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
716	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
717	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
718	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
719	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
720	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
721
722	SC_START(0); // fct melay
723
724	LABEL("DECOD [%d] %d - %d",
725	port,
726	in_PREDICT_VAL [port]->read(),
727	out_PREDICT_ACK [port]->read());
728
729	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
730	{
731	LABEL("DECOD [%d] - Transaction accepted",port);
732	have_transaction = true;
733
734	request.upt_ptr = upt_top [context];
735	upt.push_back(request);
736	// ufpt.pop_front();
737
738	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
739	}
740
741	SC_START(1); // transition
742
743	} while (not have_transaction);
744
745	in_DECOD_VAL [port]->write(0);
746
747	if (_param->_have_port_depth)
748	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
749	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
750	}
751	}
752
753	{
754	LABEL("BRANCH_COMPLETE - hit ifetch");
755
756	uint32_t port = rand() % _param->_nb_inst_branch_complete;
757
758	LABEL(" * port : %d",port);
759
760	std::list<request_t>::iterator it_upt = upt.begin();
761
762	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
763	// for (uint32_t i=0; i<upt.size(); i++)
764	// just one
765	{
766	bool have_transaction = false;
767
768	do
769	{
770	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
771	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
772	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
773	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
774	in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag );
775
776	if (_param->_have_port_depth)
777	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
778	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
779
780	SC_START(0);
781
782	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
783
784	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
785	{
786	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
787	have_transaction = true;
788
789	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
790	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
791	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
792	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
793
794	it_upt ++;
795	}
796
797	SC_START(1);
798	} while (not have_transaction);
799
800	in_BRANCH_COMPLETE_VAL [port]->write(0);
801
802	if (_param->_have_port_depth)
803	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
804	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
805	}
806	}
807
808	{
809	LABEL("UPDATE - hit ifetch");
810
811	uint32_t port = 0;
812
813	LABEL(" * port : %d",port);
814	std::list<request_t>::iterator it_upt = upt.begin();
815
816	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
817	// for (uint32_t i=0; i<upt.size(); i++)
818	// just one
819	{
820	bool have_transaction = false;
821
822	do
823	{
824	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
825
826	// if (_param->_have_port_depth)
827	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
828	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
829
830	SC_START(0);
831
832	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
833
834	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
835	{
836	LABEL("UPDATE [%d] - Transaction accepted",port);
837	have_transaction = true;
838
839	if (_param->_have_port_context_id)
840	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
841	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
842	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
843	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
844	if (update_btb(it_upt->condition))
845	{
846	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
847	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
848	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
849	}
850	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
851
852	if (update_dir(it_upt->condition))
853	if (_param->_have_port_history)
854	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
855	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
856	if (update_ras(it_upt->condition))
857	{
858	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
859	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
860	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
861	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
862	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
863	}
864	++ it_upt;
865	}
866
867	SC_START(1);
868	} while (not have_transaction);
869
870	in_UPDATE_ACK [port]->write(0);
871	// if (_param->_have_port_depth)
872	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
873	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
874	}
875	upt.clear();
876	}
877
878	{
879	LABEL("BRANCH_EVENT - have miss decod");
880
881	uint32_t port = context;
882
883	{
884	bool have_transaction = false;
885
886	do
887	{
888	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
889
890	SC_START(0);
891
892	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
893
894	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
895	{
896	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
897	have_transaction = true;
898
899	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
900	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
901	if (event.take)
902	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
903
904	event.address_src = 0;
905	event.take = 0;
906	event.address_dest = 0;
907	}
908
909	SC_START(1);
910	} while (not have_transaction);
911
912	in_BRANCH_EVENT_ACK [port]->write(0);
913	}
914	}
915
916
917	// Wait Garbage Collector
918	{
919	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
920	// upt_top [context] = (upt_top [context]);
921
922	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
923	(upt_top [context] != out_DEPTH_MAX [context]->read()))
924	SC_START(1);
925
926	}
927	}
928
929	//---------------------------------------------------------------------
930	//---------------------------------------------------------------------
931	// DECOD MISS : with RAS in ifetch
932	//---------------------------------------------------------------------
933	//---------------------------------------------------------------------
934	if (test3)
935	{
936	uint32_t context = rand() % _param->_nb_context;
937	uint32_t have_ras = false;
938	{
939	LABEL("PREDICT - fill the queue");
940	uint32_t port = rand() % _param->_nb_inst_predict;
941
942	LABEL(" * context : %d",context);
943	LABEL(" * port : %d",port);
944
945	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
946	{
947	request_t request;
948	request.context = context;
949	request.address_src = 0xdeadbeef+i;
950	request.address_dest = 0x21071981+i;
951	request.address_good = request.address_dest;
952	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
953
954	have_ras \|= (update_ras(request.condition));
955
956	request.take = 1;
957	request.take_good = 1;
958	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
959	request.is_accurate = true;
960	request.miss_ifetch = false;
961	request.miss_decod = true ;
962	request.miss_commit = false;
963	request.history = i;
964	request.ras_address = 0x12344321+i;
965	request.ras_index = (043211234+i)%_param->_size_ras_index[context];
966	request.ufpt_ptr = ufpt_top [context];
967	// request.upt_ptr;
968
969	bool have_transaction = false;
970	do
971	{
972	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
973	in_PREDICT_CONTEXT_ID [port]->write(request.context );
974	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
975	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
976	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
977	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
978	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
979	in_PREDICT_DIR_HISTORY [port]->write(request.history );
980	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
981	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
982
983	if (_param->_have_port_depth)
984	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
985	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
986
987	SC_START(0); // fct melay
988
989	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
990	port,
991	in_PREDICT_VAL [port]->read(),
992	out_PREDICT_ACK [port]->read(),
993	in_PREDICT_BTB_IS_ACCURATE [port]->read());
994
995	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
996	{
997	LABEL("PREDICT [%d] - Transaction accepted",port);
998	have_transaction = true;
999
1000	if (_param->_have_port_depth)
1001	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1002
1003	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1004	}
1005
1006	SC_START(1); // transition
1007
1008	} while (not have_transaction);
1009
1010	ufpt.push_back(request); // to update
1011
1012	in_PREDICT_VAL [port]->write(0);
1013
1014	if (_param->_have_port_depth)
1015	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1016	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1017	}
1018	}
1019
1020	{
1021	LABEL("DECOD - Miss");
1022	uint32_t port = rand() % _param->_nb_inst_decod;
1023
1024	LABEL(" * context : %d",context);
1025	LABEL(" * port : %d",port);
1026
1027	request_t request;
1028	request.context = context;
1029	request.address_src = 0x14011959;
1030	request.address_dest = 0x25071959; // after = not take
1031	request.address_good = request.address_dest;
1032	request.condition = BRANCH_CONDITION_FLAG_SET;
1033	request.take = 0;
1034	request.take_good = 0;
1035	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1036	request.is_accurate = true;
1037	request.miss_ifetch = false;
1038	request.miss_decod = true ;
1039	request.miss_commit = false;
1040	request.history = 1;
1041	request.ras_address = 0xbabababa;
1042	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
1043	request.ufpt_ptr = ufpt_top [context];
1044
1045	event = request;
1046
1047	// for (uint32_t i=0; i<upt.size(); i++)
1048	// just one
1049	{
1050	bool have_transaction = false;
1051	do
1052	{
1053	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1054	in_DECOD_CONTEXT_ID [port]->write(request.context );
1055	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1056	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1057	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1058	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1059	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1060	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1061	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1062	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1063	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1064	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1065
1066	SC_START(0); // fct melay
1067
1068	LABEL("DECOD [%d] %d - %d",
1069	port,
1070	in_PREDICT_VAL [port]->read(),
1071	out_PREDICT_ACK [port]->read());
1072
1073	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1074	{
1075	LABEL("DECOD [%d] - Transaction accepted",port);
1076	have_transaction = true;
1077
1078	request.upt_ptr = upt_top [context];
1079	upt.push_back(request);
1080	// ufpt.pop_front();
1081
1082	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1083	}
1084
1085	SC_START(1); // transition
1086
1087	} while (not have_transaction);
1088
1089	in_DECOD_VAL [port]->write(0);
1090
1091	if (_param->_have_port_depth)
1092	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1093	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1094	}
1095	}
1096
1097	{
1098	LABEL("BRANCH_COMPLETE - hit ifetch");
1099
1100	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1101
1102	LABEL(" * port : %d",port);
1103
1104	std::list<request_t>::iterator it_upt = upt.begin();
1105
1106	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1107	// for (uint32_t i=0; i<upt.size(); i++)
1108	// just one
1109	{
1110	bool have_transaction = false;
1111
1112	do
1113	{
1114	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1115	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1116	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1117	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
1118	in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag );
1119
1120	if (_param->_have_port_depth)
1121	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1122	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1123
1124	SC_START(0);
1125
1126	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1127
1128	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1129	{
1130	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1131	have_transaction = true;
1132
1133	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1134	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
1135	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1136	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
1137
1138	it_upt ++;
1139	}
1140
1141	SC_START(1);
1142	} while (not have_transaction);
1143
1144	in_BRANCH_COMPLETE_VAL [port]->write(0);
1145
1146	if (_param->_have_port_depth)
1147	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1148	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1149	}
1150	}
1151
1152	if (have_ras)
1153	{
1154	LABEL("UPDATE - Update UPFT");
1155
1156	uint32_t port = 0;
1157
1158	LABEL(" * port : %d",port);
1159	std::list<request_t>::iterator it_ufpt = ufpt.end();
1160	-- it_ufpt;
1161
1162	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1163	{
1164	bool have_transaction = false;
1165
1166	do
1167	{
1168	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1169
1170	// if (_param->_have_port_depth)
1171	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1172	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1173
1174	SC_START(0);
1175
1176	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1177
1178	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1179	{
1180	LABEL("UPDATE [%d] - Transaction accepted",port);
1181	have_transaction = true;
1182
1183	if (_param->_have_port_context_id)
1184	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1185	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1186	it_ufpt->miss_decod or
1187	it_ufpt->miss_commit ));
1188	// if (update_btb(it_ufpt->condition) or
1189	// update_dir(it_ufpt->condition))
1190	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1191	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1192	// if (update_btb(it_ufpt->condition))
1193	// {
1194	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1195	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1196	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1197	// }
1198	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1199
1200	// if (update_dir(it_ufpt->condition))
1201	// if (_param->_have_port_history)
1202	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1203	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1204	if (update_ras(it_ufpt->condition))
1205	{
1206	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1207	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1208	LABEL("KANE : out_UPDATE_RAS_ADDRESS [port]->read() : %.8x",out_UPDATE_RAS_ADDRESS [port]->read());
1209	LABEL("KANE : it_ufpt->ras_address : %.8x",it_ufpt->ras_address);
1210
1211	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1212	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1213	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1214	}
1215	}
1216
1217	SC_START(1);
1218	} while (not have_transaction);
1219
1220	-- it_ufpt;
1221
1222
1223	in_UPDATE_ACK [port]->write(0);
1224	// if (_param->_have_port_depth)
1225	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1226	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1227	}
1228	}
1229	ufpt.clear();
1230
1231	{
1232	LABEL("UPDATE - hit ifetch");
1233
1234	uint32_t port = 0;
1235
1236	LABEL(" * port : %d",port);
1237	std::list<request_t>::iterator it_upt = upt.begin();
1238
1239	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1240	// for (uint32_t i=0; i<upt.size(); i++)
1241	// just one
1242	{
1243	bool have_transaction = false;
1244
1245	do
1246	{
1247	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1248
1249	// if (_param->_have_port_depth)
1250	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1251	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1252
1253	SC_START(0);
1254
1255	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1256
1257	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1258	{
1259	LABEL("UPDATE [%d] - Transaction accepted",port);
1260	have_transaction = true;
1261
1262	if (_param->_have_port_context_id)
1263	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1264	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1265	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1266	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1267	if (update_btb(it_upt->condition))
1268	{
1269	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1270	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1271	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1272	}
1273	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1274
1275	if (update_dir(it_upt->condition))
1276	if (_param->_have_port_history)
1277	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1278	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1279	if (update_ras(it_upt->condition))
1280	{
1281	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1282	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1283	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1284	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1285	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1286	}
1287	++ it_upt;
1288	}
1289
1290	SC_START(1);
1291	} while (not have_transaction);
1292
1293	in_UPDATE_ACK [port]->write(0);
1294	// if (_param->_have_port_depth)
1295	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1296	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1297	}
1298	}
1299	upt.clear();
1300
1301	{
1302	LABEL("BRANCH_EVENT - have miss decod");
1303
1304	uint32_t port = context;
1305
1306	{
1307	bool have_transaction = false;
1308
1309	do
1310	{
1311	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1312
1313	SC_START(0);
1314
1315	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1316
1317	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1318	{
1319	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1320	have_transaction = true;
1321
1322	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1323	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
1324	if (event.take)
1325	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1326
1327	event.address_src = 0;
1328	event.take = 0;
1329	event.address_dest = 0;
1330	}
1331
1332	SC_START(1);
1333	} while (not have_transaction);
1334
1335	in_BRANCH_EVENT_ACK [port]->write(0);
1336	}
1337	}
1338
1339	// Wait Garbage Collector
1340	{
1341	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
1342	// upt_top [context] = (upt_top [context]);
1343
1344	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
1345	(upt_top [context] != out_DEPTH_MAX [context]->read()))
1346	SC_START(1);
1347
1348	}
1349	}
1350
1351	//---------------------------------------------------------------------
1352	//---------------------------------------------------------------------
1353	// COMMIT MISS : with RAS in UPFT and UPT
1354	//---------------------------------------------------------------------
1355	//---------------------------------------------------------------------
1356	if (test4)
1357	{
1358	uint32_t context = rand() % _param->_nb_context;
1359	uint32_t have_ufpt_ras = false;
1360	uint32_t have_upt_ras = false;
1361	{
1362	LABEL("PREDICT - fill the queue");
1363	uint32_t port = rand() % _param->_nb_inst_predict;
1364
1365	LABEL(" * context : %d",context);
1366	LABEL(" * port : %d",port);
1367
1368	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1369	{
1370	request_t request;
1371	request.context = context;
1372	request.address_src = rand();
1373	request.address_dest = rand();
1374
1375	request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET;
1376
1377	request.take = 1;
1378	request.take_good = 1;
1379	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1380	request.is_accurate = false;
1381	request.miss_ifetch = false;
1382	request.miss_decod = false;
1383	request.miss_commit = false;
1384	request.history = i;
1385	request.ras_address = rand();
1386	request.ras_index = rand()%_param->_size_ras_index[context];
1387	request.ufpt_ptr = ufpt_top [context];
1388	// request.upt_ptr;
1389
1390	bool have_transaction = false;
1391	do
1392	{
1393	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1394	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1395	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1396	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1397	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1398	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1399	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1400	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1401	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1402	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1403
1404	if (_param->_have_port_depth)
1405	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1406	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1407
1408	SC_START(0); // fct melay
1409
1410	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1411	port,
1412	in_PREDICT_VAL [port]->read(),
1413	out_PREDICT_ACK [port]->read(),
1414	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1415
1416	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1417	{
1418	LABEL("PREDICT [%d] - Transaction accepted",port);
1419	have_transaction = true;
1420
1421	if (_param->_have_port_depth)
1422	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1423
1424	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1425	}
1426
1427	SC_START(1); // transition
1428
1429	} while (not have_transaction);
1430
1431	ufpt.push_back(request); // to update
1432
1433	in_PREDICT_VAL [port]->write(0);
1434
1435	if (_param->_have_port_depth)
1436	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1437	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1438	}
1439	}
1440
1441	{
1442	LABEL("DECOD");
1443	uint32_t port = rand() % _param->_nb_inst_decod;
1444
1445	LABEL(" * context : %d",context);
1446	LABEL(" * port : %d",port);
1447
1448	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1449	{
1450	request_t request = ufpt.front();
1451
1452	bool have_transaction = false;
1453	do
1454	{
1455	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1456	in_DECOD_CONTEXT_ID [port]->write(request.context );
1457	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1458	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1459	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1460	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1461	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1462	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1463	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1464	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1465	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1466	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1467
1468	have_upt_ras \|= (update_ras(request.condition));
1469
1470	SC_START(0); // fct melay
1471
1472	LABEL("DECOD [%d] %d - %d",
1473	port,
1474	in_PREDICT_VAL [port]->read(),
1475	out_PREDICT_ACK [port]->read());
1476
1477	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1478	{
1479	LABEL("DECOD [%d] - Transaction accepted",port);
1480	have_transaction = true;
1481
1482	request.upt_ptr = upt_top [context];
1483	upt.push_back(request);
1484	ufpt.pop_front();
1485
1486	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1487	}
1488
1489	SC_START(1); // transition
1490
1491	} while (not have_transaction);
1492
1493	in_DECOD_VAL [port]->write(0);
1494
1495	if (_param->_have_port_depth)
1496	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1497	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1498	}
1499	}
1500
1501	{
1502	LABEL("PREDICT - fill the queue");
1503	uint32_t port = rand() % _param->_nb_inst_predict;
1504
1505	LABEL(" * context : %d",context);
1506	LABEL(" * port : %d",port);
1507
1508	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1509	{
1510	request_t request;
1511	request.context = context;
1512	request.address_src = rand();
1513	request.address_dest = rand();
1514	request.address_good = request.address_dest;
1515	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
1516
1517	have_ufpt_ras \|= (update_ras(request.condition));
1518
1519	request.take = 1;
1520	request.take_good = 1;
1521	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1522	request.is_accurate = false;
1523	request.miss_ifetch = false;
1524	request.miss_decod = false;
1525	request.miss_commit = true;
1526	request.history = i;
1527	request.ras_address = rand();
1528	request.ras_index = rand()%_param->_size_ras_index[context];
1529	request.ufpt_ptr = ufpt_top [context];
1530	// request.upt_ptr;
1531
1532	bool have_transaction = false;
1533	do
1534	{
1535	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1536	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1537	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1538	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1539	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1540	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1541	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1542	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1543	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1544	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1545
1546	if (_param->_have_port_depth)
1547	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1548	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1549
1550	SC_START(0); // fct melay
1551
1552	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1553	port,
1554	in_PREDICT_VAL [port]->read(),
1555	out_PREDICT_ACK [port]->read(),
1556	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1557
1558	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1559	{
1560	LABEL("PREDICT [%d] - Transaction accepted",port);
1561	have_transaction = true;
1562
1563	if (_param->_have_port_depth)
1564	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1565
1566	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1567	}
1568
1569	SC_START(1); // transition
1570
1571	} while (not have_transaction);
1572
1573	ufpt.push_back(request); // to update
1574
1575	in_PREDICT_VAL [port]->write(0);
1576
1577	if (_param->_have_port_depth)
1578	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1579	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1580	}
1581	}
1582
1583	std::list<request_t>::iterator it_event;
1584	{
1585	LABEL("BRANCH_COMPLETE - hit ifetch");
1586
1587	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1588
1589	LABEL(" * port : %d",port);
1590
1591	// middle
1592	it_event = upt.begin();
1593	for (uint32_t i=0; i < (upt.size()>>1); ++i)
1594	it_event ++;
1595
1596	for (std::list<request_t>::iterator it_upt = it_event;
1597	it_upt != upt.end();
1598	++it_upt)
1599	it_upt->miss_commit = true;
1600
1601	if (update_ras(it_event->condition))
1602	it_event->address_good = ~(it_event->address_dest);
1603	else
1604	{
1605	it_event->address_good = it_event->address_dest;
1606	it_event->flag = not it_event->flag;
1607	it_event->take_good = not it_event->take_good;
1608	}
1609
1610	event = *it_event;
1611
1612
1613	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1614	// for (uint32_t i=0; i<upt.size(); i++)
1615	// just one
1616	{
1617	bool have_transaction = false;
1618
1619	do
1620	{
1621	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1622	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context );
1623	in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr );
1624	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good);
1625	in_BRANCH_COMPLETE_FLAG [port]->write(it_event->flag );
1626
1627	if (_param->_have_port_depth)
1628	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1629	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1630
1631	SC_START(0);
1632
1633	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1634
1635	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1636	{
1637	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1638	LABEL(" * CONTEXT_ID %d" ,it_event->context );
1639	LABEL(" * DEPTH %d" ,it_event->upt_ptr );
1640	LABEL(" * CONDITION %d" ,it_event->condition );
1641	LABEL(" * ADDRESS %.8x",it_event->address_good);
1642	LABEL(" * FLAG %d" ,it_event->flag );
1643
1644	have_transaction = true;
1645
1646	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
1647	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good );
1648	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src );
1649	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good);
1650
1651	upt_top [it_event->context] = it_event->upt_ptr;
1652	}
1653
1654	SC_START(1);
1655	} while (not have_transaction);
1656
1657	in_BRANCH_COMPLETE_VAL [port]->write(0);
1658
1659	if (_param->_have_port_depth)
1660	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1661	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1662	}
1663	}
1664
1665	if (have_ufpt_ras)
1666	{
1667	LABEL("UPDATE - Update UPFT");
1668
1669	uint32_t port = 0;
1670
1671	LABEL(" * port : %d",port);
1672	std::list<request_t>::iterator it_ufpt = ufpt.end();
1673	-- it_ufpt;
1674
1675	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1676	{
1677	bool have_transaction = false;
1678
1679	do
1680	{
1681	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1682
1683	// if (_param->_have_port_depth)
1684	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1685	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1686
1687	SC_START(0);
1688
1689	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1690
1691	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1692	{
1693	LABEL("UPDATE [%d] - Transaction accepted",port);
1694	have_transaction = true;
1695
1696	if (_param->_have_port_context_id)
1697	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1698	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1699	it_ufpt->miss_decod or
1700	it_ufpt->miss_commit ));
1701	// if (update_btb(it_ufpt->condition) or
1702	// update_dir(it_ufpt->condition))
1703	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1704	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1705	// if (update_btb(it_ufpt->condition))
1706	// {
1707	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1708	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1709	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1710	// }
1711	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1712
1713	// if (update_dir(it_ufpt->condition))
1714	// if (_param->_have_port_history)
1715	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1716	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1717	if (update_ras(it_ufpt->condition))
1718	{
1719	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1720	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1721	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1722	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1723	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1724	}
1725	}
1726
1727	SC_START(1);
1728	} while (not have_transaction);
1729
1730	-- it_ufpt;
1731
1732
1733	in_UPDATE_ACK [port]->write(0);
1734	// if (_param->_have_port_depth)
1735	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1736	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1737	}
1738	}
1739	ufpt.clear();
1740
1741	{
1742	LABEL("UPDATE - upt");
1743
1744	uint32_t port = 0;
1745
1746	LABEL(" * port : %d",port);
1747	std::list<request_t>::iterator it_upt = upt.end();
1748	--it_upt;
1749
1750	// for (uint32_t i=0; i<upt.size(); i++)
1751	while (it_upt != it_event)
1752	{
1753	bool have_transaction = false;
1754
1755	do
1756	{
1757	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1758
1759	// if (_param->_have_port_depth)
1760	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1761	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1762
1763	SC_START(0);
1764
1765	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1766
1767	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1768	{
1769	LABEL("UPDATE [%d] - Transaction accepted",port);
1770	have_transaction = true;
1771
1772	if (_param->_have_port_context_id)
1773	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1774	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1775	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1776	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1777	if (update_btb(it_upt->condition))
1778	{
1779	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1780	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1781	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1782	}
1783	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1784
1785	if (update_dir(it_upt->condition))
1786	if (_param->_have_port_history)
1787	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1788	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1789	if (update_ras(it_upt->condition))
1790	{
1791	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1792	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1793	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1794	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1795	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1796	}
1797
1798	-- it_upt;
1799	}
1800
1801	SC_START(1);
1802	} while (not have_transaction);
1803
1804	upt.pop_back();
1805	in_UPDATE_ACK [port]->write(0);
1806	// if (_param->_have_port_depth)
1807	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1808	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1809	}
1810	}
1811	// upt.clear(); // Not yet
1812
1813	{
1814	LABEL("BRANCH_EVENT - have miss decod");
1815
1816	uint32_t port = context;
1817
1818	{
1819	bool have_transaction = false;
1820
1821	do
1822	{
1823	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1824
1825	SC_START(0);
1826
1827	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1828
1829	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1830	{
1831	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1832	have_transaction = true;
1833
1834	LABEL(" * event.address_src : %.8x,",event.address_src );
1835	LABEL(" * event.address_good : %.8x,",event.address_good);
1836	LABEL(" * event.take : %.8x,",event.take );
1837
1838	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1839	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
1840	if (event.take_good)
1841	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1842
1843	event.address_src = 0;
1844	event.take = 0;
1845	event.address_dest = 0;
1846	}
1847
1848	SC_START(1);
1849	} while (not have_transaction);
1850
1851	in_BRANCH_EVENT_ACK [port]->write(0);
1852	}
1853	}
1854
1855	{
1856	LABEL("UPDATE - upt");
1857
1858	uint32_t port = 0;
1859
1860	LABEL(" * port : %d",port);
1861	std::list<request_t>::iterator it_upt = upt.begin();
1862
1863	for (uint32_t i=0; i<upt.size(); i++)
1864	{
1865	bool have_transaction = false;
1866
1867	do
1868	{
1869	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1870
1871	// if (_param->_have_port_depth)
1872	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1873	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1874
1875	SC_START(0);
1876
1877	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1878
1879	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1880	{
1881	LABEL("UPDATE [%d] - Transaction accepted",port);
1882	have_transaction = true;
1883
1884	if (_param->_have_port_context_id)
1885	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1886	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1887	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1888	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1889	if (update_btb(it_upt->condition))
1890	{
1891	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1892	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1893	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1894	}
1895	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1896
1897	if (update_dir(it_upt->condition))
1898	if (_param->_have_port_history)
1899	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1900	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1901	if (update_ras(it_upt->condition))
1902	{
1903	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1904	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1905	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1906	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1907	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1908	}
1909
1910	-- it_upt;
1911	}
1912
1913	SC_START(1);
1914	} while (not have_transaction);
1915
1916	in_UPDATE_ACK [port]->write(0);
1917	// if (_param->_have_port_depth)
1918	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1919	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1920	}
1921	}
1922	upt.clear(); // Not yet
1923
1924	// Wait Garbage Collector
1925	{
1926	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
1927	// upt_top [context] = (upt_top [context]);
1928
1929	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
1930	(upt_top [context] != out_DEPTH_MAX [context]->read()))
1931	SC_START(1);
1932
1933	}
1934	}
1935
1936	}// ITERATION
1937
1938	/********************************************************
1939	* Simulation - End
1940	********************************************************/
1941
1942	TEST_OK ("End of Simulation");
1943	delete _time;
1944
1945	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
1946
1947	delete in_CLOCK;
1948	delete in_NRESET;
1949
1950	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1951	delete [] in_PREDICT_VAL ;
1952	delete [] out_PREDICT_ACK ;
1953	delete [] in_PREDICT_CONTEXT_ID ;
1954	delete [] in_PREDICT_BTB_ADDRESS_SRC ;
1955	delete [] in_PREDICT_BTB_ADDRESS_DEST ;
1956	delete [] in_PREDICT_BTB_CONDITION ;
1957	delete [] in_PREDICT_BTB_LAST_TAKE ;
1958	delete [] in_PREDICT_BTB_IS_ACCURATE ;
1959	delete [] in_PREDICT_DIR_HISTORY ;
1960	delete [] in_PREDICT_RAS_ADDRESS ;
1961	delete [] in_PREDICT_RAS_INDEX ;
1962	delete [] out_PREDICT_UPDATE_PREDICTION_ID;
1963
1964	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1965	delete [] in_DECOD_VAL ;
1966	delete [] out_DECOD_ACK ;
1967	delete [] in_DECOD_CONTEXT_ID ;
1968	delete [] in_DECOD_BTB_ADDRESS_SRC ;
1969	delete [] in_DECOD_BTB_ADDRESS_DEST ;
1970	delete [] in_DECOD_BTB_CONDITION ;
1971	delete [] in_DECOD_BTB_LAST_TAKE ;
1972	delete [] in_DECOD_RAS_ADDRESS ;
1973	delete [] in_DECOD_RAS_INDEX ;
1974	delete [] in_DECOD_MISS_IFETCH ;
1975	delete [] in_DECOD_MISS_DECOD ;
1976	delete [] in_DECOD_UPDATE_PREDICTION_ID ;
1977	//delete [] out_DECOD_DEPTH ;
1978	delete [] in_DECOD_IS_ACCURATE ;
1979
1980	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1981	delete [] in_BRANCH_COMPLETE_VAL ;
1982	delete [] out_BRANCH_COMPLETE_ACK ;
1983	delete [] in_BRANCH_COMPLETE_CONTEXT_ID ;
1984	delete [] in_BRANCH_COMPLETE_DEPTH ;
1985	delete [] in_BRANCH_COMPLETE_ADDRESS ;
1986	delete [] in_BRANCH_COMPLETE_FLAG ;
1987	delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
1988	delete [] out_BRANCH_COMPLETE_TAKE ;
1989	delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ;
1990	delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ;
1991
1992	// ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1993	delete [] out_BRANCH_EVENT_VAL ;
1994	delete [] in_BRANCH_EVENT_ACK ;
1995	// delete [] in_BRANCH_EVENT_CONTEXT_ID ;
1996	// delete [] in_BRANCH_EVENT_DEPTH ;
1997	// delete [] out_BRANCH_EVENT_MISS_PREDICTION;
1998	delete [] out_BRANCH_EVENT_ADDRESS_SRC ;
1999	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
2000	delete [] out_BRANCH_EVENT_ADDRESS_DEST ;
2001
2002	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2003	delete [] out_UPDATE_VAL ;
2004	delete [] in_UPDATE_ACK ;
2005	delete [] out_UPDATE_CONTEXT_ID ;
2006	delete [] out_UPDATE_MISS_PREDICTION ;
2007	delete [] out_UPDATE_DIRECTION_GOOD ;
2008	delete [] out_UPDATE_BTB_VAL ;
2009	delete [] out_UPDATE_BTB_ADDRESS_SRC ;
2010	delete [] out_UPDATE_BTB_ADDRESS_DEST ;
2011	delete [] out_UPDATE_BTB_CONDITION ;
2012	delete [] out_UPDATE_DIR_VAL ;
2013	delete [] out_UPDATE_DIR_HISTORY ;
2014	delete [] out_UPDATE_RAS_VAL ;
2015	delete [] out_UPDATE_RAS_FLUSH ;
2016	delete [] out_UPDATE_RAS_PUSH ;
2017	delete [] out_UPDATE_RAS_ADDRESS ;
2018	delete [] out_UPDATE_RAS_INDEX ;
2019	delete [] out_UPDATE_RAS_PREDICTION_IFETCH;
2020
2021	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2022	delete [] out_DEPTH_CURRENT;
2023	delete [] out_DEPTH_MIN;
2024	delete [] out_DEPTH_MAX;
2025
2026	#endif
2027
2028	delete _Update_Prediction_Table;
2029	#ifdef STATISTICS
2030	delete _parameters_statistics;
2031	#endif
2032	}

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