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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/src/test.cpp @ 95

Last change on this file since 95 was 95, checked in by rosiere, 15 years ago
1) Update Prediction Table - New architecture (systemC) done (and tested) -> need change interface in top level 2) Change documentation on VHDL generation 3) Change VHDL constant (case std_logic and std_logic_vector)
Property svn:keywords set to `Id`
File size: 105.7 KB

Line
1	/*
2	* $id: test.cpp 82 2008-05-01 16:48:45Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 16
10	#define CYCLE_MAX (1024*NB_ITERATION)
11
12	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/SelfTest/include/test.h"
13	#include "Common/include/Test.h"
14	#include "Behavioural/include/Allocation.h"
15
16	typedef struct
17	{
18	uint32_t ufpt_ptr ;
19	uint32_t upt_ptr ;
20
21	Tcontext_t context ;
22	Taddress_t address_src ;
23	Taddress_t address_dest;
24	Taddress_t address_good;
25	Tbranch_condition_t condition ;
26	Tcontrol_t take ;
27	Tcontrol_t take_good ;
28	Tcontrol_t flag ;
29	Tcontrol_t is_accurate ;
30	Thistory_t history ;
31	Taddress_t ras_address ;
32	Tptr_t ras_index ;
33	Tcontrol_t miss_ifetch ;
34	Tcontrol_t miss_decod ;
35	Tcontrol_t miss_commit ;
36	} request_t;
37
38	void test (string name,
39	morpheo::behavioural::core::multi_front_end::front_end::prediction_unit::update_prediction_table::Parameters * _param)
40	{
41	msg(_("<%s> : Simulation SystemC.\n"),name.c_str());
42
43	#ifdef STATISTICS
44	morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
45	#endif
46
47	Tusage_t _usage = USE_ALL;
48
49	// _usage = usage_unset(_usage,USE_SYSTEMC );
50	// _usage = usage_unset(_usage,USE_VHDL );
51	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
52	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
53	// _usage = usage_unset(_usage,USE_POSITION );
54	// _usage = usage_unset(_usage,USE_STATISTICS );
55	// _usage = usage_unset(_usage,USE_INFORMATION );
56
57	Update_Prediction_Table * _Update_Prediction_Table = new Update_Prediction_Table
58	(name.c_str(),
59	#ifdef STATISTICS
60	_parameters_statistics,
61	#endif
62	_param,
63	_usage);
64
65	#ifdef SYSTEMC
66	/*********************************************************************
67	* Déclarations des signaux
68	*********************************************************************/
69	string rename;
70
71	sc_clock * in_CLOCK = new sc_clock ("clock", 1.0, 0.5);
72	sc_signal<Tcontrol_t> * in_NRESET = new sc_signal<Tcontrol_t> ("NRESET");
73
74	ALLOC1_SC_SIGNAL( in_PREDICT_VAL ," in_PREDICT_VAL ",Tcontrol_t ,_param->_nb_inst_predict);
75	ALLOC1_SC_SIGNAL(out_PREDICT_ACK ,"out_PREDICT_ACK ",Tcontrol_t ,_param->_nb_inst_predict);
76	ALLOC1_SC_SIGNAL( in_PREDICT_CONTEXT_ID ," in_PREDICT_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_predict);
77	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_SRC ," in_PREDICT_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_predict);
78	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_ADDRESS_DEST ," in_PREDICT_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_predict);
79	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_CONDITION ," in_PREDICT_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_predict);
80	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_LAST_TAKE ," in_PREDICT_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_predict);
81	ALLOC1_SC_SIGNAL( in_PREDICT_BTB_IS_ACCURATE ," in_PREDICT_BTB_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_predict);
82	ALLOC1_SC_SIGNAL( in_PREDICT_DIR_HISTORY ," in_PREDICT_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_predict);
83	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_ADDRESS ," in_PREDICT_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_predict);
84	ALLOC1_SC_SIGNAL( in_PREDICT_RAS_INDEX ," in_PREDICT_RAS_INDEX ",Tptr_t ,_param->_nb_inst_predict);
85	ALLOC1_SC_SIGNAL(out_PREDICT_UPDATE_PREDICTION_ID ,"out_PREDICT_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_predict);
86	ALLOC1_SC_SIGNAL( in_DECOD_VAL ," in_DECOD_VAL ",Tcontrol_t ,_param->_nb_inst_decod);
87	ALLOC1_SC_SIGNAL(out_DECOD_ACK ,"out_DECOD_ACK ",Tcontrol_t ,_param->_nb_inst_decod);
88	ALLOC1_SC_SIGNAL( in_DECOD_CONTEXT_ID ," in_DECOD_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_decod);
89	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_SRC ," in_DECOD_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_decod);
90	ALLOC1_SC_SIGNAL( in_DECOD_BTB_ADDRESS_DEST ," in_DECOD_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_decod);
91	ALLOC1_SC_SIGNAL( in_DECOD_BTB_CONDITION ," in_DECOD_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_decod);
92	ALLOC1_SC_SIGNAL( in_DECOD_BTB_LAST_TAKE ," in_DECOD_BTB_LAST_TAKE ",Tcontrol_t ,_param->_nb_inst_decod);
93	ALLOC1_SC_SIGNAL( in_DECOD_RAS_ADDRESS ," in_DECOD_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_decod);
94	ALLOC1_SC_SIGNAL( in_DECOD_RAS_INDEX ," in_DECOD_RAS_INDEX ",Tptr_t ,_param->_nb_inst_decod);
95	ALLOC1_SC_SIGNAL( in_DECOD_MISS_IFETCH ," in_DECOD_MISS_IFETCH ",Tcontrol_t ,_param->_nb_inst_decod);
96	ALLOC1_SC_SIGNAL( in_DECOD_MISS_DECOD ," in_DECOD_MISS_DECOD ",Tcontrol_t ,_param->_nb_inst_decod);
97	ALLOC1_SC_SIGNAL( in_DECOD_UPDATE_PREDICTION_ID ," in_DECOD_UPDATE_PREDICTION_ID ",Tprediction_ptr_t ,_param->_nb_inst_decod);
98	//ALLOC1_SC_SIGNAL(out_DECOD_DEPTH ,"out_DECOD_DEPTH ",Tdepth_t ,_param->_nb_inst_decod);
99	ALLOC1_SC_SIGNAL( in_DECOD_IS_ACCURATE ," in_DECOD_IS_ACCURATE ",Tcontrol_t ,_param->_nb_inst_decod);
100
101	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_VAL ," in_BRANCH_COMPLETE_VAL ",Tcontrol_t ,_param->_nb_inst_branch_complete);
102	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ACK ,"out_BRANCH_COMPLETE_ACK ",Tcontrol_t ,_param->_nb_inst_branch_complete);
103	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_CONTEXT_ID ," in_BRANCH_COMPLETE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_branch_complete);
104	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_DEPTH ," in_BRANCH_COMPLETE_DEPTH ",Tdepth_t ,_param->_nb_inst_branch_complete);
105	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_ADDRESS ," in_BRANCH_COMPLETE_ADDRESS ",Taddress_t ,_param->_nb_inst_branch_complete);
106	ALLOC1_SC_SIGNAL( in_BRANCH_COMPLETE_FLAG ," in_BRANCH_COMPLETE_FLAG ",Tcontrol_t ,_param->_nb_inst_branch_complete);
107	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_MISS_PREDICTION,"out_BRANCH_COMPLETE_MISS_PREDICTION",Tcontrol_t ,_param->_nb_inst_branch_complete);
108	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_TAKE ,"out_BRANCH_COMPLETE_TAKE ",Tcontrol_t ,_param->_nb_inst_branch_complete);
109	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_SRC ,"out_BRANCH_COMPLETE_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_branch_complete);
110	ALLOC1_SC_SIGNAL(out_BRANCH_COMPLETE_ADDRESS_DEST ,"out_BRANCH_COMPLETE_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_branch_complete);
111
112	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_VAL ,"out_BRANCH_EVENT_VAL ",Tcontrol_t ,_param->_nb_context);
113	ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_ACK ," in_BRANCH_EVENT_ACK ",Tcontrol_t ,_param->_nb_context);
114	// ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_CONTEXT_ID ," in_BRANCH_EVENT_CONTEXT_ID ",Tcontext_t ,_param->_nb_context);
115	// ALLOC1_SC_SIGNAL( in_BRANCH_EVENT_DEPTH ," in_BRANCH_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
116	// ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_MISS_PREDICTION,"out_BRANCH_EVENT_MISS_PREDICTION",Tcontrol_t ,_param->_nb_context);
117	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_SRC ,"out_BRANCH_EVENT_ADDRESS_SRC ",Taddress_t ,_param->_nb_context);
118	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST_VAL,"out_BRANCH_EVENT_ADDRESS_DEST_VAL",Tcontrol_t ,_param->_nb_context);
119	ALLOC1_SC_SIGNAL(out_BRANCH_EVENT_ADDRESS_DEST ,"out_BRANCH_EVENT_ADDRESS_DEST ",Taddress_t ,_param->_nb_context);
120
121	ALLOC1_SC_SIGNAL(out_UPDATE_VAL ,"out_UPDATE_VAL ",Tcontrol_t ,_param->_nb_inst_update);
122	ALLOC1_SC_SIGNAL( in_UPDATE_ACK ," in_UPDATE_ACK ",Tcontrol_t ,_param->_nb_inst_update);
123	ALLOC1_SC_SIGNAL(out_UPDATE_CONTEXT_ID ,"out_UPDATE_CONTEXT_ID ",Tcontext_t ,_param->_nb_inst_update);
124	ALLOC1_SC_SIGNAL(out_UPDATE_MISS_PREDICTION ,"out_UPDATE_MISS_PREDICTION ",Tcontrol_t ,_param->_nb_inst_update);
125	ALLOC1_SC_SIGNAL(out_UPDATE_DIRECTION_GOOD ,"out_UPDATE_DIRECTION_GOOD ",Tcontrol_t ,_param->_nb_inst_update);
126	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_VAL ,"out_UPDATE_BTB_VAL ",Tcontrol_t ,_param->_nb_inst_update);
127	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_SRC ,"out_UPDATE_BTB_ADDRESS_SRC ",Taddress_t ,_param->_nb_inst_update);
128	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_ADDRESS_DEST ,"out_UPDATE_BTB_ADDRESS_DEST ",Taddress_t ,_param->_nb_inst_update);
129	ALLOC1_SC_SIGNAL(out_UPDATE_BTB_CONDITION ,"out_UPDATE_BTB_CONDITION ",Tbranch_condition_t,_param->_nb_inst_update);
130	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_VAL ,"out_UPDATE_DIR_VAL ",Tcontrol_t ,_param->_nb_inst_update);
131	ALLOC1_SC_SIGNAL(out_UPDATE_DIR_HISTORY ,"out_UPDATE_DIR_HISTORY ",Thistory_t ,_param->_nb_inst_update);
132	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_VAL ,"out_UPDATE_RAS_VAL ",Tcontrol_t ,_param->_nb_inst_update);
133	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_FLUSH ,"out_UPDATE_RAS_FLUSH ",Tcontrol_t ,_param->_nb_inst_update);
134	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PUSH ,"out_UPDATE_RAS_PUSH ",Tcontrol_t ,_param->_nb_inst_update);
135	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_ADDRESS ,"out_UPDATE_RAS_ADDRESS ",Taddress_t ,_param->_nb_inst_update);
136	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_INDEX ,"out_UPDATE_RAS_INDEX ",Tptr_t ,_param->_nb_inst_update);
137	ALLOC1_SC_SIGNAL(out_UPDATE_RAS_PREDICTION_IFETCH ,"out_UPDATE_RAS_PREDICTION_IFETCH ",Tcontrol_t ,_param->_nb_inst_update);
138
139	ALLOC1_SC_SIGNAL( in_EVENT_STATE ," in_EVENT_STATE ",Tevent_state_t ,_param->_nb_context);
140	ALLOC1_SC_SIGNAL( in_EVENT_TYPE ," in_EVENT_TYPE ",Tevent_type_t ,_param->_nb_context);
141	ALLOC1_SC_SIGNAL( in_EVENT_DEPTH ," in_EVENT_DEPTH ",Tdepth_t ,_param->_nb_context);
142
143	ALLOC1_SC_SIGNAL(out_DEPTH_CURRENT ,"out_DEPTH_CURRENT ",Tdepth_t ,_param->_nb_context);
144	ALLOC1_SC_SIGNAL(out_DEPTH_MIN ,"out_DEPTH_MIN ",Tdepth_t ,_param->_nb_context);
145	ALLOC1_SC_SIGNAL(out_DEPTH_MAX ,"out_DEPTH_MAX ",Tdepth_t ,_param->_nb_context);
146
147	/********************************************************
148	* Instanciation
149	********************************************************/
150
151	msg(_("<%s> : Instanciation of _Update_Prediction_Table.\n"),name.c_str());
152
153	((_Update_Prediction_Table->in_CLOCK)) ((in_CLOCK));
154	((_Update_Prediction_Table->in_NRESET)) ((in_NRESET));
155
156	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_VAL ,_param->_nb_inst_predict);
157	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_ACK ,_param->_nb_inst_predict);
158	if (_param->_have_port_context_id)
159	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_CONTEXT_ID ,_param->_nb_inst_predict);
160	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_SRC ,_param->_nb_inst_predict);
161	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_ADDRESS_DEST ,_param->_nb_inst_predict);
162	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_CONDITION ,_param->_nb_inst_predict);
163	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_LAST_TAKE ,_param->_nb_inst_predict);
164	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_BTB_IS_ACCURATE ,_param->_nb_inst_predict);
165	if (_param->_have_port_history)
166	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_DIR_HISTORY ,_param->_nb_inst_predict);
167	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_ADDRESS ,_param->_nb_inst_predict);
168	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_PREDICT_RAS_INDEX ,_param->_nb_inst_predict);
169	if (_param->_have_port_depth)
170	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_PREDICT_UPDATE_PREDICTION_ID ,_param->_nb_inst_predict);
171	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_VAL ,_param->_nb_inst_decod);
172	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_ACK ,_param->_nb_inst_decod);
173	if (_param->_have_port_context_id)
174	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_CONTEXT_ID ,_param->_nb_inst_decod);
175	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_SRC ,_param->_nb_inst_decod);
176	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_ADDRESS_DEST ,_param->_nb_inst_decod);
177	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_CONDITION ,_param->_nb_inst_decod);
178	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_BTB_LAST_TAKE ,_param->_nb_inst_decod);
179	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_ADDRESS ,_param->_nb_inst_decod);
180	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_RAS_INDEX ,_param->_nb_inst_decod);
181	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_IFETCH ,_param->_nb_inst_decod);
182	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_MISS_DECOD ,_param->_nb_inst_decod);
183	if (_param->_have_port_depth)
184	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_UPDATE_PREDICTION_ID ,_param->_nb_inst_decod);
185	//if (_param->_have_port_depth)
186	//INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DECOD_DEPTH ,_param->_nb_inst_decod);
187	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_DECOD_IS_ACCURATE ,_param->_nb_inst_decod);
188	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_VAL ,_param->_nb_inst_branch_complete);
189	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ACK ,_param->_nb_inst_branch_complete);
190	if (_param->_have_port_context_id)
191	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_CONTEXT_ID ,_param->_nb_inst_branch_complete);
192	if (_param->_have_port_depth)
193	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_DEPTH ,_param->_nb_inst_branch_complete);
194	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_ADDRESS ,_param->_nb_inst_branch_complete);
195	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_COMPLETE_FLAG ,_param->_nb_inst_branch_complete);
196	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_MISS_PREDICTION,_param->_nb_inst_branch_complete);
197	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_TAKE ,_param->_nb_inst_branch_complete);
198	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_SRC ,_param->_nb_inst_branch_complete);
199	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_COMPLETE_ADDRESS_DEST ,_param->_nb_inst_branch_complete);
200
201	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_VAL ,_param->_nb_context);
202	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ACK ,_param->_nb_context);
203	// if (_param->_have_port_context_id)
204	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_CONTEXT_ID ,_param->_nb_context);
205	// if (_param->_have_port_depth)
206	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_DEPTH ,_param->_nb_context);
207	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_BRANCH_EVENT_ADDRESS ,_param->_nb_context);
208	// INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_MISS_PREDICTION,_param->_nb_context);
209	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_SRC ,_param->_nb_context);
210	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST_VAL,_param->_nb_context);
211	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_BRANCH_EVENT_ADDRESS_DEST ,_param->_nb_context);
212
213	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_VAL ,_param->_nb_inst_update);
214	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_UPDATE_ACK ,_param->_nb_inst_update);
215	if (_param->_have_port_context_id)
216	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_CONTEXT_ID ,_param->_nb_inst_update);
217	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_MISS_PREDICTION ,_param->_nb_inst_update);
218	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIRECTION_GOOD ,_param->_nb_inst_update);
219	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_VAL ,_param->_nb_inst_update);
220	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_SRC ,_param->_nb_inst_update);
221	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_ADDRESS_DEST ,_param->_nb_inst_update);
222	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_BTB_CONDITION ,_param->_nb_inst_update);
223	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_VAL ,_param->_nb_inst_update);
224	if (_param->_have_port_history)
225	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_DIR_HISTORY ,_param->_nb_inst_update);
226	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_VAL ,_param->_nb_inst_update);
227	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_FLUSH ,_param->_nb_inst_update);
228	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PUSH ,_param->_nb_inst_update);
229	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_ADDRESS ,_param->_nb_inst_update);
230	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_INDEX ,_param->_nb_inst_update);
231	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_UPDATE_RAS_PREDICTION_IFETCH ,_param->_nb_inst_update);
232	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_STATE ,_param->_nb_context);
233	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_TYPE ,_param->_nb_context);
234	if (_param->_have_port_depth)
235	{
236	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table, in_EVENT_DEPTH ,_param->_nb_context);
237	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_CURRENT ,_param->_nb_context);
238	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MIN ,_param->_nb_context);
239	}
240	INSTANCE1_SC_SIGNAL(_Update_Prediction_Table,out_DEPTH_MAX ,_param->_nb_context);
241
242	msg(_("<%s> : Start Simulation ............\n"),name.c_str());
243
244	Time * _time = new Time();
245
246	/********************************************************
247	* Simulation - Begin
248	********************************************************/
249
250	// Initialisation
251
252	const uint32_t seed = 0;
253	//const uint32_t seed = static_cast<uint32_t>(time(NULL));
254
255	srand(seed);
256
257	const int32_t percent_transaction_predict = 75;
258	const int32_t percent_transaction_decod = 75;
259	const int32_t percent_transaction_branch_complete = 75;
260	const int32_t percent_transaction_update = 75;
261	const int32_t percent_transaction_branch_event = 75;
262
263	const bool test1 = true;
264	const bool test2 = true;
265	const bool test3 = true;
266	const bool test4 = true;
267
268	std::list<request_t> ufpt;
269	std::list<request_t> upt;
270	request_t event;
271
272	SC_START(0);
273	LABEL("Initialisation");
274
275	LABEL("Reset");
276	in_NRESET->write(0);
277	SC_START(5);
278	in_NRESET->write(1);
279
280	Tdepth_t ufpt_bottom [_param->_nb_context];
281	Tdepth_t ufpt_top [_param->_nb_context];
282
283	Tdepth_t upt_bottom [_param->_nb_context];
284	Tdepth_t upt_top [_param->_nb_context];
285	Tdepth_t upt_top_event[_param->_nb_context];
286
287	for (uint32_t i=0; i<_param->_nb_context; ++i)
288	{
289	ufpt_bottom [i] = 0;
290	ufpt_top [i] = 0;
291	upt_bottom [i] = 0;
292	upt_top [i] = 0;
293	upt_top_event[i] = 0;
294	}
295
296	for (uint32_t i=0; i<_param->_nb_context; ++i)
297	{
298	TEST(Tdepth_t,out_DEPTH_CURRENT [i]->read(),upt_top [i]);
299	TEST(Tdepth_t,out_DEPTH_MIN [i]->read(),upt_bottom [i]);
300	TEST(Tdepth_t,out_DEPTH_MAX [i]->read(),upt_top [i]);
301	}
302
303	for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
304	{
305	LABEL("Iteration %d",iteration);
306
307	for (uint32_t i=0; i<_param->_nb_inst_predict; ++i)
308	in_PREDICT_VAL [i]->write(0);
309	for (uint32_t i=0; i<_param->_nb_inst_decod; ++i)
310	in_DECOD_VAL [i]->write(0);
311	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; ++i)
312	in_BRANCH_COMPLETE_VAL [i]->write(0);
313	for (uint32_t i=0; i<_param->_nb_context; ++i)
314	in_BRANCH_EVENT_ACK [i]->write(0);
315	for (uint32_t i=0; i<_param->_nb_inst_update; ++i)
316	in_UPDATE_ACK [i]->write(0);
317	for (uint32_t i=0; i<_param->_nb_context; ++i)
318	{
319	in_EVENT_STATE [i]->write(EVENT_STATE_NO_EVENT);
320	in_EVENT_TYPE [i]->write(EVENT_TYPE_NONE );
321	}
322	//---------------------------------------------------------------------
323	//---------------------------------------------------------------------
324	// COMMON CASE
325	//---------------------------------------------------------------------
326	//---------------------------------------------------------------------
327	if (test1)
328	{
329	uint32_t context = rand() % _param->_nb_context;
330
331	{
332	LABEL("PREDICT - fill the queue");
333	uint32_t port = rand() % _param->_nb_inst_predict;
334
335	LABEL(" * context : %d",context);
336	LABEL(" * port : %d",port);
337
338	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
339	{
340	request_t request;
341	request.context = context;
342	request.address_src = 0xdeadbeef+i;
343	request.address_dest = 0x21071981+i;
344	request.address_good = request.address_dest;
345	request.condition = BRANCH_CONDITION_FLAG_SET;
346	request.take = 1;
347	request.take_good = 1;
348	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
349	request.is_accurate = true;
350	request.miss_ifetch = false;
351	request.miss_decod = false;
352	request.miss_commit = false;
353	request.history = i;
354	request.ras_address = 0xdeaddead+i;
355	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
356	request.ufpt_ptr = ufpt_top [context];
357	// request.upt_ptr;
358
359	bool have_transaction = false;
360	do
361	{
362	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
363	in_PREDICT_CONTEXT_ID [port]->write(request.context );
364	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
365	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
366	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
367	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
368	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
369	in_PREDICT_DIR_HISTORY [port]->write(request.history );
370	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
371	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
372
373	if (_param->_have_port_depth)
374	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
375	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
376
377	SC_START(0); // fct melay
378
379	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
380	port,
381	in_PREDICT_VAL [port]->read(),
382	out_PREDICT_ACK [port]->read(),
383	in_PREDICT_BTB_IS_ACCURATE [port]->read());
384
385	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
386	{
387	LABEL("PREDICT [%d] - Transaction accepted",port);
388	have_transaction = true;
389
390	if (_param->_have_port_depth)
391	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
392
393	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
394	}
395
396	SC_START(1); // transition
397
398	} while (not have_transaction);
399
400	ufpt.push_back(request);
401
402	in_PREDICT_VAL [port]->write(0);
403
404	if (_param->_have_port_depth)
405	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
406	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
407	}
408	}
409
410	{
411	LABEL("DECOD");
412	uint32_t port = rand() % _param->_nb_inst_decod;
413
414	LABEL(" * context : %d",context);
415	LABEL(" * port : %d",port);
416
417	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
418	{
419	request_t request = ufpt.front();
420
421	bool have_transaction = false;
422	do
423	{
424	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
425	in_DECOD_CONTEXT_ID [port]->write(request.context );
426	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
427	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
428	in_DECOD_BTB_CONDITION [port]->write(request.condition );
429	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
430	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
431	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
432	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
433	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
434	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
435	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
436
437	SC_START(0); // fct melay
438
439	LABEL("DECOD [%d] %d - %d",
440	port,
441	in_PREDICT_VAL [port]->read(),
442	out_PREDICT_ACK [port]->read());
443
444	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
445	{
446	LABEL("DECOD [%d] - Transaction accepted",port);
447	have_transaction = true;
448
449	request.upt_ptr = upt_top [context];
450	upt.push_back(request);
451	ufpt.pop_front();
452
453	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
454	}
455
456	SC_START(1); // transition
457
458	} while (not have_transaction);
459
460	in_DECOD_VAL [port]->write(0);
461
462	if (_param->_have_port_depth)
463	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
464	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
465	}
466	}
467
468	{
469	LABEL("BRANCH_COMPLETE - hit ifetch");
470
471	uint32_t port = rand() % _param->_nb_inst_branch_complete;
472
473	LABEL(" * port : %d",port);
474
475	std::list<request_t>::iterator it_upt = upt.begin();
476
477	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
478	for (uint32_t i=0; i<upt.size(); i++)
479	{
480	bool have_transaction = false;
481
482	do
483	{
484	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
485	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
486	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
487	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
488	in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag );
489
490	if (_param->_have_port_depth)
491	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
492	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
493
494	SC_START(0);
495
496	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
497
498	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
499	{
500	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
501	have_transaction = true;
502
503	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
504	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
505	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
506	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
507
508	it_upt ++;
509	}
510
511	SC_START(1);
512	} while (not have_transaction);
513
514	in_BRANCH_COMPLETE_VAL [port]->write(0);
515
516	if (_param->_have_port_depth)
517	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
518	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
519	}
520	}
521
522	{
523	LABEL("UPDATE - hit ifetch");
524
525	uint32_t port = 0;
526
527	LABEL(" * port : %d",port);
528	std::list<request_t>::iterator it_upt = upt.begin();
529
530	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
531	for (uint32_t i=0; i<upt.size(); i++)
532	{
533	bool have_transaction = false;
534
535	do
536	{
537	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
538
539	// if (_param->_have_port_depth)
540	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
541	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
542
543	SC_START(0);
544
545	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
546
547	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
548	{
549	LABEL("UPDATE [%d] - Transaction accepted",port);
550	have_transaction = true;
551
552	if (_param->_have_port_context_id)
553	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
554	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
555	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
556	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
557	if (update_btb(it_upt->condition))
558	{
559	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
560	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
561	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
562	}
563	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
564	if (update_dir(it_upt->condition))
565	if (_param->_have_port_history)
566	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
567	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
568	if (update_ras(it_upt->condition))
569	{
570	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
571	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
572	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
573	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
574	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
575	}
576	++ it_upt;
577	}
578
579	SC_START(1);
580	} while (not have_transaction);
581
582	in_UPDATE_ACK [port]->write(0);
583	// if (_param->_have_port_depth)
584	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
585	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
586	}
587	upt.clear();
588	}
589
590	// Wait Garbage Collector
591	{
592	upt_bottom [context] = (upt_bottom [context]+_param->_size_ufpt_queue[context])%_param->_size_upt_queue[context];
593	// upt_top [context] = (upt_top [context]);
594
595	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
596	(upt_top [context] != out_DEPTH_MAX [context]->read()))
597	SC_START(1);
598
599	}
600	}
601
602	//---------------------------------------------------------------------
603	//---------------------------------------------------------------------
604	// DECOD MISS : no RAS in ifetch
605	//---------------------------------------------------------------------
606	//---------------------------------------------------------------------
607	if (test2)
608	{
609	uint32_t context = rand() % _param->_nb_context;
610
611	{
612	LABEL("PREDICT - fill the queue");
613	uint32_t port = rand() % _param->_nb_inst_predict;
614
615	LABEL(" * context : %d",context);
616	LABEL(" * port : %d",port);
617
618	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
619	{
620	request_t request;
621	request.context = context;
622	request.address_src = 0xdeadbeef+i;
623	request.address_dest = 0x21071981+i;
624	request.address_good = request.address_dest;
625	request.condition = BRANCH_CONDITION_FLAG_SET;
626	request.take = 1;
627	request.take_good = 1;
628	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
629	request.is_accurate = true;
630	request.miss_ifetch = false;
631	request.miss_decod = false;
632	request.miss_commit = false;
633	request.history = i;
634	request.ras_address = 0xdeaddead+i;
635	request.ras_index = (0x12345678+i)%_param->_size_ras_index[context];
636	request.ufpt_ptr = ufpt_top [context];
637	// request.upt_ptr;
638
639	bool have_transaction = false;
640	do
641	{
642	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
643	in_PREDICT_CONTEXT_ID [port]->write(request.context );
644	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
645	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
646	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
647	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
648	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
649	in_PREDICT_DIR_HISTORY [port]->write(request.history );
650	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
651	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
652
653	if (_param->_have_port_depth)
654	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
655	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
656
657	SC_START(0); // fct melay
658
659	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
660	port,
661	in_PREDICT_VAL [port]->read(),
662	out_PREDICT_ACK [port]->read(),
663	in_PREDICT_BTB_IS_ACCURATE [port]->read());
664
665	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
666	{
667	LABEL("PREDICT [%d] - Transaction accepted",port);
668	have_transaction = true;
669
670	if (_param->_have_port_depth)
671	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
672
673	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
674	}
675
676	SC_START(1); // transition
677
678	} while (not have_transaction);
679
680	// ufpt.push_back(request);
681
682	in_PREDICT_VAL [port]->write(0);
683
684	if (_param->_have_port_depth)
685	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
686	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
687	}
688	}
689
690	{
691	LABEL("DECOD - Miss");
692	uint32_t port = rand() % _param->_nb_inst_decod;
693
694	LABEL(" * context : %d",context);
695	LABEL(" * port : %d",port);
696
697	request_t request;
698	request.context = context;
699	request.address_src = 0x14011959;
700	request.address_dest = 0x25071959; // after = not take
701	request.address_good = request.address_dest;
702	request.condition = BRANCH_CONDITION_FLAG_SET;
703	request.take = 0;
704	request.take_good = 0;
705	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
706	request.is_accurate = true;
707	request.miss_ifetch = false;
708	request.miss_decod = true ;
709	request.miss_commit = false;
710	request.history = 1;
711	request.ras_address = 0xbabababa;
712	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
713	request.ufpt_ptr = ufpt_top [context];
714
715	event = request;
716
717	// for (uint32_t i=0; i<upt.size(); i++)
718	// just one
719	{
720	bool have_transaction = false;
721	do
722	{
723	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
724	in_DECOD_CONTEXT_ID [port]->write(request.context );
725	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
726	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
727	in_DECOD_BTB_CONDITION [port]->write(request.condition );
728	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
729	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
730	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
731	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
732	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
733	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
734	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
735
736	SC_START(0); // fct melay
737
738	LABEL("DECOD [%d] %d - %d",
739	port,
740	in_PREDICT_VAL [port]->read(),
741	out_PREDICT_ACK [port]->read());
742
743	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
744	{
745	LABEL("DECOD [%d] - Transaction accepted",port);
746	have_transaction = true;
747
748	request.upt_ptr = upt_top [context];
749	upt.push_back(request);
750	// ufpt.pop_front();
751
752	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
753	}
754
755	SC_START(1); // transition
756
757	} while (not have_transaction);
758
759	in_DECOD_VAL [port]->write(0);
760
761	if (_param->_have_port_depth)
762	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
763	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
764	}
765	}
766
767	{
768	LABEL("BRANCH_COMPLETE - hit ifetch");
769
770	uint32_t port = rand() % _param->_nb_inst_branch_complete;
771
772	LABEL(" * port : %d",port);
773
774	std::list<request_t>::iterator it_upt = upt.begin();
775
776	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
777	// for (uint32_t i=0; i<upt.size(); i++)
778	// just one
779	{
780	bool have_transaction = false;
781
782	do
783	{
784	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
785	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
786	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
787	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
788	in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag );
789
790	if (_param->_have_port_depth)
791	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
792	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
793
794	SC_START(0);
795
796	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
797
798	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
799	{
800	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
801	have_transaction = true;
802
803	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
804	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
805	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
806	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
807
808	it_upt ++;
809	}
810
811	SC_START(1);
812	} while (not have_transaction);
813
814	in_BRANCH_COMPLETE_VAL [port]->write(0);
815
816	if (_param->_have_port_depth)
817	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
818	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
819	}
820	}
821
822	{
823	LABEL("UPDATE - hit ifetch");
824
825	uint32_t port = 0;
826
827	LABEL(" * port : %d",port);
828	std::list<request_t>::iterator it_upt = upt.begin();
829
830	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
831	// for (uint32_t i=0; i<upt.size(); i++)
832	// just one
833	{
834	bool have_transaction = false;
835
836	do
837	{
838	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
839
840	// if (_param->_have_port_depth)
841	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
842	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
843
844	SC_START(0);
845
846	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
847
848	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
849	{
850	LABEL("UPDATE [%d] - Transaction accepted",port);
851	have_transaction = true;
852
853	if (_param->_have_port_context_id)
854	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
855	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
856	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
857	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
858	if (update_btb(it_upt->condition))
859	{
860	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
861	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
862	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
863	}
864	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
865
866	if (update_dir(it_upt->condition))
867	if (_param->_have_port_history)
868	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
869	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
870	if (update_ras(it_upt->condition))
871	{
872	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
873	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
874	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
875	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
876	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
877	}
878	++ it_upt;
879	}
880
881	SC_START(1);
882	} while (not have_transaction);
883
884	in_UPDATE_ACK [port]->write(0);
885	// if (_param->_have_port_depth)
886	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
887	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
888	}
889	upt.clear();
890	}
891
892	{
893	LABEL("BRANCH_EVENT - have miss decod");
894
895	uint32_t port = context;
896
897	{
898	bool have_transaction = false;
899
900	do
901	{
902	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
903
904	SC_START(0);
905
906	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
907
908	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
909	{
910	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
911	have_transaction = true;
912
913	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
914	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
915	if (event.take)
916	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
917
918	event.address_src = 0;
919	event.take = 0;
920	event.address_dest = 0;
921	}
922
923	SC_START(1);
924	} while (not have_transaction);
925
926	in_BRANCH_EVENT_ACK [port]->write(0);
927	}
928	}
929
930	{
931	LABEL("EVENT_STATE");
932
933	SC_START(1);
934	in_EVENT_STATE [context]->write(EVENT_STATE_END );
935	in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION);
936
937	SC_START(1);
938	in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT );
939	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
940	}
941
942	// Wait Garbage Collector
943	{
944	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
945	// upt_top [context] = (upt_top [context]);
946
947	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
948	(upt_top [context] != out_DEPTH_MAX [context]->read()))
949	SC_START(1);
950
951	}
952	}
953
954	//---------------------------------------------------------------------
955	//---------------------------------------------------------------------
956	// DECOD MISS : with RAS in ifetch
957	//---------------------------------------------------------------------
958	//---------------------------------------------------------------------
959	if (test3)
960	{
961	uint32_t context = rand() % _param->_nb_context;
962	uint32_t have_ras = false;
963	{
964	LABEL("PREDICT - fill the queue");
965	uint32_t port = rand() % _param->_nb_inst_predict;
966
967	LABEL(" * context : %d",context);
968	LABEL(" * port : %d",port);
969
970	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
971	{
972	request_t request;
973	request.context = context;
974	request.address_src = 0xdeadbeef+i;
975	request.address_dest = 0x21071981+i;
976	request.address_good = request.address_dest;
977	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
978
979	have_ras \|= (update_ras(request.condition));
980
981	request.take = 1;
982	request.take_good = 1;
983	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
984	request.is_accurate = true;
985	request.miss_ifetch = false;
986	request.miss_decod = true ;
987	request.miss_commit = false;
988	request.history = i;
989	request.ras_address = 0x12344321+i;
990	request.ras_index = (043211234+i)%_param->_size_ras_index[context];
991	request.ufpt_ptr = ufpt_top [context];
992	// request.upt_ptr;
993
994	bool have_transaction = false;
995	do
996	{
997	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
998	in_PREDICT_CONTEXT_ID [port]->write(request.context );
999	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1000	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1001	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1002	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1003	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1004	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1005	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1006	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1007
1008	if (_param->_have_port_depth)
1009	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1010	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1011
1012	SC_START(0); // fct melay
1013
1014	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1015	port,
1016	in_PREDICT_VAL [port]->read(),
1017	out_PREDICT_ACK [port]->read(),
1018	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1019
1020	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1021	{
1022	LABEL("PREDICT [%d] - Transaction accepted",port);
1023	have_transaction = true;
1024
1025	if (_param->_have_port_depth)
1026	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1027
1028	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1029	}
1030
1031	SC_START(1); // transition
1032
1033	} while (not have_transaction);
1034
1035	ufpt.push_back(request); // to update
1036
1037	in_PREDICT_VAL [port]->write(0);
1038
1039	if (_param->_have_port_depth)
1040	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1041	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1042	}
1043	}
1044
1045	{
1046	LABEL("DECOD - Miss");
1047	uint32_t port = rand() % _param->_nb_inst_decod;
1048
1049	LABEL(" * context : %d",context);
1050	LABEL(" * port : %d",port);
1051
1052	request_t request;
1053	request.context = context;
1054	request.address_src = 0x14011959;
1055	request.address_dest = 0x25071959; // after = not take
1056	request.address_good = request.address_dest;
1057	request.condition = BRANCH_CONDITION_FLAG_SET;
1058	request.take = 0;
1059	request.take_good = 0;
1060	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1061	request.is_accurate = true;
1062	request.miss_ifetch = false;
1063	request.miss_decod = true ;
1064	request.miss_commit = false;
1065	request.history = 1;
1066	request.ras_address = 0xbabababa;
1067	request.ras_index = (0x87654321)%_param->_size_ras_index[context];
1068	request.ufpt_ptr = ufpt_top [context];
1069
1070	event = request;
1071
1072	// for (uint32_t i=0; i<upt.size(); i++)
1073	// just one
1074	{
1075	bool have_transaction = false;
1076	do
1077	{
1078	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1079	in_DECOD_CONTEXT_ID [port]->write(request.context );
1080	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1081	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1082	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1083	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1084	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1085	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1086	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1087	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1088	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1089	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1090
1091	SC_START(0); // fct melay
1092
1093	LABEL("DECOD [%d] %d - %d",
1094	port,
1095	in_PREDICT_VAL [port]->read(),
1096	out_PREDICT_ACK [port]->read());
1097
1098	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1099	{
1100	LABEL("DECOD [%d] - Transaction accepted",port);
1101	have_transaction = true;
1102
1103	request.upt_ptr = upt_top [context];
1104	upt.push_back(request);
1105	// ufpt.pop_front();
1106
1107	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1108	}
1109
1110	SC_START(1); // transition
1111
1112	} while (not have_transaction);
1113
1114	in_DECOD_VAL [port]->write(0);
1115
1116	if (_param->_have_port_depth)
1117	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1118	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1119	}
1120	}
1121
1122	{
1123	LABEL("BRANCH_COMPLETE - hit ifetch");
1124
1125	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1126
1127	LABEL(" * port : %d",port);
1128
1129	std::list<request_t>::iterator it_upt = upt.begin();
1130
1131	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1132	// for (uint32_t i=0; i<upt.size(); i++)
1133	// just one
1134	{
1135	bool have_transaction = false;
1136
1137	do
1138	{
1139	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1140	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1141	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1142	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_good);
1143	in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag );
1144
1145	if (_param->_have_port_depth)
1146	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1147	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1148
1149	SC_START(0);
1150
1151	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1152
1153	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1154	{
1155	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1156	have_transaction = true;
1157
1158	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1159	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take_good );
1160	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1161	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_good);
1162
1163	it_upt ++;
1164	}
1165
1166	SC_START(1);
1167	} while (not have_transaction);
1168
1169	in_BRANCH_COMPLETE_VAL [port]->write(0);
1170
1171	if (_param->_have_port_depth)
1172	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1173	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1174	}
1175	}
1176
1177	if (have_ras)
1178	{
1179	LABEL("UPDATE - Update UPFT");
1180
1181	uint32_t port = 0;
1182
1183	LABEL(" * port : %d",port);
1184	std::list<request_t>::iterator it_ufpt = ufpt.end();
1185	-- it_ufpt;
1186
1187	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1188	{
1189	bool have_transaction = false;
1190
1191	do
1192	{
1193	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1194
1195	// if (_param->_have_port_depth)
1196	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1197	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1198
1199	SC_START(0);
1200
1201	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1202
1203	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1204	{
1205	LABEL("UPDATE [%d] - Transaction accepted",port);
1206	have_transaction = true;
1207
1208	if (_param->_have_port_context_id)
1209	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1210	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1211	it_ufpt->miss_decod or
1212	it_ufpt->miss_commit ));
1213	// if (update_btb(it_ufpt->condition) or
1214	// update_dir(it_ufpt->condition))
1215	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1216	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1217	// if (update_btb(it_ufpt->condition))
1218	// {
1219	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1220	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1221	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1222	// }
1223	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1224
1225	// if (update_dir(it_ufpt->condition))
1226	// if (_param->_have_port_history)
1227	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1228	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1229	if (update_ras(it_ufpt->condition))
1230	{
1231	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1232	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1233	LABEL("KANE : out_UPDATE_RAS_ADDRESS [port]->read() : %.8x",out_UPDATE_RAS_ADDRESS [port]->read());
1234	LABEL("KANE : it_ufpt->ras_address : %.8x",it_ufpt->ras_address);
1235
1236	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1237	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1238	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1239	}
1240	}
1241
1242	SC_START(1);
1243	} while (not have_transaction);
1244
1245	-- it_ufpt;
1246
1247
1248	in_UPDATE_ACK [port]->write(0);
1249	// if (_param->_have_port_depth)
1250	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1251	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1252	}
1253	}
1254	ufpt.clear();
1255
1256	{
1257	LABEL("UPDATE - hit ifetch");
1258
1259	uint32_t port = 0;
1260
1261	LABEL(" * port : %d",port);
1262	std::list<request_t>::iterator it_upt = upt.begin();
1263
1264	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1265	// for (uint32_t i=0; i<upt.size(); i++)
1266	// just one
1267	{
1268	bool have_transaction = false;
1269
1270	do
1271	{
1272	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1273
1274	// if (_param->_have_port_depth)
1275	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1276	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1277
1278	SC_START(0);
1279
1280	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1281
1282	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1283	{
1284	LABEL("UPDATE [%d] - Transaction accepted",port);
1285	have_transaction = true;
1286
1287	if (_param->_have_port_context_id)
1288	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1289	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1290	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1291	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
1292	if (update_btb(it_upt->condition))
1293	{
1294	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1295	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1296	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1297	}
1298	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
1299
1300	if (update_dir(it_upt->condition))
1301	if (_param->_have_port_history)
1302	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1303	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
1304	if (update_ras(it_upt->condition))
1305	{
1306	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1307	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1308	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1309	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1310	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1311	}
1312	++ it_upt;
1313	}
1314
1315	SC_START(1);
1316	} while (not have_transaction);
1317
1318	in_UPDATE_ACK [port]->write(0);
1319	// if (_param->_have_port_depth)
1320	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1321	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1322	}
1323	}
1324	upt.clear();
1325
1326	{
1327	LABEL("BRANCH_EVENT - have miss decod");
1328
1329	uint32_t port = context;
1330
1331	{
1332	bool have_transaction = false;
1333
1334	do
1335	{
1336	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1337
1338	SC_START(0);
1339
1340	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1341
1342	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1343	{
1344	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1345	have_transaction = true;
1346
1347	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1348	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take);
1349	if (event.take)
1350	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1351
1352	event.address_src = 0;
1353	event.take = 0;
1354	event.address_dest = 0;
1355	}
1356
1357	SC_START(1);
1358	} while (not have_transaction);
1359
1360	in_BRANCH_EVENT_ACK [port]->write(0);
1361	}
1362	}
1363
1364	{
1365	LABEL("EVENT_STATE");
1366
1367	SC_START(1);
1368	in_EVENT_STATE [context]->write(EVENT_STATE_END );
1369	in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION);
1370
1371	SC_START(1);
1372	in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT );
1373	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
1374	}
1375
1376	// Wait Garbage Collector
1377	{
1378	upt_bottom [context] = (upt_bottom [context]+1)%_param->_size_upt_queue[context];
1379	// upt_top [context] = (upt_top [context]);
1380
1381	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
1382	(upt_top [context] != out_DEPTH_MAX [context]->read()))
1383	SC_START(1);
1384
1385	}
1386	}
1387
1388	//---------------------------------------------------------------------
1389	//---------------------------------------------------------------------
1390	// COMMIT MISS : with RAS in UPFT and UPT
1391	//---------------------------------------------------------------------
1392	//---------------------------------------------------------------------
1393	if (test4)
1394	{
1395	uint32_t context = rand() % _param->_nb_context;
1396	uint32_t have_ufpt_ras = false;
1397	uint32_t have_upt_ras = false;
1398	{
1399	LABEL("PREDICT - fill the queue");
1400	uint32_t port = rand() % _param->_nb_inst_predict;
1401
1402	LABEL(" * context : %d",context);
1403	LABEL(" * port : %d",port);
1404
1405	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1406	{
1407	request_t request;
1408	request.context = context;
1409	request.address_src = rand();
1410	request.address_dest = rand();
1411
1412	request.condition = (rand()%2)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_FLAG_SET;
1413
1414	request.take = 1;
1415	request.take_good = 1;
1416	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1417	request.is_accurate = true ;
1418	request.miss_ifetch = false;
1419	request.miss_decod = false;
1420	request.miss_commit = false;
1421	request.history = i;
1422	request.ras_address = rand();
1423	request.ras_index = rand()%_param->_size_ras_index[context];
1424	request.ufpt_ptr = ufpt_top [context];
1425	// request.upt_ptr;
1426
1427	bool have_transaction = false;
1428	do
1429	{
1430	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1431	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1432	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1433	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1434	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1435	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1436	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1437	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1438	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1439	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1440
1441	if (_param->_have_port_depth)
1442	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1443	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1444
1445	SC_START(0); // fct melay
1446
1447	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1448	port,
1449	in_PREDICT_VAL [port]->read(),
1450	out_PREDICT_ACK [port]->read(),
1451	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1452
1453	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1454	{
1455	LABEL("PREDICT [%d] - Transaction accepted",port);
1456	have_transaction = true;
1457
1458	if (_param->_have_port_depth)
1459	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1460
1461	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1462	}
1463
1464	SC_START(1); // transition
1465
1466	} while (not have_transaction);
1467
1468	ufpt.push_back(request); // to update
1469
1470	in_PREDICT_VAL [port]->write(0);
1471
1472	if (_param->_have_port_depth)
1473	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1474	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1475	}
1476	}
1477
1478	{
1479	LABEL("DECOD");
1480	uint32_t port = rand() % _param->_nb_inst_decod;
1481
1482	LABEL(" * context : %d",context);
1483	LABEL(" * port : %d",port);
1484
1485	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1486	{
1487	request_t request = ufpt.front();
1488
1489	bool have_transaction = false;
1490	do
1491	{
1492	in_DECOD_VAL [port]->write((rand()%100)<percent_transaction_decod);
1493	in_DECOD_CONTEXT_ID [port]->write(request.context );
1494	in_DECOD_BTB_ADDRESS_SRC [port]->write(request.address_src );
1495	in_DECOD_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1496	in_DECOD_BTB_CONDITION [port]->write(request.condition );
1497	in_DECOD_BTB_LAST_TAKE [port]->write(request.take );
1498	in_DECOD_RAS_ADDRESS [port]->write(request.ras_address );
1499	in_DECOD_RAS_INDEX [port]->write(request.ras_index );
1500	in_DECOD_UPDATE_PREDICTION_ID [port]->write(request.ufpt_ptr );
1501	in_DECOD_MISS_IFETCH [port]->write(request.miss_ifetch );
1502	in_DECOD_MISS_DECOD [port]->write(request.miss_decod );
1503	in_DECOD_IS_ACCURATE [port]->write(request.is_accurate );
1504
1505	have_upt_ras \|= (update_ras(request.condition));
1506
1507	SC_START(0); // fct melay
1508
1509	LABEL("DECOD [%d] %d - %d",
1510	port,
1511	in_DECOD_VAL [port]->read(),
1512	out_DECOD_ACK [port]->read());
1513
1514	if (in_DECOD_VAL [port]->read() and out_DECOD_ACK [port]->read())
1515	{
1516	LABEL("DECOD [%d] - Transaction accepted",port);
1517	have_transaction = true;
1518
1519	request.upt_ptr = upt_top [context];
1520	upt.push_back(request);
1521	ufpt.pop_front();
1522
1523	upt_top [context] = (upt_top [context]+1)%_param->_size_upt_queue[context];
1524	}
1525
1526	SC_START(1); // transition
1527
1528	} while (not have_transaction);
1529
1530	in_DECOD_VAL [port]->write(0);
1531
1532	if (_param->_have_port_depth)
1533	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1534	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1535	}
1536	}
1537
1538	{
1539	LABEL("PREDICT - fill the queue");
1540	uint32_t port = rand() % _param->_nb_inst_predict;
1541
1542	LABEL(" * context : %d",context);
1543	LABEL(" * port : %d",port);
1544
1545	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1546	{
1547	request_t request;
1548	request.context = context;
1549	request.address_src = rand();
1550	request.address_dest = rand();
1551	request.address_good = request.address_dest;
1552	request.condition = (rand()%2)?BRANCH_CONDITION_NONE_WITH_WRITE_STACK:BRANCH_CONDITION_FLAG_SET;
1553
1554	have_ufpt_ras \|= (update_ras(request.condition));
1555
1556	request.take = 1;
1557	request.take_good = 1;
1558	request.flag = (request.condition == BRANCH_CONDITION_FLAG_SET)?request.take_good:(not request.take_good);
1559	request.is_accurate = true ;
1560	request.miss_ifetch = false;
1561	request.miss_decod = false;
1562	request.miss_commit = true;
1563	request.history = i;
1564	request.ras_address = rand();
1565	request.ras_index = rand()%_param->_size_ras_index[context];
1566	request.ufpt_ptr = ufpt_top [context];
1567	// request.upt_ptr;
1568
1569	bool have_transaction = false;
1570	do
1571	{
1572	in_PREDICT_VAL [port]->write((rand()%100)<percent_transaction_predict);
1573	in_PREDICT_CONTEXT_ID [port]->write(request.context );
1574	in_PREDICT_BTB_ADDRESS_SRC [port]->write(request.address_src );
1575	in_PREDICT_BTB_ADDRESS_DEST [port]->write(request.address_dest);
1576	in_PREDICT_BTB_CONDITION [port]->write(request.condition );
1577	in_PREDICT_BTB_LAST_TAKE [port]->write(request.take );
1578	in_PREDICT_BTB_IS_ACCURATE [port]->write(request.is_accurate );
1579	in_PREDICT_DIR_HISTORY [port]->write(request.history );
1580	in_PREDICT_RAS_ADDRESS [port]->write(request.ras_address );
1581	in_PREDICT_RAS_INDEX [port]->write(request.ras_index );
1582
1583	if (_param->_have_port_depth)
1584	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1585	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1586
1587	SC_START(0); // fct melay
1588
1589	LABEL("PREDICT [%d] %d - %d (accurate : %d).",
1590	port,
1591	in_PREDICT_VAL [port]->read(),
1592	out_PREDICT_ACK [port]->read(),
1593	in_PREDICT_BTB_IS_ACCURATE [port]->read());
1594
1595	if (in_PREDICT_VAL [port]->read() and out_PREDICT_ACK [port]->read())
1596	{
1597	LABEL("PREDICT [%d] - Transaction accepted",port);
1598	have_transaction = true;
1599
1600	if (_param->_have_port_depth)
1601	TEST(Tprediction_ptr_t,out_PREDICT_UPDATE_PREDICTION_ID [port]->read(),ufpt_top [context]);
1602
1603	ufpt_top [context] = (ufpt_top [context]+1)%_param->_size_ufpt_queue[context];
1604	}
1605
1606	SC_START(1); // transition
1607
1608	} while (not have_transaction);
1609
1610	ufpt.push_back(request); // to update
1611
1612	in_PREDICT_VAL [port]->write(0);
1613
1614	if (_param->_have_port_depth)
1615	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1616	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1617	}
1618	}
1619
1620	std::list<request_t>::iterator it_event;
1621	{
1622	LABEL("BRANCH_COMPLETE - Miss ifetch");
1623
1624	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1625
1626	LABEL(" * port : %d",port);
1627
1628	// middle
1629	it_event = upt.begin();
1630	for (uint32_t i=0; i < (upt.size()>>1); ++i)
1631	it_event ++;
1632
1633	for (std::list<request_t>::iterator it_upt = it_event;
1634	it_upt != upt.end();
1635	++it_upt)
1636	it_upt->miss_commit = true;
1637
1638	if (update_ras(it_event->condition))
1639	{
1640	it_event->address_good = ~(it_event->address_dest);
1641	}
1642	else
1643	{
1644	it_event->address_good = it_event->address_dest;
1645	it_event->flag = not it_event->flag;
1646	it_event->take_good = not it_event->take_good;
1647	}
1648
1649	event = *it_event;
1650
1651
1652	// for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1653	// for (uint32_t i=0; i<upt.size(); i++)
1654	// just one
1655	{
1656	bool have_transaction = false;
1657
1658	do
1659	{
1660	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1661	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_event->context );
1662	in_BRANCH_COMPLETE_DEPTH [port]->write(it_event->upt_ptr );
1663	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_event->address_good);
1664	in_BRANCH_COMPLETE_FLAG [port]->write(it_event->flag );
1665
1666	if (_param->_have_port_depth)
1667	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1668	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1669
1670	SC_START(0);
1671
1672	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1673
1674	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1675	{
1676	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1677	LABEL(" * CONTEXT_ID %d" ,it_event->context );
1678	LABEL(" * DEPTH %d" ,it_event->upt_ptr );
1679	LABEL(" * CONDITION %d" ,it_event->condition );
1680	LABEL(" * ADDRESS %.8x",it_event->address_good);
1681	LABEL(" * FLAG %d" ,it_event->flag );
1682
1683	have_transaction = true;
1684
1685	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_event->miss_commit );
1686	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_event->take_good );
1687	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_event->address_src );
1688	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_event->address_good);
1689
1690	upt_top_event [it_event->context] = upt_top [it_event->context];
1691	upt_top [it_event->context] = it_event->upt_ptr;
1692	}
1693
1694	SC_START(1);
1695	} while (not have_transaction);
1696
1697	in_BRANCH_COMPLETE_VAL [port]->write(0);
1698
1699	if (_param->_have_port_depth)
1700	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1701	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1702	}
1703	}
1704
1705	{
1706	LABEL("BRANCH_COMPLETE - Hit ifetch");
1707
1708	uint32_t port = rand() % _param->_nb_inst_branch_complete;
1709
1710	LABEL(" * port : %d",port);
1711
1712	std::list<request_t>::iterator it_upt = upt.begin();
1713
1714	while (it_upt != it_event)
1715	{
1716	bool have_transaction = false;
1717
1718	do
1719	{
1720	in_BRANCH_COMPLETE_VAL [port]->write((rand()%100)<percent_transaction_branch_complete);
1721	in_BRANCH_COMPLETE_CONTEXT_ID [port]->write(it_upt->context );
1722	in_BRANCH_COMPLETE_DEPTH [port]->write(it_upt->upt_ptr );
1723	in_BRANCH_COMPLETE_ADDRESS [port]->write(it_upt->address_dest);
1724	in_BRANCH_COMPLETE_FLAG [port]->write(it_upt->flag );
1725
1726	if (_param->_have_port_depth)
1727	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1728	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1729
1730	SC_START(0);
1731
1732	LABEL("BRANCH_COMPLETE [%d] %d - %d.",port,in_BRANCH_COMPLETE_VAL [port]->read(),out_BRANCH_COMPLETE_ACK [port]->read());
1733
1734	if (in_BRANCH_COMPLETE_VAL [port]->read() and out_BRANCH_COMPLETE_ACK [port]->read())
1735	{
1736	LABEL("BRANCH_COMPLETE [%d] - Transaction accepted",port);
1737	LABEL(" * CONTEXT_ID %d" ,it_upt->context );
1738	LABEL(" * DEPTH %d" ,it_upt->upt_ptr );
1739	LABEL(" * CONDITION %d" ,it_upt->condition );
1740	LABEL(" * ADDRESS %.8x",it_upt->address_dest);
1741	LABEL(" * FLAG %d" ,it_upt->flag );
1742
1743	have_transaction = true;
1744
1745	TEST(Tcontrol_t,out_BRANCH_COMPLETE_MISS_PREDICTION[port]->read(),it_upt->miss_commit );
1746	TEST(Tcontrol_t,out_BRANCH_COMPLETE_TAKE [port]->read(),it_upt->take );
1747	it_upt->take_good = it_upt->take;
1748	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_SRC [port]->read(),it_upt->address_src );
1749	TEST(Taddress_t,out_BRANCH_COMPLETE_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1750
1751	it_upt++;
1752	}
1753
1754	SC_START(1);
1755	} while (not have_transaction);
1756
1757	in_BRANCH_COMPLETE_VAL [port]->write(0);
1758
1759	if (_param->_have_port_depth)
1760	TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1761	TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1762	}
1763	}
1764
1765	if (have_ufpt_ras)
1766	{
1767	LABEL("UPDATE - Update UPFT");
1768
1769	uint32_t port = 0;
1770
1771	LABEL(" * port : %d",port);
1772	std::list<request_t>::iterator it_ufpt = ufpt.end();
1773	-- it_ufpt;
1774
1775	for (uint32_t i=0; i<_param->_size_ufpt_queue[context]; i++)
1776	{
1777	bool have_transaction = false;
1778
1779	do
1780	{
1781	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1782
1783	// if (_param->_have_port_depth)
1784	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1785	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1786
1787	SC_START(0);
1788
1789	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1790
1791	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1792	{
1793	LABEL("UPDATE [%d] - Transaction accepted",port);
1794	have_transaction = true;
1795
1796	if (_param->_have_port_context_id)
1797	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_ufpt->context);
1798	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),(it_ufpt->miss_ifetch or
1799	it_ufpt->miss_decod or
1800	it_ufpt->miss_commit ));
1801	// if (update_btb(it_ufpt->condition) or
1802	// update_dir(it_ufpt->condition))
1803	// TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_ufpt->take_good);
1804	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),0);
1805	// if (update_btb(it_ufpt->condition))
1806	// {
1807	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_ufpt->address_src);
1808	// TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_ufpt->address_dest);
1809	// TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_ufpt->condition);
1810	// }
1811	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),0);
1812
1813	// if (update_dir(it_ufpt->condition))
1814	// if (_param->_have_port_history)
1815	// TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_ufpt->history);
1816	// TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_ufpt->condition));
1817	if (update_ras(it_ufpt->condition))
1818	{
1819	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1820	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_ufpt->condition));
1821	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_ufpt->ras_address);
1822	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_ufpt->ras_index);
1823	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_ufpt->miss_ifetch);
1824	}
1825	}
1826
1827	SC_START(1);
1828	} while (not have_transaction);
1829
1830	-- it_ufpt;
1831
1832
1833	in_UPDATE_ACK [port]->write(0);
1834	// if (_param->_have_port_depth)
1835	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), ufpt_bottom [context]);
1836	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), ufpt_top [context]);
1837	}
1838	}
1839	ufpt.clear();
1840
1841	{
1842	LABEL("UPDATE - upt (after event)");
1843
1844	uint32_t port = 0;
1845
1846	LABEL(" * port : %d",port);
1847	std::list<request_t>::iterator it_upt = upt.end();
1848
1849	// for (uint32_t i=0; i<upt.size(); i++)
1850	do
1851	{
1852	--it_upt;
1853
1854	bool have_transaction = false;
1855
1856	if (need_update(it_upt->condition))
1857	do
1858	{
1859	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
1860
1861	// if (_param->_have_port_depth)
1862	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1863	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1864
1865	SC_START(0);
1866
1867	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
1868
1869	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
1870	{
1871	LABEL("UPDATE [%d] - Transaction accepted",port);
1872	LABEL(" * address_src : %.8x",it_upt->address_src);
1873	LABEL(" * out_UPDATE_BTB_ADDRESS_SRC : %.8x",out_UPDATE_BTB_ADDRESS_SRC[port]->read());
1874
1875	have_transaction = true;
1876
1877	bool btb_val = ((it_upt == it_event) and
1878	(update_btb(it_upt->condition)));
1879	bool dir_val = ((it_upt == it_event) and
1880	update_dir(it_upt->condition) and
1881	not (it_upt->miss_ifetch or it_upt->miss_decod));
1882	bool ras_val = update_ras(it_upt->condition);
1883
1884	if (_param->_have_port_context_id)
1885	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
1886	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
1887	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),btb_val);
1888
1889	if (btb_val)
1890	{
1891	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
1892	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
1893	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
1894	}
1895	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),dir_val);
1896
1897	if (dir_val)
1898	{
1899	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
1900	if (_param->_have_port_history)
1901	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
1902	}
1903	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),ras_val);
1904
1905	if (ras_val)
1906	{
1907	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
1908	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
1909	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
1910	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
1911	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
1912	}
1913
1914	// -- it_upt;
1915	}
1916
1917	SC_START(1);
1918	} while (not have_transaction);
1919
1920	upt.pop_back();
1921	in_UPDATE_ACK [port]->write(0);
1922	// if (_param->_have_port_depth)
1923	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
1924	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
1925	}
1926	while (it_upt != it_event);
1927
1928	}
1929
1930	{
1931	LABEL("BRANCH_EVENT - have miss decod");
1932
1933	uint32_t port = context;
1934
1935	{
1936	bool have_transaction = false;
1937
1938	do
1939	{
1940	in_BRANCH_EVENT_ACK [port]->write((rand()%100)<percent_transaction_branch_event);
1941
1942	SC_START(0);
1943
1944	LABEL("BRANCH_EVENT [%d] %d - %d.",port,out_BRANCH_EVENT_VAL [port]->read(),in_BRANCH_EVENT_ACK [port]->read());
1945
1946	if (out_BRANCH_EVENT_VAL [port]->read() and in_BRANCH_EVENT_ACK [port]->read())
1947	{
1948	LABEL("BRANCH_EVENT [%d] - Transaction accepted",port);
1949	have_transaction = true;
1950
1951	LABEL(" * event.address_src : %.8x,",event.address_src );
1952	LABEL(" * event.address_good : %.8x,",event.address_good);
1953	LABEL(" * event.take : %.8x,",event.take );
1954
1955	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_SRC [port]->read(),event.address_src);
1956	TEST(Tcontrol_t,out_BRANCH_EVENT_ADDRESS_DEST_VAL [port]->read(),event.take_good);
1957	if (event.take_good)
1958	TEST(Taddress_t,out_BRANCH_EVENT_ADDRESS_DEST [port]->read(),event.address_good);
1959
1960	event.address_src = 0;
1961	event.take = 0;
1962	event.address_dest = 0;
1963	}
1964
1965	SC_START(1);
1966	} while (not have_transaction);
1967
1968	in_BRANCH_EVENT_ACK [port]->write(0);
1969	}
1970	}
1971
1972	{
1973	LABEL("EVENT_STATE");
1974
1975	SC_START(1);
1976	in_EVENT_STATE [context]->write(EVENT_STATE_END );
1977	in_EVENT_TYPE [context]->write(EVENT_TYPE_MISS_SPECULATION);
1978
1979	SC_START(1);
1980	in_EVENT_STATE [context]->write(EVENT_STATE_NO_EVENT );
1981	in_EVENT_TYPE [context]->write(EVENT_TYPE_NONE );
1982	}
1983
1984	{
1985	LABEL("UPDATE - upt (before event)");
1986
1987	uint32_t port = 0;
1988
1989	LABEL(" * port : %d",port);
1990	LABEL(" * size : %d",upt.size());
1991	std::list<request_t>::iterator it_upt = upt.begin();
1992
1993	for (uint32_t i=0; i<upt.size(); i++)
1994	{
1995	bool have_transaction = false;
1996
1997	do
1998	{
1999	in_UPDATE_ACK [port]->write((rand()%100)<percent_transaction_update);
2000
2001	// if (_param->_have_port_depth)
2002	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2003	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2004
2005	SC_START(0);
2006
2007	LABEL("UPDATE [%d] %d - %d.",port,out_UPDATE_VAL [port]->read(),in_UPDATE_ACK [port]->read());
2008
2009	if (out_UPDATE_VAL [port]->read() and in_UPDATE_ACK [port]->read())
2010	{
2011	LABEL("UPDATE [%d] - Transaction accepted",port);
2012	have_transaction = true;
2013
2014	if (_param->_have_port_context_id)
2015	TEST(Tcontext_t ,out_UPDATE_CONTEXT_ID [port]->read(),it_upt->context);
2016	TEST(Tcontrol_t ,out_UPDATE_MISS_PREDICTION [port]->read(),it_upt->miss_commit);
2017	TEST(Tcontrol_t ,out_UPDATE_DIRECTION_GOOD [port]->read(),it_upt->take_good);
2018	TEST(Tcontrol_t ,out_UPDATE_BTB_VAL [port]->read(),update_btb(it_upt->condition));
2019	if (update_btb(it_upt->condition))
2020	{
2021	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_SRC [port]->read(),it_upt->address_src);
2022	TEST(Taddress_t ,out_UPDATE_BTB_ADDRESS_DEST [port]->read(),it_upt->address_dest);
2023	TEST(Tbranch_condition_t,out_UPDATE_BTB_CONDITION [port]->read(),it_upt->condition);
2024	}
2025	TEST(Tcontrol_t ,out_UPDATE_DIR_VAL [port]->read(),update_dir(it_upt->condition) and not (it_upt->miss_ifetch or it_upt->miss_decod));
2026
2027	if (update_dir(it_upt->condition))
2028	if (_param->_have_port_history)
2029	TEST(Thistory_t ,out_UPDATE_DIR_HISTORY [port]->read(),it_upt->history);
2030	TEST(Tcontrol_t ,out_UPDATE_RAS_VAL [port]->read(),update_ras(it_upt->condition));
2031	if (update_ras(it_upt->condition))
2032	{
2033	// TEST(Tcontrol_t ,out_UPDATE_RAS_FLUSH [port]->read(),0);
2034	TEST(Tcontrol_t ,out_UPDATE_RAS_PUSH [port]->read(),push_ras (it_upt->condition));
2035	TEST(Taddress_t ,out_UPDATE_RAS_ADDRESS [port]->read(),it_upt->ras_address);
2036	TEST(Tptr_t ,out_UPDATE_RAS_INDEX [port]->read(),it_upt->ras_index);
2037	TEST(Tcontrol_t ,out_UPDATE_RAS_PREDICTION_IFETCH [port]->read(),not it_upt->miss_ifetch);
2038	}
2039
2040	++ it_upt;
2041	}
2042
2043	SC_START(1);
2044	} while (not have_transaction);
2045
2046	in_UPDATE_ACK [port]->write(0);
2047	// if (_param->_have_port_depth)
2048	// TEST(Tdepth_t,out_DEPTH_MIN [context]->read(), upt_bottom [context]);
2049	// TEST(Tdepth_t,out_DEPTH_MAX [context]->read(), upt_top [context]);
2050	}
2051	}
2052	upt.clear();
2053
2054	// Wait Garbage Collector
2055	{
2056	LABEL("GARBAGE COLLECTOR");
2057	LABEL(" * upt bottom : %d",upt_bottom [context]);
2058	LABEL(" * upt top : %d",upt_top [context]);
2059
2060	upt_top [context] = (upt_top_event [context]);
2061	upt_bottom [context] = (upt_top [context]);
2062
2063	while ((upt_bottom [context] != out_DEPTH_MIN [context]->read()) or
2064	(upt_top [context] != out_DEPTH_MAX [context]->read()))
2065	{
2066	SC_START(1);
2067	}
2068
2069	}
2070	}
2071
2072	}// ITERATION
2073
2074	/********************************************************
2075	* Simulation - End
2076	********************************************************/
2077
2078	TEST_OK ("End of Simulation");
2079	delete _time;
2080
2081	msg(_("<%s> : ............ Stop Simulation\n"),name.c_str());
2082
2083	delete in_CLOCK;
2084	delete in_NRESET;
2085
2086	// ~~~~~[ Interface : "predict" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2087	delete [] in_PREDICT_VAL ;
2088	delete [] out_PREDICT_ACK ;
2089	delete [] in_PREDICT_CONTEXT_ID ;
2090	delete [] in_PREDICT_BTB_ADDRESS_SRC ;
2091	delete [] in_PREDICT_BTB_ADDRESS_DEST ;
2092	delete [] in_PREDICT_BTB_CONDITION ;
2093	delete [] in_PREDICT_BTB_LAST_TAKE ;
2094	delete [] in_PREDICT_BTB_IS_ACCURATE ;
2095	delete [] in_PREDICT_DIR_HISTORY ;
2096	delete [] in_PREDICT_RAS_ADDRESS ;
2097	delete [] in_PREDICT_RAS_INDEX ;
2098	delete [] out_PREDICT_UPDATE_PREDICTION_ID;
2099
2100	// ~~~~~[ Interface : "decod" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2101	delete [] in_DECOD_VAL ;
2102	delete [] out_DECOD_ACK ;
2103	delete [] in_DECOD_CONTEXT_ID ;
2104	delete [] in_DECOD_BTB_ADDRESS_SRC ;
2105	delete [] in_DECOD_BTB_ADDRESS_DEST ;
2106	delete [] in_DECOD_BTB_CONDITION ;
2107	delete [] in_DECOD_BTB_LAST_TAKE ;
2108	delete [] in_DECOD_RAS_ADDRESS ;
2109	delete [] in_DECOD_RAS_INDEX ;
2110	delete [] in_DECOD_MISS_IFETCH ;
2111	delete [] in_DECOD_MISS_DECOD ;
2112	delete [] in_DECOD_UPDATE_PREDICTION_ID ;
2113	//delete [] out_DECOD_DEPTH ;
2114	delete [] in_DECOD_IS_ACCURATE ;
2115
2116	// ~~~~~[ Interface : "branch_complete" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2117	delete [] in_BRANCH_COMPLETE_VAL ;
2118	delete [] out_BRANCH_COMPLETE_ACK ;
2119	delete [] in_BRANCH_COMPLETE_CONTEXT_ID ;
2120	delete [] in_BRANCH_COMPLETE_DEPTH ;
2121	delete [] in_BRANCH_COMPLETE_ADDRESS ;
2122	delete [] in_BRANCH_COMPLETE_FLAG ;
2123	delete [] out_BRANCH_COMPLETE_MISS_PREDICTION;
2124	delete [] out_BRANCH_COMPLETE_TAKE ;
2125	delete [] out_BRANCH_COMPLETE_ADDRESS_SRC ;
2126	delete [] out_BRANCH_COMPLETE_ADDRESS_DEST ;
2127
2128	// ~~~~~[ Interface : "branch_event" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2129	delete [] out_BRANCH_EVENT_VAL ;
2130	delete [] in_BRANCH_EVENT_ACK ;
2131	//delete [] in_BRANCH_EVENT_CONTEXT_ID ;
2132	//delete [] in_BRANCH_EVENT_DEPTH ;
2133	//delete [] out_BRANCH_EVENT_MISS_PREDICTION;
2134	delete [] out_BRANCH_EVENT_ADDRESS_SRC ;
2135	delete [] out_BRANCH_EVENT_ADDRESS_DEST_VAL;
2136	delete [] out_BRANCH_EVENT_ADDRESS_DEST ;
2137
2138	// ~~~~~[ Interface : "update" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2139	delete [] out_UPDATE_VAL ;
2140	delete [] in_UPDATE_ACK ;
2141	delete [] out_UPDATE_CONTEXT_ID ;
2142	delete [] out_UPDATE_MISS_PREDICTION ;
2143	delete [] out_UPDATE_DIRECTION_GOOD ;
2144	delete [] out_UPDATE_BTB_VAL ;
2145	delete [] out_UPDATE_BTB_ADDRESS_SRC ;
2146	delete [] out_UPDATE_BTB_ADDRESS_DEST ;
2147	delete [] out_UPDATE_BTB_CONDITION ;
2148	delete [] out_UPDATE_DIR_VAL ;
2149	delete [] out_UPDATE_DIR_HISTORY ;
2150	delete [] out_UPDATE_RAS_VAL ;
2151	delete [] out_UPDATE_RAS_FLUSH ;
2152	delete [] out_UPDATE_RAS_PUSH ;
2153	delete [] out_UPDATE_RAS_ADDRESS ;
2154	delete [] out_UPDATE_RAS_INDEX ;
2155	delete [] out_UPDATE_RAS_PREDICTION_IFETCH;
2156
2157	DELETE1_SC_SIGNAL( in_EVENT_STATE ,_param->_nb_context);
2158	DELETE1_SC_SIGNAL( in_EVENT_TYPE ,_param->_nb_context);
2159	DELETE1_SC_SIGNAL( in_EVENT_DEPTH ,_param->_nb_context);
2160
2161	// ~~~~~[ Interface : "depth" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2162	delete [] out_DEPTH_CURRENT;
2163	delete [] out_DEPTH_MIN;
2164	delete [] out_DEPTH_MAX;
2165
2166	#endif
2167
2168	delete _Update_Prediction_Table;
2169	#ifdef STATISTICS
2170	delete _parameters_statistics;
2171	#endif
2172	}

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