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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp @ 134

Last change on this file since 134 was 134, checked in by rosiere, 15 years ago
1) valgrind fix 2) debug file on/off
Property svn:keywords set to `Id`
File size: 72.4 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Update_Prediction_Table_transition.cpp 134 2009-07-15 08:41:01Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace prediction_unit {
17	namespace update_prediction_table {
18
19	#undef FUNCTION
20	#define FUNCTION "Update_Prediction_Table::transition"
21	void Update_Prediction_Table::transition (void)
22	{
23	log_begin(Update_Prediction_Table,FUNCTION);
24	log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Initialisation
29
30	reg_UPDATE_PRIORITY = 0;
31
32	// All pointer is set at 0
33	for (uint32_t i=0; i<_param->_nb_context; i++)
34	{
35	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
36	{
37	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
38	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition = 0; // not necessary
39	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src = 0; // not necessary
40	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest = 0; // not necessary
41	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take = 0; // not necessary
42	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate = 0; // not necessary
43	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history = 0; // not necessary
44	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras = 0; // not necessary
45	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras = 0; // not necessary
46	}
47	reg_UFPT_BOTTOM [i] = 0;
48	reg_UFPT_TOP [i] = 0;
49	reg_UFPT_UPDATE [i] = 0;
50	reg_UFPT_NB_NEED_UPDATE [i] = 0;
51	reg_UFPT_NB_UPDATE [i] = 0;
52
53	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
54	{
55	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY;
56	reg_UPDATE_PREDICTION_TABLE [i][j]._condition = 0; // not necessary
57	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src = 0; // not necessary
58	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest = 0; // not necessary
59	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take = 0; // not necessary
60	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take = 0; // not necessary
61	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate = 0; // not necessary
62	reg_UPDATE_PREDICTION_TABLE [i][j]._history = 0; // not necessary
63	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras = 0; // not necessary
64	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras = 0; // not necessary
65	reg_UPDATE_PREDICTION_TABLE [i][j]._ifetch_prediction= 0; // not necessary
66	reg_UPDATE_PREDICTION_TABLE [i][j]._miss_commit = 0; // not necessary
67	reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = 0; // not necessary
68	reg_UPDATE_PREDICTION_TABLE [i][j]._miss_prediction = 0; // not necessary
69	}
70	reg_UPT_BOTTOM [i] = 0;
71	reg_UPT_TOP [i] = 0;
72	reg_UPT_TOP_EVENT [i] = 0;
73	reg_UPT_UPDATE [i] = 0;
74	reg_UPT_EMPTY [i] = true;
75
76	reg_IS_ACCURATE [i] = true;
77
78	reg_UFPT_EVENT_STATE [i] = UFPT_EVENT_STATE_OK;
79	reg_UPT_EVENT_STATE [i] = UPT_EVENT_STATE_OK;
80
81	reg_EVENT_UPT_PTR [i] = 0; // not necessary
82	reg_EVENT_UPT_FULL [i] = 0; // not necessary
83
84	// reg_EVENT_STATE [i] = EVENT_STATE_OK; // not necessary
85	// reg_EVENT_IS_BRANCH [i] = true ; // not necessary
86
87	reg_EVENT_DEPTH [i] = 0; // not necessary
88	reg_EVENT_ADDRESS_SRC [i] = 0; // not necessary
89	reg_EVENT_ADDRESS_DEST_VAL [i] = 0; // not necessary
90	reg_EVENT_ADDRESS_DEST [i] = 0; // not necessary
91	reg_EVENT_CAN_CONTINUE [i] = 0; // not necessary
92
93	}
94	}
95	else
96	{
97	bool flush_UFPT [_param->_nb_context];
98	for (uint32_t i=0; i<_param->_nb_context; i++)
99	{
100	flush_UFPT [i] = false;
101	}
102
103	// ===================================================================
104	// =====[ GARBAGE COLLECTOR ]=========================================
105	// ===================================================================
106
107	// Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot
108	// * Update state -> new status is "empty"
109	// * Update pointer (bottom and accurate)
110	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (BEGIN)");
111	for (uint32_t i=0; i<_param->_nb_context; i++)
112	{
113	// -----------------------------
114	// UPDATE_FETCH_PREDICTION_TABLE
115	// -----------------------------
116	{
117	uint32_t bottom = reg_UFPT_BOTTOM [i];
118	bool end = (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END);
119
120	// Test if bottom slot can be remove
121	if (end)
122	{
123	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom);
124	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom);
125
126	// Free slot
127	reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
128	// Update pointer
129	bottom = (bottom+1)%_param->_size_ufpt_queue[i];
130
131	reg_UFPT_BOTTOM [i] = bottom;
132	}
133	}
134
135	// -----------------------
136	// UPDATE_PREDICTION_TABLE
137	// -----------------------
138	{
139	uint32_t bottom = reg_UPT_BOTTOM [i];
140
141	// if (reg_UPT_EVENT_STATE [i] == UPT_EVENT_STATE_OK)
142	{
143	bool end = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END);
144
145	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (before) : %d",bottom);
146	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state is STATE_END : %d",end);
147
148	if (end)
149	{
150	#if defined(DEBUG) and defined(DEBUG_Update_Prediction_Table) and (DEBUG_Update_Prediction_Table == true)
151	if (log_file_generate)
152	if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._retire_ok)
153	{
154	uint32_t num_thread = _param->_translate_num_context_to_num_thread [i];
155	branchement_log_file [num_thread]
156	<< std::hex
157	<< "0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " "
158	<< "0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " "
159	<< std::dec
160	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " - "
161	<< "[" << simulation_cycle() << "] " << " "
162	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._miss_prediction << " "
163	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._ifetch_prediction << " "
164	<< "(" << toString(reg_UPDATE_PREDICTION_TABLE [i][bottom]._condition) << ")"
165	<< std::endl;
166	}
167	#endif
168
169	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom);
170	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
171	// Free slot
172	reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
173
174	// Update pointer
175	reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
176
177	// Free a slot, test if bottom pointer overtake the top pointer
178	if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i])
179	reg_UPT_EMPTY [i] = true; // free a slot
180
181	reg_EVENT_UPT_FULL [i] = false;
182	}
183
184	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (after ) : %d",reg_UPT_BOTTOM [i]);
185	}
186	}
187	}
188
189	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)");
190
191	// ===================================================================
192	// =====[ PREDICT ]===================================================
193	// ===================================================================
194
195	// An ifetch_unit compute next cycle and have an branch : predict_val is set
196	// * Alloc new entry -> new status is "wait decod"
197	// * Save input (to restore in miss or error)
198	// * Update pointer
199
200	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
201	// Test if have a transaction
202	if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i])
203	{
204	// get transaction information
205	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
206	uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i];
207	Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
208	bool is_accurate = (_param->_always_accurate_predict or
209	(_param->_can_accurate_predict and PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i])));
210
211
212	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i);
213	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
214	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
215	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %d",condition);
216	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is_accurate : %d",is_accurate);
217
218	#ifdef DEBUG_TEST
219	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
220	throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state."));
221	#endif
222
223	// Ifetch unit have fetch an instruction bundle with a branchement.
224	// Insert in UFPT
225	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top);
226	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD;
227
228	// Write information
229	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition;
230	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]);
231	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
232	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]);
233	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = is_accurate;
234	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0;
235	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]);
236	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]);
237
238	// Update pointer
239	reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context];
240
241	// Test if this branchement need update
242	if (need_update(condition))
243	{
244	reg_UFPT_NB_NEED_UPDATE [context] ++;
245	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
246	}
247	}
248
249	// ===================================================================
250	// =====[ DECOD ]=====================================================
251	// ===================================================================
252
253
254	// An decod is detected by decod stage
255	// 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch
256	// * Update state, wait_decod -> wait_end
257	// * Pop ufpt -> push upt
258	// * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod
259	// 2) Miss : The instruction bundle have a branch but it is not predicted
260	// * Flush ufpt
261	// * decod information is write in upt
262
263	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
264	// Test if have a decod transaction
265	if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i])
266	{
267	// Read information
268	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
269	Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]);
270	Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]);
271	uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i];
272	uint32_t top_next = (upt_ptr_write+1)%_param->_size_upt_queue [context];
273	Tbranch_condition_t condition ;
274	Tcontrol_t is_accurate;
275	Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]);
276	Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
277	Tcontrol_t direction = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]);
278
279	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i);
280	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
281	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch);
282	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod);
283	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write);
284
285	// In decod step, two miss type :
286	// miss_ifetch = branch is previously predict (predict interface), but it's not the good
287	// miss_decod = branch was not detected
288	if (not (miss_ifetch or miss_decod))
289	{
290	// Normal case : branch is previous predicted, change state of branch
291
292	// Read ufpt_ptr (send in predic step)
293	uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
294
295	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read);
296
297	#ifdef DEBUG_TEST
298	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
299	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
300	#endif
301	// Change state
302	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
303	reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
304
305	// Push upt (from Pop ufpt)
306	condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
307	is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
308
309	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
310	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
311	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
312	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ;
313	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
314	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
315	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ;
316	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
317	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ;
318	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch
319
320	// Update pointer (now, this instruction is not in ufpt)
321	if (need_update(condition))
322	{
323	reg_UFPT_NB_NEED_UPDATE [context] --;
324	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
325	}
326	}
327	else
328	{
329	// Have a miss !!!
330	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss !!!");
331
332	condition = PORT_READ(in_DECOD_BTB_CONDITION [i]);
333	is_accurate = (_param->_always_accurate_decod or
334	(_param->_can_accurate_decod and PORT_READ(in_DECOD_IS_ACCURATE [i])));
335
336	// if can_continue, don't wait the end of all instruction
337	// (can_continue = not miss_commit and the destination is accurate (know))
338	Tcontrol_t can_continue = is_accurate;
339
340	#ifdef DEBUG_TEST
341	if (reg_UPT_EVENT_STATE [context] != UPT_EVENT_STATE_OK)
342	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt event state."));
343	if (reg_UFPT_EVENT_STATE [context] != UFPT_EVENT_STATE_OK)
344	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt event state."));
345	#endif
346
347	// miss_ifetch -> need flush ufpt
348	// miss_decod -> not necessary
349	// if can_continue (destination is know) and direction is not take (instruction in ifetch_queue can be valid)
350	bool flush_ufpt = (not (can_continue and not direction and not miss_ifetch));
351
352	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * can_continue: %d",can_continue);
353	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * direction : %d",direction );
354	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch );
355	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flush_ufpt: %d",flush_ufpt );
356
357	// Test if can continue without flushing the ufpt (and ifetch_queue)
358	if (flush_ufpt)
359	{
360	// // Optimisation : Test if ufpt have entry that need update prediction struction (as Return Address Stack)
361	// if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
362	// {
363	// // Change state
364	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
365	// reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT;
366
367	// // @@@
368	// // // Have an actual event ?
369	// // if (not reg_EVENT_VAL [context])
370	// // reg_EVENT_UPT_PTR [context] = upt_ptr_write;
371	// }
372	// else
373	// {
374	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- UPT_EVENT_STATE_KO_MISS_WAIT_UFPT (decod - miss - flush ufpt)",context);
375	// // just wait ufpt, don't flush upt
376	// reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_MISS_WAIT_UFPT;
377	// }
378
379	reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT;
380	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT_STATE [%d] <- %s (decod, miss)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
381
382	// Need Flush UPFT
383	flush_UFPT [context] = true;
384
385	// Write information
386	// reg_EVENT_IS_BRANCH [context] = true;
387	reg_EVENT_DEPTH [context] = upt_ptr_write;
388	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
389	reg_EVENT_ADDRESS_DEST_VAL[context] = direction;
390	reg_EVENT_ADDRESS_DEST [context] = address_dest;
391	reg_EVENT_CAN_CONTINUE [context] = can_continue;
392	}
393	// else can continue
394
395	// Push upt (from decod interface)
396	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
397	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ;
398	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest;
399	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = direction ;
400	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
401	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
402	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction
403	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]);
404	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]);
405	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction
406	}
407
408	// In all case !!!
409	#ifdef DEBUG_TEST
410	if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY)
411	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state."));
412	#endif
413
414	// Change state
415	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write);
416	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END;
417	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._retire_ok = false;
418	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._miss_commit = false;
419
420	// Write new accurate
421	#ifdef DEBUG_TEST
422	if (not reg_IS_ACCURATE [context] and not is_accurate)
423	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag."));
424	#endif
425
426	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is_accurate : %d",is_accurate);
427
428	reg_IS_ACCURATE [context] = is_accurate;
429
430	// Update pointer
431	reg_UPT_TOP [context] = top_next;
432	reg_UPT_EMPTY [context] = false; // new instruction
433	}
434
435	// ===================================================================
436	// =====[ UPDATE ]====================================================
437	// ===================================================================
438	{
439	bool can_continue [_param->_nb_context];
440	for (uint32_t i=0; i<_param->_nb_context; ++i)
441	can_continue [i] = true;
442
443	// For each updated instruction
444	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
445	{
446	Tcontext_t context = internal_UPDATE_CONTEXT_ID [i];
447
448	// Test if transaction
449	// (an val_with_out is an update and don't need update prediction structure
450	if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or
451	(internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context]))
452	{
453	Tdepth_t depth = internal_UPDATE_DEPTH [i];
454
455	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i);
456	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
457	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
458
459	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [context];
460
461	// One interface to two source :
462	// * from ufpt -> newest prediction
463	// * from upt -> oldest prediction
464	if (internal_UPDATE_FROM_UFPT [i])
465	{
466	// if free a slot, also all queue is updated
467	// Last slot ?
468	if ((--reg_UFPT_NB_UPDATE [context])==0)
469	{
470	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT_EVENT [%d] <- UFPT_EVENT_STATE_OK (update - end flush ufpt)",context);
471	reg_UFPT_EVENT_STATE [context] = UFPT_EVENT_STATE_OK;
472	reg_UFPT_NB_NEED_UPDATE [context] = 0;
473
474	// // Test upt event to change state
475	// // test if upt wait ufpt
476	// switch (upt_event_state)
477	// {
478	// // this case when don't need flush upt (miss decod and can continue)
479	// case UPT_EVENT_STATE_KO_MISS_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
480	// case UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_OK ; break;
481	// default : break;
482	// }
483
484	// reg_UPT_EVENT_STATE [context] = upt_event_state;
485	}
486
487	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table");
488
489	// Change state
490	#ifdef DEBUG_TEST
491	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT)
492	throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state."));
493	#endif
494
495	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth);
496
497	reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END;
498
499	// Update pointer
500	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]);
501	reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
502	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]);
503	}
504	else
505	{
506	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table");
507	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (before) : %d",reg_UPT_UPDATE [context]);
508	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(upt_event_state).c_str());
509
510	// Change state
511	#ifdef DEBUG_TEST
512	if (internal_UPDATE_RAS [i])
513	{
514	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and
515	(reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) )
516	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
517	}
518	else
519	{
520	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK )
521	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
522	}
523	#endif
524
525	#ifdef STATISTICS
526	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
527	#endif
528	bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK);
529	bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
530
531	// Test if branch is valid (prediction can be incorrect)
532	if (ok or ko)
533	{
534	reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true;
535	reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_prediction = ko;
536
537	#ifdef STATISTICS
538	if (usage_is_set(_usage,USE_STATISTICS))
539	{
540	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._ifetch_prediction)
541	(*_stat_nb_branch_ifetch_prediction [context])++;
542	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate)
543	(*_stat_nb_branch_accurate [context])++;
544	}
545	#endif
546	}
547
548	// Have an update, test the state to transiste to the good state
549	if (ko)
550	{
551	// Ko
552	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth);
553
554	// Wait update of context_state
555	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
556
557	reg_EVENT_UPT_PTR [context] = depth;
558
559	#ifdef STATISTICS
560	if (usage_is_set(_usage,USE_STATISTICS))
561	(*_stat_nb_branch_miss [context][condition])++;
562	#endif
563	}
564	else
565	{
566	// ok or event
567
568	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth);
569	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END;
570
571	#ifdef STATISTICS
572	if (usage_is_set(_usage,USE_STATISTICS))
573	{
574	if (ok)
575	(*_stat_nb_branch_hit [context][condition]) ++;
576	else
577	(*_stat_nb_branch_unused [context]) ++;
578	}
579	#endif
580	}
581
582	// Test if freeing the branch with no accurate ?
583	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko)
584	reg_IS_ACCURATE [context] = true;
585
586	// Update pointer
587	// * if update RAS : update pointer is decreaste until it equal at top pointer
588	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * internal_UPDATE_RAS [%d] : %d",i,internal_UPDATE_RAS [i]);
589
590	if (internal_UPDATE_RAS [i])
591	{
592	// if end_event, restart too bottom, else decrease pointer
593	bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]);
594
595	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * end_event : %d",end_event);
596	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",reg_UPT_BOTTOM[context]);
597
598	if (end_event)
599	{
600	reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);
601	// reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context];
602
603	switch (upt_event_state)
604	{
605	// this case when don't need flush upt (miss decod and can continue)
606	case UPT_EVENT_STATE_KO_MISS_FLUSH_UPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
607	case UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT :
608	{
609	upt_event_state = UPT_EVENT_STATE_OK;
610	reg_UPT_TOP [context] = reg_UPT_TOP_EVENT [context];
611	reg_UPT_UPDATE [context] = reg_UPT_TOP_EVENT [context];
612
613	break;
614	}
615	default : break;
616	}
617
618	}
619	else
620	{
621	// else, decrease update pointer
622	reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1);
623	}
624	}
625	else
626	{
627	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * next update");
628
629	// increase pointer
630	reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
631	}
632
633	// special case :
634	if ((upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE) and
635	(reg_UPT_UPDATE [context] == reg_EVENT_UPT_PTR [context]))
636	{
637	reg_UPT_TOP [context] = reg_UPT_TOP_EVENT [context];
638	reg_UPT_UPDATE [context] = reg_UPT_TOP_EVENT [context];
639	reg_IS_ACCURATE [context] = true;
640
641	upt_event_state = UPT_EVENT_STATE_OK;
642	}
643
644	reg_UPT_EVENT_STATE [context] = upt_event_state;
645
646	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (after ) : %d",reg_UPT_UPDATE[context]);
647	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(reg_UPT_EVENT_STATE [context]).c_str());
648	}
649	}
650	else
651	can_continue [context] = false;
652	}
653
654	// Round robin
655	reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context;
656	}
657
658	// ===================================================================
659	// =====[ BRANCH_COMPLETE ]===========================================
660	// ===================================================================
661
662	// The branch is complete
663	// * Hit prediction :
664	// * update status
665	// * Miss prediction :
666	{
667	bool branch_complete_miss [_param->_nb_context];
668	for (uint32_t i=0; i<_param->_nb_context; ++i)
669	branch_complete_miss [i] = false;
670
671	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
672	if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
673	{
674	// Read information
675	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
676	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
677	Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
678	Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i];
679	Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];
680
681	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [context];
682
683	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);
684	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
685	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
686	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);
687	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(upt_event_state).c_str());
688
689	// Test if the completed branch is a speculation miss
690	if (miss)
691	{
692	// special case : two branch complete on the same context.
693	// when the re order keep the order, the branch complete j is most speculative that the branch comple i if i < j
694	if (not branch_complete_miss [context])
695	{
696	branch_complete_miss [context] = true;
697	// Flush UPT
698	// get information
699	uint32_t top = reg_UPT_TOP [context];
700	uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;
701
702	Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
703	upt_state_t top_state = reg_UPDATE_PREDICTION_TABLE [context][top]._state;
704
705	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_event_state : %s",toString(upt_event_state).c_str());
706	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top_state : %s",toString(top_state).c_str());
707
708	bool previous_ufpt_event = (reg_UFPT_EVENT_STATE [context] == UFPT_EVENT_STATE_KO_FLUSH);
709
710
711	bool previous_upt_event = (false
712	or (upt_event_state == UPT_EVENT_STATE_KO_MISS_WAIT_UFPT )
713	or (upt_event_state == UPT_EVENT_STATE_KO_MISS_FLUSH_UPT )
714	or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT)
715	or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT)
716	or (upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE)
717	or (top_state == UPDATE_PREDICTION_STATE_END_KO )
718	or (top_state == UPDATE_PREDICTION_STATE_KO )
719	);
720
721	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
722	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
723	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_upt_event : %d",previous_upt_event);
724	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_ufpt_event : %d",previous_ufpt_event);
725	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [context]);
726
727	// Have a miss !!!
728	// Flush UPFT
729	flush_UFPT [context] \|= not previous_ufpt_event;
730
731	// Test if the entry wait the branchment (else, they have a previous event)
732	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
733	{
734	// All instruction between the instruction and the top is disable
735	for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
736	j!=top;
737	j=(j+1)%_param->_size_upt_queue[context])
738	{
739	reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
740	reg_UPDATE_PREDICTION_TABLE [context][j]._retire_ok = false; // event
741	}
742
743	// New top
744	reg_UPT_TOP [context] = depth;
745
746	if (not previous_upt_event)
747	{
748	reg_UPT_TOP_EVENT [context] = top;
749	reg_UPT_UPDATE [context] = new_update;
750	}
751	else
752	{
753	// Have event. Top index this slot
754	reg_UPDATE_PREDICTION_TABLE [context][top]._retire_ok = false;
755
756	switch (top_state)
757	{
758	case UPDATE_PREDICTION_STATE_END_KO :
759	case UPDATE_PREDICTION_STATE_END :
760	{
761	// Have already update predictor
762	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END;
763	reg_UPT_UPDATE [context] = new_update;
764	break;
765	}
766	case UPDATE_PREDICTION_STATE_KO :
767	{
768	// Doesn't have update predictor
769	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
770	break;
771	}
772	default :
773	{
774	// reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
775	// break;
776
777	#ifdef DEBUG_TEST
778	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
779	#endif
780	}
781	}
782	}
783
784	if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
785	reg_UPT_EMPTY [context] = true;
786
787	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
788	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
789
790	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE [%d] : %d",context,reg_UFPT_NB_NEED_UPDATE [context]);
791
792	// if ( (reg_UFPT_NB_NEED_UPDATE [context] > 0) or
793	// (reg_UFPT_NB_UPDATE [context] > 0))
794	// {
795	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
796	// reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
797	// }
798	// else
799	// {
800	// // if (not previous_update_ras)
801	// {
802	// // have ras prediction ?
803	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
804
805	// reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
806
807	// }
808	// }
809
810	reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_MISS_FLUSH_UPT;
811	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT_STATE [%d] <- %s (branch_complete, ifetch hit)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
812
813	// reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT;
814
815	// else no update
816
817	// reg_EVENT_IS_BRANCH [context] = true;
818	reg_EVENT_DEPTH [context] = depth;
819	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
820	reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
821	reg_EVENT_ADDRESS_DEST [context] = good_addr;
822	reg_EVENT_CAN_CONTINUE [context] = false;
823
824	}
825
826	reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_commit = true;
827	}
828	}
829	else
830	{
831	// Hit case
832
833	// #ifdef DEBUG_TEST
834	// if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
835	// throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
836	// #endif
837
838	// In same cycle, can have a previous branch_complete
839	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
840	{
841	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
842	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
843	}
844	}
845
846	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(reg_UPT_EVENT_STATE [context]).c_str());
847
848	// In all case : update good_take
849	reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;
850
851	// Write address_dest if need read register
852	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
853
854	if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
855	(condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or
856	(condition == BRANCH_CONDITION_READ_STACK ) )
857	reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
858	}
859	}
860
861	// ===================================================================
862	// =====[ BRANCH_EVENT ]==============================================
863	// ===================================================================
864	for (uint32_t i=0; i<_param->_nb_context; i++)
865	if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
866	{
867	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i);
868
869	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
870
871	switch (upt_event_state)
872	{
873	case UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT : upt_event_state = UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT; break;
874	case UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT; break;
875	default : break; // an other branch is occured
876	}
877
878	reg_UPT_EVENT_STATE [i] = upt_event_state;
879	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s (branch_event)",toString(upt_event_state).c_str());
880	}
881
882	// ===================================================================
883	// =====[ EVENT ]=====================================================
884	// ===================================================================
885	for (uint32_t i=0; i<_param->_nb_context; ++i)
886	if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i])
887	{
888	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT");
889
890	//----------------------------------------------------------------
891	// Cases
892	//----------------------------------------------------------------
893	// * EVENT_TYPE_NONE - nothing
894	// * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer
895	// * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer
896	// * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update
897	// * EVENT_TYPE_SPR_ACCESS - nothing
898	// * EVENT_TYPE_MSYNC - nothing
899	// * EVENT_TYPE_PSYNC - nothing
900	// * EVENT_TYPE_CSYNC - nothing
901
902	Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]);
903	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
904
905	// Test if end of miss -> all previous branch is complete
906	// -> all next branch is finish
907
908	switch (event_type)
909	{
910	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
911	{
912	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_BRANCH_MISS_SPECULATION");
913
914	switch (upt_event_state)
915	{
916	case UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT :
917	{
918	Tdepth_t depth = reg_EVENT_UPT_PTR [i];
919	Tdepth_t update = reg_UPT_UPDATE [i];
920
921	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
922
923	if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO)
924	{
925	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth);
926
927	reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END;
928	}
929
930	// Special case : branch_complete a speculative branch and the context_state signal the end of this event before the complete of previous branch
931	if (depth != update)
932	{
933	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_COMMIT_WAIT_END_UPDATE (event)",i);
934	upt_event_state = UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE;
935
936	break; // stop here
937	}
938
939	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
940	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
941
942	// break; continue
943	}
944	case UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT :
945	{
946	// Change state
947	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i);
948
949	upt_event_state = UPT_EVENT_STATE_OK;
950	reg_IS_ACCURATE [i] = true;
951
952	break;
953	}
954	default : break; // an other branch is occured
955	}
956
957	break;
958	}
959	case EVENT_TYPE_LOAD_MISS_SPECULATION :
960	case EVENT_TYPE_EXCEPTION :
961	{
962	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_LOAD_MISS_SPECULATION");
963
964	// Have a miss !!!
965	// Flush UPFT
966	flush_UFPT [i] = true;
967
968	if (upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE)
969	{
970	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
971	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
972	reg_IS_ACCURATE [i] = true;
973
974	upt_event_state = UPT_EVENT_STATE_OK;
975	}
976
977	// Flush UPT
978	uint32_t bottom = reg_UPT_BOTTOM [i];
979
980	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom);
981
982	// event_state_t event_state = reg_EVENT_STATE [i];
983	// bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
984	// (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or
985	// (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
986	// (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
987
988	bool find = false; // have slot to update ???
989	bool find_top = false;
990	Tdepth_t top = bottom;
991	Tdepth_t update = bottom;
992	bool empty = reg_UPT_EMPTY [i];
993
994	// flush all slot, because this event is in head of rob
995	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
996	{
997	Tdepth_t x = (bottom+j)%_param->_size_upt_queue[i];
998
999	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d] : %s",x,toString(reg_UPDATE_PREDICTION_TABLE [i][x]._state).c_str());
1000
1001	if ((reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_END) and
1002	(reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY))
1003	{
1004	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find at UPT[%d]",x);
1005
1006	find = true; // find a not empty slot
1007	reg_UPDATE_PREDICTION_TABLE [i][x]._state = UPDATE_PREDICTION_STATE_EVENT;
1008	reg_UPDATE_PREDICTION_TABLE [i][x]._retire_ok = false;
1009	update = x;
1010	}
1011
1012	if (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY)
1013	if (not find_top)
1014	{
1015	top = x;
1016	find_top = true;
1017	}
1018	}
1019
1020	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find);
1021	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
1022	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update : %d",update);
1023
1024	// Test if have update slot
1025	reg_UPT_TOP_EVENT [i] = reg_UPT_TOP[i];
1026	if (find)
1027	{
1028	// TODO : special case : event is an exception on branch, also depth is not valid
1029	reg_UPT_TOP [i] = top; // depth is again valid
1030
1031	if (bottom == reg_UPT_TOP [i])
1032	reg_UPT_EMPTY [i] = true;
1033
1034	reg_UPT_UPDATE [i] = update;
1035	}
1036
1037	// new state :
1038	// * test if ufpt is empty
1039	// * ok : flush upft and upt
1040	// * ko : test if have previous flush upt
1041	// * ok : nothing
1042	// * ko : flush upt
1043	// reg_EVENT_VAL [i] = find;
1044	// reg_EVENT_IS_BRANCH [i] = false;
1045	// reg_EVENT_UPT_PTR [i] = ((top==0)?_param->_size_upt_queue[i]:top)-1; ///// ZE MODIF
1046	reg_EVENT_UPT_PTR [i] = top;
1047	reg_EVENT_UPT_FULL [i] = (not empty and (bottom == reg_UPT_TOP [i]));
1048	// reg_EVENT_DEPTH [i] = PORT_READ(in_EVENT_DEPTH [i]);//(top+1)%_param->_size_upt_queue[i];
1049	reg_EVENT_DEPTH [i] = top;
1050
1051	// reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State
1052	// reg_EVENT_ADDRESS_DEST_VAL[i] = good_take;
1053	// reg_EVENT_ADDRESS_DEST [i] = good_addr;
1054
1055	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
1056	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
1057	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
1058
1059	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]);
1060	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]);
1061	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL [i]);
1062	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1063	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
1064
1065	if (find)
1066	{
1067	// have ras prediction ?
1068	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT (event - find)",i);
1069
1070	upt_event_state = UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT;
1071	}
1072	else
1073	{
1074	// special case : nothing
1075	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT (event - not find)",i);
1076
1077	// reg_EVENT_VAL [i] = false;
1078
1079	upt_event_state = UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT;
1080	}
1081
1082	break;
1083	}
1084	default :
1085	{
1086	// nothing
1087	break;
1088	}
1089	}
1090
1091	reg_UPT_EVENT_STATE [i] = upt_event_state;
1092	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s (branch_event)",toString(upt_event_state).c_str());
1093	}
1094
1095	// ===================================================================
1096	// =====[ FLUSH ]=====================================================
1097	// ===================================================================
1098
1099	for (uint32_t i=0; i<_param->_nb_context; ++i)
1100	{
1101	if (flush_UFPT [i])
1102	{
1103	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table");
1104	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i);
1105	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1106
1107	// It's to accelerate miss speculation -> associative access
1108	if (reg_UFPT_NB_NEED_UPDATE [i] == 0)
1109	{
1110	// No entry need prediction, flush all entry -> Reset
1111	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
1112	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
1113	reg_UFPT_BOTTOM [i] = 0;
1114	reg_UFPT_TOP [i] = 0;
1115	}
1116	else
1117	{
1118	uint32_t bottom = reg_UFPT_BOTTOM [i];
1119	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
1120	{
1121	uint32_t index = (bottom+j)%_param->_size_ufpt_queue[i];
1122	// EMPTY : no event
1123	// END : already update
1124	// EVENT : previous event
1125	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
1126	{
1127	reg_UFPT_UPDATE [i] = index;
1128	reg_UFPT_NB_UPDATE [i] ++;
1129	reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
1130	}
1131	}
1132
1133	// Change state
1134	reg_UFPT_EVENT_STATE [i] = UFPT_EVENT_STATE_KO_FLUSH;
1135	}
1136
1137	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]);
1138
1139	}
1140
1141	// Change state on UPT
1142	{
1143	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
1144	ufpt_event_state_t ufpt_event_state = reg_UFPT_EVENT_STATE [i];
1145
1146	// Test upt event to change state
1147	// test if upt wait ufpt
1148	if (ufpt_event_state == UFPT_EVENT_STATE_OK)
1149	switch (upt_event_state)
1150	{
1151	// this case when don't need flush upt (miss decod and can continue)
1152	case UPT_EVENT_STATE_KO_MISS_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
1153	case UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_OK ; break;
1154	default : break;
1155	}
1156
1157	reg_UPT_EVENT_STATE [i] = upt_event_state;
1158	}
1159	}
1160
1161	#ifdef STATISTICS
1162	if (usage_is_set(_usage,USE_STATISTICS))
1163	for (uint32_t i=0; i<_param->_nb_context; i++)
1164	{
1165	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
1166	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
1167	(*_stat_ufpt_queue_nb_elt [i]) ++;
1168	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
1169	if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)
1170	(*_stat_upt_queue_nb_elt [i]) ++;
1171	}
1172	#endif
1173
1174	// ===================================================================
1175	// =====[ PRINT ]=====================================================
1176	// ===================================================================
1177
1178	#if (DEBUG >= DEBUG_TRACE)
1179	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table");
1180	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY);
1181	for (uint32_t i=0; i<_param->_nb_context; i++)
1182	{
1183	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]);
1184	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UFPT_STATE : %s" ,toString(reg_UFPT_EVENT_STATE [i]).c_str());
1185	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_STATE : %s" ,toString(reg_UPT_EVENT_STATE [i]).c_str());
1186	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]);
1187	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]);
1188	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d" ,reg_EVENT_UPT_FULL [i]);
1189	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_IS_BRANCH : %d" ,reg_EVENT_IS_BRANCH [i]);
1190	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
1191	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2);
1192	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]);
1193	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST [i],reg_EVENT_ADDRESS_DEST [i]<<2);
1194	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_CAN_CONTINUE : %d" ,reg_EVENT_CAN_CONTINUE [i]);
1195
1196	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump UFPT [%d] (Update_Fetch_Prediction_Table)",i);
1197	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]);
1198	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]);
1199	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]);
1200	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1201	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
1202	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
1203	{
1204	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d, %.8lld %.8x (%.8x) %.4d - %s",
1205	j,
1206	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition,
1207	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src,
1208	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src<<2,
1209	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest,
1210	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest<<2,
1211	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take,
1212	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate,
1213	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history,
1214	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras,
1215	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras<<2,
1216	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras,
1217	toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str()
1218	);
1219	}
1220
1221	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump UPT [%d] (Update_Prediction_Table)",i);
1222	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
1223	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
1224	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]);
1225	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
1226	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
1227	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
1228	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d %.1d, %.8lld %.8x (%.8x) %.4d - %s",
1229	j,
1230	reg_UPDATE_PREDICTION_TABLE [i][j]._condition,
1231	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src,
1232	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src<<2,
1233	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest,
1234	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest<<2,
1235	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take,
1236	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take,
1237	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate,
1238	reg_UPDATE_PREDICTION_TABLE [i][j]._history,
1239	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras,
1240	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras<<2,
1241	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras,
1242	toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str()
1243	);
1244	}
1245	#endif
1246
1247	#ifdef DEBUG_TEST
1248	for (uint32_t i=0; i<_param->_nb_context; i++)
1249	{
1250	if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i])
1251	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i]));
1252	if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i])
1253	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i]));
1254	}
1255	#endif
1256
1257	}
1258
1259
1260	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
1261	end_cycle ();
1262	#endif
1263
1264	log_end(Update_Prediction_Table,FUNCTION);
1265	};
1266
1267	}; // end namespace update_prediction_table
1268	}; // end namespace prediction_unit
1269	}; // end namespace front_end
1270	}; // end namespace multi_front_end
1271	}; // end namespace core
1272
1273	}; // end namespace behavioural
1274	}; // end namespace morpheo
1275	#endif

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