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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp @ 145

Last change on this file since 145 was 145, checked in by rosiere, 14 years ago
1) add test with SPECINT2K 2) new config of Selftest 3) modif RAT to support multiple depth_save ... but not finish (need fix Update Prediction Table) 4) add Function_pointer but need fix
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File size: 72.4 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Update_Prediction_Table_transition.cpp 145 2010-10-13 18:15:51Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace prediction_unit {
17	namespace update_prediction_table {
18
19	#undef FUNCTION
20	#define FUNCTION "Update_Prediction_Table::transition"
21	void Update_Prediction_Table::transition (void)
22	{
23	log_begin(Update_Prediction_Table,FUNCTION);
24	log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Initialisation
29
30	reg_UPDATE_PRIORITY = 0;
31
32	// All pointer is set at 0
33	for (uint32_t i=0; i<_param->_nb_context; i++)
34	{
35	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
36	{
37	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
38	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition = 0; // not necessary
39	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src = 0; // not necessary
40	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest = 0; // not necessary
41	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take = 0; // not necessary
42	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate = 0; // not necessary
43	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history = 0; // not necessary
44	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras = 0; // not necessary
45	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras = 0; // not necessary
46	}
47	reg_UFPT_BOTTOM [i] = 0;
48	reg_UFPT_TOP [i] = 0;
49	reg_UFPT_UPDATE [i] = 0;
50	reg_UFPT_NB_NEED_UPDATE [i] = 0;
51	reg_UFPT_NB_UPDATE [i] = 0;
52
53	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
54	{
55	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY;
56	reg_UPDATE_PREDICTION_TABLE [i][j]._condition = 0; // not necessary
57	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src = 0; // not necessary
58	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest = 0; // not necessary
59	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take = 0; // not necessary
60	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take = 0; // not necessary
61	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate = 0; // not necessary
62	reg_UPDATE_PREDICTION_TABLE [i][j]._history = 0; // not necessary
63	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras = 0; // not necessary
64	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras = 0; // not necessary
65	reg_UPDATE_PREDICTION_TABLE [i][j]._ifetch_prediction= 0; // not necessary
66	reg_UPDATE_PREDICTION_TABLE [i][j]._miss_commit = 0; // not necessary
67	reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = 0; // not necessary
68	reg_UPDATE_PREDICTION_TABLE [i][j]._miss_prediction = 0; // not necessary
69	}
70	reg_UPT_BOTTOM [i] = 0;
71	reg_UPT_TOP [i] = 0;
72	reg_UPT_TOP_EVENT [i] = 0;
73	reg_UPT_UPDATE [i] = 0;
74	reg_UPT_EMPTY [i] = true;
75
76	reg_IS_ACCURATE [i] = true;
77
78	reg_UFPT_EVENT_STATE [i] = UFPT_EVENT_STATE_OK;
79	reg_UPT_EVENT_STATE [i] = UPT_EVENT_STATE_OK;
80
81	reg_EVENT_UPT_PTR [i] = 0; // not necessary
82	reg_EVENT_UPT_FULL [i] = 0; // not necessary
83
84	// reg_EVENT_STATE [i] = EVENT_STATE_OK; // not necessary
85	// reg_EVENT_IS_BRANCH [i] = true ; // not necessary
86
87	reg_EVENT_DEPTH [i] = 0; // not necessary
88	reg_EVENT_ADDRESS_SRC [i] = 0; // not necessary
89	reg_EVENT_ADDRESS_DEST_VAL [i] = 0; // not necessary
90	reg_EVENT_ADDRESS_DEST [i] = 0; // not necessary
91	reg_EVENT_CAN_CONTINUE [i] = 0; // not necessary
92	}
93	}
94	else
95	{
96	bool flush_UFPT [_param->_nb_context];
97	for (uint32_t i=0; i<_param->_nb_context; i++)
98	{
99	flush_UFPT [i] = false;
100	}
101
102	// ===================================================================
103	// =====[ GARBAGE COLLECTOR ]=========================================
104	// ===================================================================
105
106	// Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot
107	// * Update state -> new status is "empty"
108	// * Update pointer (bottom and accurate)
109	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (BEGIN)");
110	for (uint32_t i=0; i<_param->_nb_context; i++)
111	{
112	// -----------------------------
113	// UPDATE_FETCH_PREDICTION_TABLE
114	// -----------------------------
115	{
116	uint32_t bottom = reg_UFPT_BOTTOM [i];
117	bool end = (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END);
118
119	// Test if bottom slot can be remove
120	if (end)
121	{
122	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom);
123	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom);
124
125	// Free slot
126	reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
127	// Update pointer
128	bottom = (bottom+1)%_param->_size_ufpt_queue[i];
129
130	reg_UFPT_BOTTOM [i] = bottom;
131	}
132	}
133
134	// -----------------------
135	// UPDATE_PREDICTION_TABLE
136	// -----------------------
137	{
138	uint32_t bottom = reg_UPT_BOTTOM [i];
139
140	// if (reg_UPT_EVENT_STATE [i] == UPT_EVENT_STATE_OK)
141	{
142	bool end = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END);
143
144	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (before) : %d",bottom);
145	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state is STATE_END : %d",end);
146
147	if (end)
148	{
149	#if defined(DEBUG) and defined(DEBUG_Update_Prediction_Table) and (DEBUG_Update_Prediction_Table == true)
150	if (log_file_generate)
151	if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._retire_ok)
152	{
153	uint32_t num_thread = _param->_translate_num_context_to_num_thread [i];
154	branchement_log_file [num_thread]
155	<< std::hex
156	<< "0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " "
157	<< "0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " "
158	<< std::dec
159	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " - "
160	<< "[" << simulation_cycle() << "] " << " "
161	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._miss_prediction << " "
162	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._ifetch_prediction << " "
163	<< "(" << toString(reg_UPDATE_PREDICTION_TABLE [i][bottom]._condition) << ")"
164	<< std::endl;
165	}
166	#endif
167
168	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom);
169	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
170	// Free slot
171	reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
172
173	// Update pointer
174	reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
175
176	// Free a slot, test if bottom pointer overtake the top pointer
177	if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i])
178	reg_UPT_EMPTY [i] = true; // free a slot
179
180	reg_EVENT_UPT_FULL [i] = false;
181	}
182
183	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (after ) : %d",reg_UPT_BOTTOM [i]);
184	}
185	}
186	}
187
188	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)");
189
190	// ===================================================================
191	// =====[ PREDICT ]===================================================
192	// ===================================================================
193
194	// An ifetch_unit compute next cycle and have an branch : predict_val is set
195	// * Alloc new entry -> new status is "wait decod"
196	// * Save input (to restore in miss or error)
197	// * Update pointer
198
199	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
200	// Test if have a transaction
201	if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i])
202	{
203	// get transaction information
204	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
205	uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i];
206	Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
207	bool is_accurate = (_param->_always_accurate_predict or
208	(_param->_can_accurate_predict and PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i])));
209
210
211	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i);
212	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
213	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
214	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %d",condition);
215	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is_accurate : %d",is_accurate);
216
217	#ifdef DEBUG_TEST
218	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
219	throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state."));
220	#endif
221
222	// Ifetch unit have fetch an instruction bundle with a branchement.
223	// Insert in UFPT
224	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top);
225	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD;
226
227	// Write information
228	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition;
229	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]);
230	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
231	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]);
232	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = is_accurate;
233	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0;
234	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]);
235	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]);
236
237	// Update pointer
238	reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context];
239
240	// Test if this branchement need update
241	if (need_update(condition))
242	{
243	reg_UFPT_NB_NEED_UPDATE [context] ++;
244	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
245	}
246	}
247
248	// ===================================================================
249	// =====[ DECOD ]=====================================================
250	// ===================================================================
251
252
253	// An decod is detected by decod stage
254	// 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch
255	// * Update state, wait_decod -> wait_end
256	// * Pop ufpt -> push upt
257	// * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod
258	// 2) Miss : The instruction bundle have a branch but it is not predicted
259	// * Flush ufpt
260	// * decod information is write in upt
261
262	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
263	// Test if have a decod transaction
264	if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i])
265	{
266	// Read information
267	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
268	Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]);
269	Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]);
270	uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i];
271	uint32_t top_next = (upt_ptr_write+1)%_param->_size_upt_queue [context];
272	Tbranch_condition_t condition ;
273	Tcontrol_t is_accurate;
274	Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]);
275	Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
276	Tcontrol_t direction = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]);
277
278	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i);
279	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
280	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch);
281	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod);
282	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write);
283
284	// In decod step, two miss type :
285	// miss_ifetch = branch is previously predict (predict interface), but it's not the good
286	// miss_decod = branch was not detected
287	if (not (miss_ifetch or miss_decod))
288	{
289	// Normal case : branch is previous predicted, change state of branch
290
291	// Read ufpt_ptr (send in predic step)
292	uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
293
294	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read);
295
296	#ifdef DEBUG_TEST
297	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
298	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
299	#endif
300	// Change state
301	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
302	reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
303
304	// Push upt (from Pop ufpt)
305	condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
306	is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
307
308	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
309	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
310	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
311	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ;
312	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
313	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
314	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ;
315	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
316	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ;
317	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch
318
319	// Update pointer (now, this instruction is not in ufpt)
320	if (need_update(condition))
321	{
322	reg_UFPT_NB_NEED_UPDATE [context] --;
323	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
324	}
325	}
326	else
327	{
328	// Have a miss !!!
329	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss !!!");
330
331	condition = PORT_READ(in_DECOD_BTB_CONDITION [i]);
332	is_accurate = (_param->_always_accurate_decod or
333	(_param->_can_accurate_decod and PORT_READ(in_DECOD_IS_ACCURATE [i])));
334
335	// if can_continue, don't wait the end of all instruction
336	// (can_continue = not miss_commit and the destination is accurate (know))
337	Tcontrol_t can_continue = is_accurate;
338
339	#ifdef DEBUG_TEST
340	if (reg_UPT_EVENT_STATE [context] != UPT_EVENT_STATE_OK)
341	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt event state."));
342	if (reg_UFPT_EVENT_STATE [context] != UFPT_EVENT_STATE_OK)
343	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt event state."));
344	#endif
345
346	// miss_ifetch -> need flush ufpt
347	// miss_decod -> not necessary
348	// if can_continue (destination is know) and direction is not take (instruction in ifetch_queue can be valid)
349	bool flush_ufpt = (not (can_continue and not direction and not miss_ifetch));
350
351	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * can_continue: %d",can_continue);
352	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * direction : %d",direction );
353	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch );
354	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flush_ufpt: %d",flush_ufpt );
355
356	// Test if can continue without flushing the ufpt (and ifetch_queue)
357	if (flush_ufpt)
358	{
359	// // Optimisation : Test if ufpt have entry that need update prediction struction (as Return Address Stack)
360	// if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
361	// {
362	// // Change state
363	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
364	// reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT;
365
366	// // @@@
367	// // // Have an actual event ?
368	// // if (not reg_EVENT_VAL [context])
369	// // reg_EVENT_UPT_PTR [context] = upt_ptr_write;
370	// }
371	// else
372	// {
373	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- UPT_EVENT_STATE_KO_MISS_WAIT_UFPT (decod - miss - flush ufpt)",context);
374	// // just wait ufpt, don't flush upt
375	// reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_MISS_WAIT_UFPT;
376	// }
377
378	reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT;
379	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT_STATE [%d] <- %s (decod, miss)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
380
381	// Need Flush UPFT
382	flush_UFPT [context] = true;
383
384	// Write information
385	// reg_EVENT_IS_BRANCH [context] = true;
386	reg_EVENT_DEPTH [context] = upt_ptr_write;
387	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
388	reg_EVENT_ADDRESS_DEST_VAL[context] = direction;
389	reg_EVENT_ADDRESS_DEST [context] = address_dest;
390	reg_EVENT_CAN_CONTINUE [context] = can_continue;
391	}
392	// else can continue
393
394	// Push upt (from decod interface)
395	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
396	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ;
397	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest;
398	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = direction ;
399	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
400	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
401	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction
402	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]);
403	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]);
404	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction
405	}
406
407	// In all case !!!
408	#ifdef DEBUG_TEST
409	if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY)
410	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state."));
411	#endif
412
413	// Change state
414	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write);
415	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END;
416	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._retire_ok = false;
417	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._miss_commit = false;
418
419	// Write new accurate
420	#ifdef DEBUG_TEST
421	if (not reg_IS_ACCURATE [context] and not is_accurate)
422	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag."));
423	#endif
424
425	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is_accurate : %d",is_accurate);
426
427	reg_IS_ACCURATE [context] = is_accurate;
428
429	// Update pointer
430	reg_UPT_TOP [context] = top_next;
431	reg_UPT_EMPTY [context] = false; // new instruction
432	}
433
434	// ===================================================================
435	// =====[ UPDATE ]====================================================
436	// ===================================================================
437	{
438	bool can_continue [_param->_nb_context];
439	for (uint32_t i=0; i<_param->_nb_context; ++i)
440	can_continue [i] = true;
441
442	// For each updated instruction
443	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
444	{
445	Tcontext_t context = internal_UPDATE_CONTEXT_ID [i];
446
447	// Test if transaction
448	// (an val_with_out is an update and don't need update prediction structure
449	if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or
450	(internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context]))
451	{
452	Tdepth_t depth = internal_UPDATE_DEPTH [i];
453
454	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i);
455	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
456	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
457
458	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [context];
459
460	// One interface to two source :
461	// * from ufpt -> newest prediction
462	// * from upt -> oldest prediction
463	if (internal_UPDATE_FROM_UFPT [i])
464	{
465	// if free a slot, also all queue is updated
466	// Last slot ?
467	if ((--reg_UFPT_NB_UPDATE [context])==0)
468	{
469	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT_EVENT [%d] <- UFPT_EVENT_STATE_OK (update - end flush ufpt)",context);
470	reg_UFPT_EVENT_STATE [context] = UFPT_EVENT_STATE_OK;
471	reg_UFPT_NB_NEED_UPDATE [context] = 0;
472
473	// // Test upt event to change state
474	// // test if upt wait ufpt
475	// switch (upt_event_state)
476	// {
477	// // this case when don't need flush upt (miss decod and can continue)
478	// case UPT_EVENT_STATE_KO_MISS_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
479	// case UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_OK ; break;
480	// default : break;
481	// }
482
483	// reg_UPT_EVENT_STATE [context] = upt_event_state;
484	}
485
486	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table");
487
488	// Change state
489	#ifdef DEBUG_TEST
490	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT)
491	throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state."));
492	#endif
493
494	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth);
495
496	reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END;
497
498	// Update pointer
499	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]);
500	reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
501	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]);
502	}
503	else
504	{
505	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table");
506	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (before) : %d",reg_UPT_UPDATE [context]);
507	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(upt_event_state).c_str());
508
509	// Change state
510	#ifdef DEBUG_TEST
511	if (internal_UPDATE_RAS [i])
512	{
513	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and
514	(reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) )
515	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
516	}
517	else
518	{
519	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK )
520	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
521	}
522	#endif
523
524	#ifdef STATISTICS
525	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
526	#endif
527	bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK);
528	bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
529
530	// Test if branch is valid (prediction can be incorrect)
531	if (ok or ko)
532	{
533	reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true;
534	reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_prediction = ko;
535
536	#ifdef STATISTICS
537	if (usage_is_set(_usage,USE_STATISTICS))
538	{
539	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._ifetch_prediction)
540	(*_stat_nb_branch_ifetch_prediction [context])++;
541	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate)
542	(*_stat_nb_branch_accurate [context])++;
543	}
544	#endif
545	}
546
547	// Have an update, test the state to transiste to the good state
548	if (ko)
549	{
550	// Ko
551	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth);
552
553	// Wait update of context_state
554	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
555
556	reg_EVENT_UPT_PTR [context] = depth;
557
558	#ifdef STATISTICS
559	if (usage_is_set(_usage,USE_STATISTICS))
560	(*_stat_nb_branch_miss [context][condition])++;
561	#endif
562	}
563	else
564	{
565	// ok or event
566
567	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth);
568	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END;
569
570	#ifdef STATISTICS
571	if (usage_is_set(_usage,USE_STATISTICS))
572	{
573	if (ok)
574	(*_stat_nb_branch_hit [context][condition]) ++;
575	else
576	(*_stat_nb_branch_unused [context]) ++;
577	}
578	#endif
579	}
580
581	// Test if freeing the branch with no accurate ?
582	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko)
583	reg_IS_ACCURATE [context] = true;
584
585	// Update pointer
586	// * if update RAS : update pointer is decreaste until it equal at top pointer
587	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * internal_UPDATE_RAS [%d] : %d",i,internal_UPDATE_RAS [i]);
588
589	if (internal_UPDATE_RAS [i])
590	{
591	// if end_event, restart too bottom, else decrease pointer
592	bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]);
593
594	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * end_event : %d",end_event);
595	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",reg_UPT_BOTTOM[context]);
596
597	if (end_event)
598	{
599	reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);
600	// reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context];
601
602	switch (upt_event_state)
603	{
604	// this case when don't need flush upt (miss decod and can continue)
605	case UPT_EVENT_STATE_KO_MISS_FLUSH_UPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
606	case UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT :
607	{
608	upt_event_state = UPT_EVENT_STATE_OK;
609	reg_UPT_TOP [context] = reg_UPT_TOP_EVENT [context];
610	reg_UPT_UPDATE [context] = reg_UPT_TOP_EVENT [context];
611
612	break;
613	}
614	default : break;
615	}
616
617	}
618	else
619	{
620	// else, decrease update pointer
621	reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1);
622	}
623	}
624	else
625	{
626	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * next update");
627
628	// increase pointer
629	reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
630	}
631
632	// special case :
633	if ((upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE) and
634	(reg_UPT_UPDATE [context] == reg_EVENT_UPT_PTR [context]))
635	{
636	reg_UPT_TOP [context] = reg_UPT_TOP_EVENT [context];
637	reg_UPT_UPDATE [context] = reg_UPT_TOP_EVENT [context];
638	reg_IS_ACCURATE [context] = true;
639
640	upt_event_state = UPT_EVENT_STATE_OK;
641	}
642
643	reg_UPT_EVENT_STATE [context] = upt_event_state;
644
645	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (after ) : %d",reg_UPT_UPDATE[context]);
646	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(reg_UPT_EVENT_STATE [context]).c_str());
647	}
648	}
649	else
650	can_continue [context] = false;
651	}
652
653	// Round robin
654	reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context;
655	}
656
657	// ===================================================================
658	// =====[ BRANCH_COMPLETE ]===========================================
659	// ===================================================================
660
661	// The branch is complete
662	// * Hit prediction :
663	// * update status
664	// * Miss prediction :
665	{
666	bool branch_complete_miss [_param->_nb_context];
667	for (uint32_t i=0; i<_param->_nb_context; ++i)
668	branch_complete_miss [i] = false;
669
670	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
671	if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
672	{
673	// Read information
674	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
675	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
676	Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
677	Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i];
678	Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];
679
680	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [context];
681
682	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);
683	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
684	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
685	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);
686	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(upt_event_state).c_str());
687
688	// Test if the completed branch is a speculation miss
689	if (miss)
690	{
691	// special case : two branch complete on the same context.
692	// when the re order keep the order, the branch complete j is most speculative that the branch comple i if i < j
693	if (not branch_complete_miss [context])
694	{
695	branch_complete_miss [context] = true;
696	// Flush UPT
697	// get information
698	uint32_t top = reg_UPT_TOP [context];
699	uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;
700
701	Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
702	upt_state_t top_state = reg_UPDATE_PREDICTION_TABLE [context][top]._state;
703
704	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_event_state : %s",toString(upt_event_state).c_str());
705	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top_state : %s",toString(top_state).c_str());
706
707	bool previous_ufpt_event = (reg_UFPT_EVENT_STATE [context] == UFPT_EVENT_STATE_KO_FLUSH);
708
709
710	bool previous_upt_event = (false
711	or (upt_event_state == UPT_EVENT_STATE_KO_MISS_WAIT_UFPT )
712	or (upt_event_state == UPT_EVENT_STATE_KO_MISS_FLUSH_UPT )
713	or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT)
714	or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT)
715	or (upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE)
716	or (top_state == UPDATE_PREDICTION_STATE_END_KO )
717	or (top_state == UPDATE_PREDICTION_STATE_KO )
718	);
719
720	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
721	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
722	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_upt_event : %d",previous_upt_event);
723	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_ufpt_event : %d",previous_ufpt_event);
724	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [context]);
725
726	// Have a miss !!!
727	// Flush UPFT
728	flush_UFPT [context] \|= not previous_ufpt_event;
729
730	// Test if the entry wait the branchment (else, they have a previous event)
731	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
732	{
733	// All instruction between the instruction and the top is disable
734	for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
735	j!=top;
736	j=(j+1)%_param->_size_upt_queue[context])
737	{
738	reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
739	reg_UPDATE_PREDICTION_TABLE [context][j]._retire_ok = false; // event
740	}
741
742	// New top
743	reg_UPT_TOP [context] = depth;
744
745	if (not previous_upt_event)
746	{
747	reg_UPT_TOP_EVENT [context] = top;
748	reg_UPT_UPDATE [context] = new_update;
749	}
750	else
751	{
752	// Have event. Top index this slot
753	reg_UPDATE_PREDICTION_TABLE [context][top]._retire_ok = false;
754
755	switch (top_state)
756	{
757	case UPDATE_PREDICTION_STATE_END_KO :
758	case UPDATE_PREDICTION_STATE_END :
759	{
760	// Have already update predictor
761	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END;
762	reg_UPT_UPDATE [context] = new_update;
763	break;
764	}
765	case UPDATE_PREDICTION_STATE_KO :
766	{
767	// Doesn't have update predictor
768	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
769	break;
770	}
771	default :
772	{
773	// reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
774	// break;
775
776	#ifdef DEBUG_TEST
777	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
778	#endif
779	}
780	}
781	}
782
783	if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
784	reg_UPT_EMPTY [context] = true;
785
786	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
787	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
788
789	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE [%d] : %d",context,reg_UFPT_NB_NEED_UPDATE [context]);
790
791	// if ( (reg_UFPT_NB_NEED_UPDATE [context] > 0) or
792	// (reg_UFPT_NB_UPDATE [context] > 0))
793	// {
794	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
795	// reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
796	// }
797	// else
798	// {
799	// // if (not previous_update_ras)
800	// {
801	// // have ras prediction ?
802	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
803
804	// reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
805
806	// }
807	// }
808
809	reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_MISS_FLUSH_UPT;
810	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT_STATE [%d] <- %s (branch_complete, ifetch hit)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
811
812	// reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT;
813
814	// else no update
815
816	// reg_EVENT_IS_BRANCH [context] = true;
817	reg_EVENT_DEPTH [context] = depth;
818	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
819	reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
820	reg_EVENT_ADDRESS_DEST [context] = good_addr;
821	reg_EVENT_CAN_CONTINUE [context] = true;
822	// reg_EVENT_CAN_CONTINUE [context] = false;
823	}
824
825	reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_commit = true;
826	}
827	}
828	else
829	{
830	// Hit case
831
832	// #ifdef DEBUG_TEST
833	// if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
834	// throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
835	// #endif
836
837	// In same cycle, can have a previous branch_complete
838	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
839	{
840	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
841	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
842	}
843	}
844
845	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(reg_UPT_EVENT_STATE [context]).c_str());
846
847	// In all case : update good_take
848	reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;
849
850	// Write address_dest if need read register
851	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
852
853	if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
854	(condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or
855	(condition == BRANCH_CONDITION_READ_STACK ) )
856	reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
857	}
858	}
859
860	// ===================================================================
861	// =====[ BRANCH_EVENT ]==============================================
862	// ===================================================================
863	for (uint32_t i=0; i<_param->_nb_context; i++)
864	if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
865	{
866	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i);
867
868	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
869
870	switch (upt_event_state)
871	{
872	case UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT : upt_event_state = UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT; break;
873	case UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT; break;
874	default : break; // an other branch is occured
875	}
876
877	reg_UPT_EVENT_STATE [i] = upt_event_state;
878	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s (branch_event)",toString(upt_event_state).c_str());
879	}
880
881	// ===================================================================
882	// =====[ EVENT ]=====================================================
883	// ===================================================================
884	for (uint32_t i=0; i<_param->_nb_context; ++i)
885	if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i])
886	{
887	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT");
888
889	//----------------------------------------------------------------
890	// Cases
891	//----------------------------------------------------------------
892	// * EVENT_TYPE_NONE - nothing
893	// * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer
894	// * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer
895	// * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update
896	// * EVENT_TYPE_SPR_ACCESS - nothing
897	// * EVENT_TYPE_MSYNC - nothing
898	// * EVENT_TYPE_PSYNC - nothing
899	// * EVENT_TYPE_CSYNC - nothing
900
901	Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]);
902	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
903
904	// Test if end of miss -> all previous branch is complete
905	// -> all next branch is finish
906
907	switch (event_type)
908	{
909	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
910	{
911	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_BRANCH_MISS_SPECULATION");
912
913	switch (upt_event_state)
914	{
915	case UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT :
916	{
917	Tdepth_t depth = reg_EVENT_UPT_PTR [i];
918	Tdepth_t update = reg_UPT_UPDATE [i];
919
920	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
921
922	if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO)
923	{
924	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth);
925
926	reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END;
927	}
928
929	// Special case : branch_complete a speculative branch and the context_state signal the end of this event before the complete of previous branch
930	if (depth != update)
931	{
932	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_COMMIT_WAIT_END_UPDATE (event)",i);
933	upt_event_state = UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE;
934
935	break; // stop here
936	}
937
938	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
939	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
940
941	// break; continue
942	}
943	case UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT :
944	{
945	// Change state
946	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i);
947
948	upt_event_state = UPT_EVENT_STATE_OK;
949	reg_IS_ACCURATE [i] = true;
950
951	break;
952	}
953	default : break; // an other branch is occured
954	}
955
956	break;
957	}
958	case EVENT_TYPE_LOAD_MISS_SPECULATION :
959	case EVENT_TYPE_EXCEPTION :
960	{
961	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_LOAD_MISS_SPECULATION");
962
963	// Have a miss !!!
964	// Flush UPFT
965	flush_UFPT [i] = true;
966
967	if (upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE)
968	{
969	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
970	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
971	reg_IS_ACCURATE [i] = true;
972
973	upt_event_state = UPT_EVENT_STATE_OK;
974	}
975
976	// Flush UPT
977	uint32_t bottom = reg_UPT_BOTTOM [i];
978
979	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom);
980
981	// event_state_t event_state = reg_EVENT_STATE [i];
982	// bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
983	// (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or
984	// (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
985	// (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
986
987	bool find = false; // have slot to update ???
988	bool find_top = false;
989	Tdepth_t top = bottom;
990	Tdepth_t update = bottom;
991	bool empty = reg_UPT_EMPTY [i];
992
993	// flush all slot, because this event is in head of rob
994	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
995	{
996	Tdepth_t x = (bottom+j)%_param->_size_upt_queue[i];
997
998	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d] : %s",x,toString(reg_UPDATE_PREDICTION_TABLE [i][x]._state).c_str());
999
1000	if ((reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_END) and
1001	(reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY))
1002	{
1003	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find at UPT[%d]",x);
1004
1005	find = true; // find a not empty slot
1006	reg_UPDATE_PREDICTION_TABLE [i][x]._state = UPDATE_PREDICTION_STATE_EVENT;
1007	reg_UPDATE_PREDICTION_TABLE [i][x]._retire_ok = false;
1008	update = x;
1009	}
1010
1011	if (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY)
1012	if (not find_top)
1013	{
1014	top = x;
1015	find_top = true;
1016	}
1017	}
1018
1019	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find);
1020	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
1021	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update : %d",update);
1022
1023	// Test if have update slot
1024	reg_UPT_TOP_EVENT [i] = reg_UPT_TOP[i];
1025	if (find)
1026	{
1027	// TODO : special case : event is an exception on branch, also depth is not valid
1028	reg_UPT_TOP [i] = top; // depth is again valid
1029
1030	if (bottom == reg_UPT_TOP [i])
1031	reg_UPT_EMPTY [i] = true;
1032
1033	reg_UPT_UPDATE [i] = update;
1034	}
1035
1036	// new state :
1037	// * test if ufpt is empty
1038	// * ok : flush upft and upt
1039	// * ko : test if have previous flush upt
1040	// * ok : nothing
1041	// * ko : flush upt
1042	// reg_EVENT_VAL [i] = find;
1043	// reg_EVENT_IS_BRANCH [i] = false;
1044	// reg_EVENT_UPT_PTR [i] = ((top==0)?_param->_size_upt_queue[i]:top)-1; ///// ZE MODIF
1045	reg_EVENT_UPT_PTR [i] = top;
1046	reg_EVENT_UPT_FULL [i] = (not empty and (bottom == reg_UPT_TOP [i]));
1047	// reg_EVENT_DEPTH [i] = PORT_READ(in_EVENT_DEPTH [i]);//(top+1)%_param->_size_upt_queue[i];
1048	reg_EVENT_DEPTH [i] = top;
1049
1050	// reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State
1051	// reg_EVENT_ADDRESS_DEST_VAL[i] = good_take;
1052	// reg_EVENT_ADDRESS_DEST [i] = good_addr;
1053
1054	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
1055	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
1056	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
1057
1058	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]);
1059	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]);
1060	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL [i]);
1061	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1062	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
1063
1064	if (find)
1065	{
1066	// have ras prediction ?
1067	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT (event - find)",i);
1068
1069	upt_event_state = UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT;
1070	}
1071	else
1072	{
1073	// special case : nothing
1074	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT (event - not find)",i);
1075
1076	// reg_EVENT_VAL [i] = false;
1077
1078	upt_event_state = UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT;
1079	}
1080
1081	break;
1082	}
1083	default :
1084	{
1085	// nothing
1086	break;
1087	}
1088	}
1089
1090	reg_UPT_EVENT_STATE [i] = upt_event_state;
1091	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s (branch_event)",toString(upt_event_state).c_str());
1092	}
1093
1094	// ===================================================================
1095	// =====[ FLUSH ]=====================================================
1096	// ===================================================================
1097
1098	for (uint32_t i=0; i<_param->_nb_context; ++i)
1099	{
1100	if (flush_UFPT [i])
1101	{
1102	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table");
1103	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i);
1104	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1105
1106	// It's to accelerate miss speculation -> associative access
1107	if (reg_UFPT_NB_NEED_UPDATE [i] == 0)
1108	{
1109	// No entry need prediction, flush all entry -> Reset
1110	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
1111	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
1112	reg_UFPT_BOTTOM [i] = 0;
1113	reg_UFPT_TOP [i] = 0;
1114	}
1115	else
1116	{
1117	uint32_t bottom = reg_UFPT_BOTTOM [i];
1118	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
1119	{
1120	uint32_t index = (bottom+j)%_param->_size_ufpt_queue[i];
1121	// EMPTY : no event
1122	// END : already update
1123	// EVENT : previous event
1124	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
1125	{
1126	reg_UFPT_UPDATE [i] = index;
1127	reg_UFPT_NB_UPDATE [i] ++;
1128	reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
1129	}
1130	}
1131
1132	// Change state
1133	reg_UFPT_EVENT_STATE [i] = UFPT_EVENT_STATE_KO_FLUSH;
1134	}
1135
1136	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]);
1137
1138	}
1139
1140	// Change state on UPT
1141	{
1142	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
1143	ufpt_event_state_t ufpt_event_state = reg_UFPT_EVENT_STATE [i];
1144
1145	// Test upt event to change state
1146	// test if upt wait ufpt
1147	if (ufpt_event_state == UFPT_EVENT_STATE_OK)
1148	switch (upt_event_state)
1149	{
1150	// this case when don't need flush upt (miss decod and can continue)
1151	case UPT_EVENT_STATE_KO_MISS_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
1152	case UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_OK ; break;
1153	default : break;
1154	}
1155
1156	reg_UPT_EVENT_STATE [i] = upt_event_state;
1157	}
1158	}
1159
1160	#ifdef STATISTICS
1161	if (usage_is_set(_usage,USE_STATISTICS))
1162	for (uint32_t i=0; i<_param->_nb_context; i++)
1163	{
1164	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
1165	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
1166	(*_stat_ufpt_queue_nb_elt [i]) ++;
1167	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
1168	if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)
1169	(*_stat_upt_queue_nb_elt [i]) ++;
1170	}
1171	#endif
1172
1173	// ===================================================================
1174	// =====[ PRINT ]=====================================================
1175	// ===================================================================
1176
1177	#if (DEBUG >= DEBUG_TRACE)
1178	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table");
1179	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY);
1180	for (uint32_t i=0; i<_param->_nb_context; i++)
1181	{
1182	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]);
1183	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UFPT_STATE : %s" ,toString(reg_UFPT_EVENT_STATE [i]).c_str());
1184	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_STATE : %s" ,toString(reg_UPT_EVENT_STATE [i]).c_str());
1185	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]);
1186	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]);
1187	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d" ,reg_EVENT_UPT_FULL [i]);
1188	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_IS_BRANCH : %d" ,reg_EVENT_IS_BRANCH [i]);
1189	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
1190	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2);
1191	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]);
1192	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST [i],reg_EVENT_ADDRESS_DEST [i]<<2);
1193	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_CAN_CONTINUE : %d" ,reg_EVENT_CAN_CONTINUE [i]);
1194
1195	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump UFPT [%d] (Update_Fetch_Prediction_Table)",i);
1196	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]);
1197	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]);
1198	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]);
1199	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1200	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
1201	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
1202	{
1203	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d, %.8lld %.8x (%.8x) %.4d - %s",
1204	j,
1205	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition,
1206	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src,
1207	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src<<2,
1208	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest,
1209	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest<<2,
1210	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take,
1211	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate,
1212	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history,
1213	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras,
1214	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras<<2,
1215	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras,
1216	toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str()
1217	);
1218	}
1219
1220	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump UPT [%d] (Update_Prediction_Table)",i);
1221	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
1222	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
1223	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]);
1224	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
1225	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
1226	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
1227	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d %.1d, %.8lld %.8x (%.8x) %.4d - %s",
1228	j,
1229	reg_UPDATE_PREDICTION_TABLE [i][j]._condition,
1230	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src,
1231	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src<<2,
1232	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest,
1233	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest<<2,
1234	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take,
1235	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take,
1236	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate,
1237	reg_UPDATE_PREDICTION_TABLE [i][j]._history,
1238	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras,
1239	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras<<2,
1240	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras,
1241	toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str()
1242	);
1243	}
1244	#endif
1245
1246	#ifdef DEBUG_TEST
1247	for (uint32_t i=0; i<_param->_nb_context; i++)
1248	{
1249	if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i])
1250	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i]));
1251	if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i])
1252	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i]));
1253	}
1254	#endif
1255
1256	}
1257
1258
1259	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
1260	end_cycle ();
1261	#endif
1262
1263	log_end(Update_Prediction_Table,FUNCTION);
1264	};
1265
1266	}; // end namespace update_prediction_table
1267	}; // end namespace prediction_unit
1268	}; // end namespace front_end
1269	}; // end namespace multi_front_end
1270	}; // end namespace core
1271
1272	}; // end namespace behavioural
1273	}; // end namespace morpheo
1274	#endif

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