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Update_Prediction_Table_transition.cpp @ 146

Last change on this file since 146 was 146, checked in by rosiere, 13 years ago
1) Integration of RegisterFile_Internal_Banked in RegisterFile? 2) Erase "read_write" interface in RegisterFile_Monolithic component 3) Add smith predictor parameters in Load_store_pointer_unit. 4) Fix not statistics flags
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File size: 72.9 KB

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1	#ifdef SYSTEMC
2	/*
3	* $Id: Update_Prediction_Table_transition.cpp 146 2011-02-01 20:57:54Z rosiere $
4	*
5	* [ Description ]
6	*
7	*/
8
9	#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/include/Update_Prediction_Table.h"
10
11	namespace morpheo {
12	namespace behavioural {
13	namespace core {
14	namespace multi_front_end {
15	namespace front_end {
16	namespace prediction_unit {
17	namespace update_prediction_table {
18
19	#undef FUNCTION
20	#define FUNCTION "Update_Prediction_Table::transition"
21	void Update_Prediction_Table::transition (void)
22	{
23	log_begin(Update_Prediction_Table,FUNCTION);
24	log_function(Update_Prediction_Table,FUNCTION,_name.c_str());
25
26	if (PORT_READ(in_NRESET) == 0)
27	{
28	// Initialisation
29
30	reg_UPDATE_PRIORITY = 0;
31
32	// All pointer is set at 0
33	for (uint32_t i=0; i<_param->_nb_context; i++)
34	{
35	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
36	{
37	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
38	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition = 0; // not necessary
39	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src = 0; // not necessary
40	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest = 0; // not necessary
41	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take = 0; // not necessary
42	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate = 0; // not necessary
43	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history = 0; // not necessary
44	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras = 0; // not necessary
45	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras = 0; // not necessary
46	}
47	reg_UFPT_BOTTOM [i] = 0;
48	reg_UFPT_TOP [i] = 0;
49	reg_UFPT_UPDATE [i] = 0;
50	reg_UFPT_NB_NEED_UPDATE [i] = 0;
51	reg_UFPT_NB_UPDATE [i] = 0;
52
53	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
54	{
55	reg_UPDATE_PREDICTION_TABLE [i][j]._state = UPDATE_PREDICTION_STATE_EMPTY;
56	reg_UPDATE_PREDICTION_TABLE [i][j]._condition = 0; // not necessary
57	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src = 0; // not necessary
58	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest = 0; // not necessary
59	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take = 0; // not necessary
60	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take = 0; // not necessary
61	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate = 0; // not necessary
62	reg_UPDATE_PREDICTION_TABLE [i][j]._history = 0; // not necessary
63	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras = 0; // not necessary
64	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras = 0; // not necessary
65	reg_UPDATE_PREDICTION_TABLE [i][j]._ifetch_prediction= 0; // not necessary
66	reg_UPDATE_PREDICTION_TABLE [i][j]._miss_commit = 0; // not necessary
67	reg_UPDATE_PREDICTION_TABLE [i][j]._retire_ok = 0; // not necessary
68	reg_UPDATE_PREDICTION_TABLE [i][j]._miss_prediction = 0; // not necessary
69	}
70	reg_UPT_BOTTOM [i] = 0;
71	reg_UPT_TOP [i] = 0;
72	reg_UPT_TOP_EVENT [i] = 0;
73	reg_UPT_UPDATE [i] = 0;
74	reg_UPT_EMPTY [i] = true;
75
76	reg_IS_ACCURATE [i] = true;
77
78	reg_UFPT_EVENT_STATE [i] = UFPT_EVENT_STATE_OK;
79	reg_UPT_EVENT_STATE [i] = UPT_EVENT_STATE_OK;
80
81	reg_EVENT_UPT_PTR [i] = 0; // not necessary
82	reg_EVENT_UPT_FULL [i] = 0; // not necessary
83
84	// reg_EVENT_STATE [i] = EVENT_STATE_OK; // not necessary
85	// reg_EVENT_IS_BRANCH [i] = true ; // not necessary
86
87	reg_EVENT_DEPTH [i] = 0; // not necessary
88	reg_EVENT_ADDRESS_SRC [i] = 0; // not necessary
89	reg_EVENT_ADDRESS_DEST_VAL [i] = 0; // not necessary
90	reg_EVENT_ADDRESS_DEST [i] = 0; // not necessary
91	reg_EVENT_CAN_CONTINUE [i] = 0; // not necessary
92	}
93	}
94	else
95	{
96	bool flush_UFPT [_param->_nb_context];
97	for (uint32_t i=0; i<_param->_nb_context; i++)
98	{
99	flush_UFPT [i] = false;
100	}
101
102	// ===================================================================
103	// =====[ GARBAGE COLLECTOR ]=========================================
104	// ===================================================================
105
106	// Each cycle, if the most lastest branch have update all prediction struction (state = end), free this slot
107	// * Update state -> new status is "empty"
108	// * Update pointer (bottom and accurate)
109	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (BEGIN)");
110	for (uint32_t i=0; i<_param->_nb_context; i++)
111	{
112	// -----------------------------
113	// UPDATE_FETCH_PREDICTION_TABLE
114	// -----------------------------
115	{
116	uint32_t bottom = reg_UFPT_BOTTOM [i];
117	bool end = (reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state == UPDATE_FETCH_PREDICTION_STATE_END);
118
119	// Test if bottom slot can be remove
120	if (end)
121	{
122	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d]",i,bottom);
123	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state = UPDATE_FETCH_PREDICTION_STATE_EMPTY",i,bottom);
124
125	// Free slot
126	reg_UPDATE_FETCH_PREDICTION_TABLE [i][bottom]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
127	// Update pointer
128	bottom = (bottom+1)%_param->_size_ufpt_queue[i];
129
130	reg_UFPT_BOTTOM [i] = bottom;
131	}
132	}
133
134	// -----------------------
135	// UPDATE_PREDICTION_TABLE
136	// -----------------------
137	{
138	uint32_t bottom = reg_UPT_BOTTOM [i];
139
140	// if (reg_UPT_EVENT_STATE [i] == UPT_EVENT_STATE_OK)
141	{
142	bool end = (reg_UPDATE_PREDICTION_TABLE [i][bottom]._state == UPDATE_PREDICTION_STATE_END);
143
144	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (before) : %d",bottom);
145	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * state is STATE_END : %d",end);
146
147	if (end)
148	{
149	#if defined(DEBUG) and defined(DEBUG_Update_Prediction_Table) and (DEBUG_Update_Prediction_Table == true)
150	if (log_file_generate)
151	if (reg_UPDATE_PREDICTION_TABLE [i][bottom]._retire_ok)
152	{
153	uint32_t num_thread = _param->_translate_num_context_to_num_thread [i];
154	branchement_log_file [num_thread]
155	<< std::hex
156	<< "0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_src << " "
157	<< "0x" << std::setfill('0') << std::setw(_param->_size_general_data/4) << reg_UPDATE_PREDICTION_TABLE [i][bottom]._address_dest << " "
158	<< std::dec
159	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._good_take << " - "
160	<< "[" << simulation_cycle() << "] " << " "
161	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._miss_prediction << " "
162	<< reg_UPDATE_PREDICTION_TABLE [i][bottom]._ifetch_prediction << " "
163	<< "(" << toString(reg_UPDATE_PREDICTION_TABLE [i][bottom]._condition) << ")"
164	<< std::endl;
165	}
166	#endif
167
168	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]",i,bottom);
169	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d]._state = UPDATE_PREDICTION_STATE_EMPTY",i,bottom);
170	// Free slot
171	reg_UPDATE_PREDICTION_TABLE [i][bottom]._state = UPDATE_PREDICTION_STATE_EMPTY;
172
173	// Update pointer
174	reg_UPT_BOTTOM [i] = (bottom+1)%_param->_size_upt_queue[i];
175
176	// Free a slot, test if bottom pointer overtake the top pointer
177	if (reg_UPT_BOTTOM [i] == reg_UPT_TOP [i])
178	reg_UPT_EMPTY [i] = true; // free a slot
179
180	reg_EVENT_UPT_FULL [i] = false;
181	}
182
183	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM (after ) : %d",reg_UPT_BOTTOM [i]);
184	}
185	}
186	}
187
188	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * GARBAGE COLLECTOR (END)");
189
190	// ===================================================================
191	// =====[ PREDICT ]===================================================
192	// ===================================================================
193
194	// An ifetch_unit compute next cycle and have an branch : predict_val is set
195	// * Alloc new entry -> new status is "wait decod"
196	// * Save input (to restore in miss or error)
197	// * Update pointer
198
199	for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
200	// Test if have a transaction
201	if (PORT_READ(in_PREDICT_VAL[i]) and internal_PREDICT_ACK [i])
202	{
203	// get transaction information
204	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_PREDICT_CONTEXT_ID [i]):0;
205	uint32_t top = internal_PREDICT_UPDATE_PREDICTION_ID [i];
206	Tbranch_condition_t condition = PORT_READ(in_PREDICT_BTB_CONDITION [i]);
207	bool is_accurate = (_param->_always_accurate_predict or
208	(_param->_can_accurate_predict and PORT_READ(in_PREDICT_BTB_IS_ACCURATE [i])));
209
210
211	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * PREDICT[%d] - Accepted",i);
212	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
213	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
214	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * condition : %d",condition);
215	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is_accurate : %d",is_accurate);
216
217	#ifdef DEBUG_TEST
218	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
219	throw ERRORMORPHEO(FUNCTION,_("Predict : invalid state."));
220	#endif
221
222	// Ifetch unit have fetch an instruction bundle with a branchement.
223	// Insert in UFPT
224	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD (predict)",context,top);
225	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._state = UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD;
226
227	// Write information
228	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._condition = condition;
229	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_src = PORT_READ(in_PREDICT_BTB_ADDRESS_SRC [i]);
230	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_dest = PORT_READ(in_PREDICT_BTB_ADDRESS_DEST [i]);
231	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._last_take = PORT_READ(in_PREDICT_BTB_LAST_TAKE [i]);
232	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._is_accurate = is_accurate;
233	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._history = (_param->_have_port_history)?PORT_READ(in_PREDICT_DIR_HISTORY [i]):0;
234	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._address_ras = PORT_READ(in_PREDICT_RAS_ADDRESS [i]);
235	reg_UPDATE_FETCH_PREDICTION_TABLE [context][top]._index_ras = PORT_READ(in_PREDICT_RAS_INDEX [i]);
236
237	// Update pointer
238	reg_UFPT_TOP [context] = (top+1)%_param->_size_ufpt_queue [context];
239
240	// Test if this branchement need update
241	if (need_update(condition))
242	{
243	reg_UFPT_NB_NEED_UPDATE [context] ++;
244	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
245	}
246	}
247
248	// ===================================================================
249	// =====[ DECOD ]=====================================================
250	// ===================================================================
251
252
253	// An decod is detected by decod stage
254	// 1) Hit prediction : The instruction bundle have a branch predicted in ifetch stage and it is this branch
255	// * Update state, wait_decod -> wait_end
256	// * Pop ufpt -> push upt
257	// * Update accurate register : if the predict stage have tagged this branch as not accurate, stop decod
258	// 2) Miss : The instruction bundle have a branch but it is not predicted
259	// * Flush ufpt
260	// * decod information is write in upt
261
262	for (uint32_t i=0; i<_param->_nb_inst_decod; i++)
263	// Test if have a decod transaction
264	if (PORT_READ(in_DECOD_VAL[i]) and internal_DECOD_ACK [i])
265	{
266	// Read information
267	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_DECOD_CONTEXT_ID [i]):0;
268	Tcontrol_t miss_ifetch = PORT_READ(in_DECOD_MISS_IFETCH [i]);
269	Tcontrol_t miss_decod = PORT_READ(in_DECOD_MISS_DECOD [i]);
270	uint32_t upt_ptr_write = internal_DECOD_UPT_PTR_WRITE [i];
271	uint32_t top_next = (upt_ptr_write+1)%_param->_size_upt_queue [context];
272	Tbranch_condition_t condition ;
273	Tcontrol_t is_accurate;
274	Taddress_t address_src = PORT_READ(in_DECOD_BTB_ADDRESS_SRC [i]);
275	Taddress_t address_dest = PORT_READ(in_DECOD_BTB_ADDRESS_DEST [i]);
276	Tcontrol_t direction = PORT_READ(in_DECOD_BTB_LAST_TAKE [i]);
277
278	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * DECOD[%d] - Accepted",i);
279	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
280	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch);
281	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_decod : %d",miss_decod);
282	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_ptr_write : %d",upt_ptr_write);
283
284	// In decod step, two miss type :
285	// miss_ifetch = branch is previously predict (predict interface), but it's not the good
286	// miss_decod = branch was not detected
287	if (not (miss_ifetch or miss_decod))
288	{
289	// Normal case : branch is previous predicted, change state of branch
290
291	// Read ufpt_ptr (send in predic step)
292	uint32_t ufpt_ptr_read = (_param->_have_port_depth)?PORT_READ(in_DECOD_UPDATE_PREDICTION_ID [i]):0;
293
294	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * ufpt_ptr_read : %d",ufpt_ptr_read);
295
296	#ifdef DEBUG_TEST
297	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state != UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
298	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt state."));
299	#endif
300	// Change state
301	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (decod - hit)",context,ufpt_ptr_read);
302	reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._state = UPDATE_FETCH_PREDICTION_STATE_END;
303
304	// Push upt (from Pop ufpt)
305	condition = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._condition;
306	is_accurate = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._is_accurate;
307
308	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
309	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_src ;
310	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_dest;
311	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._last_take ;
312	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
313	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
314	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._history ;
315	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._address_ras ;
316	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = reg_UPDATE_FETCH_PREDICTION_TABLE [context][ufpt_ptr_read]._index_ras ;
317	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = true ; // prediction from ifetch
318
319	// Update pointer (now, this instruction is not in ufpt)
320	if (need_update(condition))
321	{
322	reg_UFPT_NB_NEED_UPDATE [context] --;
323	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE (after) : %d",reg_UFPT_NB_NEED_UPDATE [context]);
324	}
325	}
326	else
327	{
328	// Have a miss !!!
329	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss !!!");
330
331	condition = PORT_READ(in_DECOD_BTB_CONDITION [i]);
332	is_accurate = (_param->_always_accurate_decod or
333	(_param->_can_accurate_decod and PORT_READ(in_DECOD_IS_ACCURATE [i])));
334
335	// if can_continue, don't wait the end of all instruction
336	// (can_continue = not miss_commit and the destination is accurate (know))
337	Tcontrol_t can_continue = is_accurate;
338
339	#ifdef DEBUG_TEST
340	if (reg_UPT_EVENT_STATE [context] != UPT_EVENT_STATE_OK)
341	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt event state."));
342	if (reg_UFPT_EVENT_STATE [context] != UFPT_EVENT_STATE_OK)
343	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid ufpt event state."));
344	#endif
345
346	// miss_ifetch -> need flush ufpt
347	// miss_decod -> not necessary
348	// if can_continue (destination is know) and direction is not take (instruction in ifetch_queue can be valid)
349	bool flush_ufpt = (not (can_continue and not direction and not miss_ifetch));
350
351	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * can_continue: %d",can_continue);
352	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * direction : %d",direction );
353	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss_ifetch : %d",miss_ifetch );
354	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * flush_ufpt: %d",flush_ufpt );
355
356	// Test if can continue without flushing the ufpt (and ifetch_queue)
357	if (flush_ufpt)
358	{
359	// // Optimisation : Test if ufpt have entry that need update prediction struction (as Return Address Stack)
360	// if (reg_UFPT_NB_NEED_UPDATE [context] == 0)
361	// {
362	// // Change state
363	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT (decod - miss - no flush ufpt)",context);
364	// reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT;
365
366	// // // Have an actual event ?
367	// // if (not reg_EVENT_VAL [context])
368	// // reg_EVENT_UPT_PTR [context] = upt_ptr_write;
369	// }
370	// else
371	// {
372	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- UPT_EVENT_STATE_KO_MISS_WAIT_UFPT (decod - miss - flush ufpt)",context);
373	// // just wait ufpt, don't flush upt
374	// reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_MISS_WAIT_UFPT;
375	// }
376
377	reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT;
378	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT_STATE [%d] <- %s (decod, miss)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
379
380	// Need Flush UPFT
381	flush_UFPT [context] = true;
382
383	// Write information
384	// reg_EVENT_IS_BRANCH [context] = true;
385	reg_EVENT_DEPTH [context] = upt_ptr_write;
386	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
387	reg_EVENT_ADDRESS_DEST_VAL[context] = direction;
388	reg_EVENT_ADDRESS_DEST [context] = address_dest;
389	reg_EVENT_CAN_CONTINUE [context] = can_continue;
390	}
391	// else can continue
392
393	// Push upt (from decod interface)
394	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._condition = condition;
395	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_src = address_src ;
396	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_dest = address_dest;
397	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._last_take = direction ;
398	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._good_take;
399	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._is_accurate = is_accurate;
400	// reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._history = ; // static prediction
401	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._address_ras = PORT_READ(in_DECOD_RAS_ADDRESS [i]);
402	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._index_ras = PORT_READ(in_DECOD_RAS_INDEX [i]);
403	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._ifetch_prediction = false; // static prediction
404	}
405
406	// In all case !!!
407	#ifdef DEBUG_TEST
408	if (reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state != UPDATE_PREDICTION_STATE_EMPTY)
409	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid upt state."));
410	#endif
411
412	// Change state
413	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_WAIT_END (decod - hit)",context,upt_ptr_write);
414	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._state = UPDATE_PREDICTION_STATE_WAIT_END;
415	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._retire_ok = false;
416	reg_UPDATE_PREDICTION_TABLE [context][upt_ptr_write]._miss_commit = false;
417
418	// Write new accurate
419	#ifdef DEBUG_TEST
420	if (not reg_IS_ACCURATE [context] and not is_accurate)
421	throw ERRORMORPHEO(FUNCTION,_("Decod : invalid accurate flag."));
422	#endif
423
424	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * is_accurate : %d",is_accurate);
425
426	reg_IS_ACCURATE [context] = is_accurate;
427
428	// Update pointer
429	reg_UPT_TOP [context] = top_next;
430	reg_UPT_EMPTY [context] = false; // new instruction
431	}
432
433	// ===================================================================
434	// =====[ UPDATE ]====================================================
435	// ===================================================================
436	{
437	bool can_continue [_param->_nb_context];
438	for (uint32_t i=0; i<_param->_nb_context; ++i)
439	can_continue [i] = true;
440
441	// For each updated instruction
442	for (uint32_t i=0; i<_param->_nb_inst_update; i++)
443	{
444	Tcontext_t context = internal_UPDATE_CONTEXT_ID [i];
445
446	// Test if transaction
447	// (an val_with_out is an update and don't need update prediction structure
448	if ((internal_UPDATE_VAL[i] and PORT_READ(in_UPDATE_ACK [i])) or
449	(internal_UPDATE_VAL_WITHOUT_ACK [i] and can_continue [context]))
450	{
451	Tdepth_t depth = internal_UPDATE_DEPTH [i];
452
453	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPDATE[%d] - Accepted",i);
454	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
455	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
456
457	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [context];
458
459	// One interface to two source :
460	// * from ufpt -> newest prediction
461	// * from upt -> oldest prediction
462	if (internal_UPDATE_FROM_UFPT [i])
463	{
464	// if free a slot, also all queue is updated
465	// Last slot ?
466	if ((--reg_UFPT_NB_UPDATE [context])==0)
467	{
468	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT_EVENT [%d] <- UFPT_EVENT_STATE_OK (update - end flush ufpt)",context);
469	reg_UFPT_EVENT_STATE [context] = UFPT_EVENT_STATE_OK;
470	reg_UFPT_NB_NEED_UPDATE [context] = 0;
471
472	// // Test upt event to change state
473	// // test if upt wait ufpt
474	// switch (upt_event_state)
475	// {
476	// // this case when don't need flush upt (miss decod and can continue)
477	// case UPT_EVENT_STATE_KO_MISS_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
478	// case UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_OK ; break;
479	// default : break;
480	// }
481
482	// reg_UPT_EVENT_STATE [context] = upt_event_state;
483	}
484
485	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Fetch Prediction Table");
486
487	// Change state
488	#ifdef DEBUG_TEST
489	if (reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state != UPDATE_FETCH_PREDICTION_STATE_EVENT)
490	throw ERRORMORPHEO(FUNCTION,_("Update : invalid ufpt state."));
491	#endif
492
493	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UFPT [%d][%d].state <- UPDATE_FETCH_PREDICTION_STATE_END (update)",context,depth);
494
495	reg_UPDATE_FETCH_PREDICTION_TABLE [context][depth]._state = UPDATE_FETCH_PREDICTION_STATE_END;
496
497	// Update pointer
498	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (before) : %d",reg_UFPT_UPDATE [context]);
499	reg_UFPT_UPDATE [context] = ((depth==0)?_param->_size_ufpt_queue[context]:depth)-1;
500	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [context]);
501	}
502	else
503	{
504	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Update Prediction Table");
505	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (before) : %d",reg_UPT_UPDATE [context]);
506	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(upt_event_state).c_str());
507
508	// Change state
509	#ifdef DEBUG_TEST
510	if (internal_UPDATE_RAS [i])
511	{
512	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_EVENT) and
513	(reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_KO ) )
514	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
515	}
516	else
517	{
518	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_OK )
519	throw ERRORMORPHEO(FUNCTION,_("Update : invalid upt state."));
520	}
521	#endif
522
523	#ifdef STATISTICS
524	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
525	#endif
526	bool ok = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_OK);
527	bool ko = (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_KO);
528
529	// Test if branch is valid (prediction can be incorrect)
530	if (ok or ko)
531	{
532	reg_UPDATE_PREDICTION_TABLE [context][depth]._retire_ok = true;
533	reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_prediction = ko;
534
535	#ifdef STATISTICS
536	if (usage_is_set(_usage,USE_STATISTICS))
537	{
538	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._ifetch_prediction)
539	(*_stat_nb_branch_ifetch_prediction [context])++;
540	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate)
541	(*_stat_nb_branch_accurate [context])++;
542	}
543	#endif
544	}
545
546	// Have an update, test the state to transiste to the good state
547	if (ko)
548	{
549	// Ko
550	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END_KO (update)",context,depth);
551
552	// Wait update of context_state
553	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END_KO;
554
555	reg_EVENT_UPT_PTR [context] = depth;
556
557	#ifdef STATISTICS
558	if (usage_is_set(_usage,USE_STATISTICS))
559	(*_stat_nb_branch_miss [context][condition])++;
560	#endif
561	}
562	else
563	{
564	// ok or event
565
566	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (update)",context,depth);
567	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_END;
568
569	#ifdef STATISTICS
570	if (usage_is_set(_usage,USE_STATISTICS))
571	{
572	if (ok)
573	(*_stat_nb_branch_hit [context][condition]) ++;
574	else
575	(*_stat_nb_branch_unused [context]) ++;
576	}
577	#endif
578	}
579
580	// Test if freeing the branch with no accurate ?
581	if ((reg_UPDATE_PREDICTION_TABLE [context][depth]._is_accurate == false) and not ko)
582	reg_IS_ACCURATE [context] = true;
583
584	// Update pointer
585	// * if update RAS : update pointer is decreaste until it equal at top pointer
586	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * internal_UPDATE_RAS [%d] : %d",i,internal_UPDATE_RAS [i]);
587
588	if (internal_UPDATE_RAS [i])
589	{
590	// if end_event, restart too bottom, else decrease pointer
591	bool end_event = (reg_UPT_UPDATE [context] == reg_UPT_TOP [context]);
592
593	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * end_event : %d",end_event);
594	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",reg_UPT_BOTTOM[context]);
595
596	if (end_event)
597	{
598	reg_UPT_UPDATE [context] = (end_event)?reg_UPT_BOTTOM[context]:(((depth==0)?_param->_size_upt_queue[context]:depth)-1);
599	// reg_UPT_UPDATE [context] = reg_UPT_BOTTOM[context];
600
601	switch (upt_event_state)
602	{
603	// this case when don't need flush upt (miss decod and can continue)
604	case UPT_EVENT_STATE_KO_MISS_FLUSH_UPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
605	case UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT :
606	{
607	upt_event_state = UPT_EVENT_STATE_OK;
608	reg_UPT_TOP [context] = reg_UPT_TOP_EVENT [context];
609	reg_UPT_UPDATE [context] = reg_UPT_TOP_EVENT [context];
610
611	break;
612	}
613	default : break;
614	}
615
616	}
617	else
618	{
619	// else, decrease update pointer
620	reg_UPT_UPDATE [context] = (((depth==0)?_param->_size_upt_queue[context]:depth)-1);
621	}
622	}
623	else
624	{
625	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * next update");
626
627	// increase pointer
628	reg_UPT_UPDATE [context] = (depth+1)%_param->_size_upt_queue[context];
629	}
630	// @@@
631	// special case :
632	if ((upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE) and
633	(reg_UPT_UPDATE [context] == reg_EVENT_UPT_PTR [context]))
634	{
635	reg_UPT_TOP [context] = reg_UPT_TOP_EVENT [context];
636	reg_UPT_UPDATE [context] = reg_UPT_TOP_EVENT [context];
637	reg_IS_ACCURATE [context] = true;
638
639	upt_event_state = UPT_EVENT_STATE_OK;
640	}
641
642	if ((ok and (upt_event_state == UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT)) and
643	(depth == reg_EVENT_DEPTH [context]))
644	{
645	// reg_UPT_TOP [context] = reg_UPT_TOP_EVENT [context];
646	// reg_UPT_UPDATE [context] = reg_UPT_TOP_EVENT [context];
647	reg_IS_ACCURATE [context] = true;
648
649	upt_event_state = UPT_EVENT_STATE_OK;
650	}
651
652	reg_UPT_EVENT_STATE [context] = upt_event_state;
653
654	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE (after ) : %d",reg_UPT_UPDATE[context]);
655	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(reg_UPT_EVENT_STATE [context]).c_str());
656	}
657	}
658	else
659	can_continue [context] = false;
660	}
661
662	// Round robin
663	reg_UPDATE_PRIORITY = (reg_UPDATE_PRIORITY+1)%_param->_nb_context;
664	}
665
666	// ===================================================================
667	// =====[ BRANCH_COMPLETE ]===========================================
668	// ===================================================================
669
670	// The branch is complete
671	// * Hit prediction :
672	// * update status
673	// * Miss prediction :
674	{
675	bool branch_complete_miss [_param->_nb_context];
676	for (uint32_t i=0; i<_param->_nb_context; ++i)
677	branch_complete_miss [i] = false;
678
679	for (uint32_t i=0; i<_param->_nb_inst_branch_complete; i++)
680	if (PORT_READ(in_BRANCH_COMPLETE_VAL[i]) and internal_BRANCH_COMPLETE_ACK [i])
681	{
682	// Read information
683	Tcontext_t context = (_param->_have_port_context_id)?PORT_READ(in_BRANCH_COMPLETE_CONTEXT_ID [i]):0;
684	Tdepth_t depth = (_param->_have_port_depth )?PORT_READ(in_BRANCH_COMPLETE_DEPTH [i]):0;
685	Tcontrol_t miss = internal_BRANCH_COMPLETE_MISS_PREDICTION [i];
686	Tcontrol_t good_take = internal_BRANCH_COMPLETE_TAKE [i];
687	Taddress_t good_addr = internal_BRANCH_COMPLETE_ADDRESS_DEST [i];
688
689	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [context];
690
691	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_COMPLETE[%d] - Accepted",i);
692	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",context);
693	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
694	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * miss : %d",miss);
695	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(upt_event_state).c_str());
696
697	// Test if the completed branch is a speculation miss
698	if (miss)
699	{
700	// special case : two branch complete on the same context.
701	// when the re order keep the order, the branch complete j is most speculative that the branch comple i if i < j
702	if (not branch_complete_miss [context])
703	{
704	branch_complete_miss [context] = true;
705	// Flush UPT
706	// get information
707	uint32_t top = reg_UPT_TOP [context];
708	uint32_t new_update = ((top==0)?_param->_size_upt_queue[context]:top)-1;
709
710	Taddress_t address_src = reg_UPDATE_PREDICTION_TABLE [context][depth]._address_src;
711	upt_state_t top_state = reg_UPDATE_PREDICTION_TABLE [context][top]._state;
712
713	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * upt_event_state : %s",toString(upt_event_state).c_str());
714	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top_state : %s",toString(top_state).c_str());
715
716	bool previous_ufpt_event = (reg_UFPT_EVENT_STATE [context] == UFPT_EVENT_STATE_KO_FLUSH);
717
718
719	bool previous_upt_event = (false
720	or (upt_event_state == UPT_EVENT_STATE_KO_MISS_WAIT_UFPT )
721	or (upt_event_state == UPT_EVENT_STATE_KO_MISS_FLUSH_UPT )
722	or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT)
723	or (upt_event_state == UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT)
724	or (upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE)
725	or (top_state == UPDATE_PREDICTION_STATE_END_KO )
726	or (top_state == UPDATE_PREDICTION_STATE_KO )
727	);
728
729	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
730	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * new_update : %d",new_update);
731	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_upt_event : %d",previous_upt_event);
732	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * previous_ufpt_event : %d",previous_ufpt_event);
733	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [context]);
734
735	// Have a miss !!!
736	// Flush UPFT
737	flush_UFPT [context] \|= not previous_ufpt_event;
738
739	// Test if the entry wait the branchment (else, they have a previous event)
740	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
741	{
742	// All instruction between the instruction and the top is disable
743	for (uint32_t j=(depth+1)%_param->_size_upt_queue[context];
744	j!=top;
745	j=(j+1)%_param->_size_upt_queue[context])
746	{
747	reg_UPDATE_PREDICTION_TABLE [context][j]._state = UPDATE_PREDICTION_STATE_EVENT;
748	reg_UPDATE_PREDICTION_TABLE [context][j]._retire_ok = false; // event
749	}
750
751	// New top
752	reg_UPT_TOP [context] = depth;
753
754	if (not previous_upt_event)
755	{
756	reg_UPT_TOP_EVENT [context] = top;
757	reg_UPT_UPDATE [context] = new_update;
758	}
759	else
760	{
761	// Have event. Top index this slot
762	reg_UPDATE_PREDICTION_TABLE [context][top]._retire_ok = false;
763
764	switch (top_state)
765	{
766	case UPDATE_PREDICTION_STATE_END_KO :
767	case UPDATE_PREDICTION_STATE_END :
768	{
769	// Have already update predictor
770	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_END;
771	reg_UPT_UPDATE [context] = new_update;
772	break;
773	}
774	case UPDATE_PREDICTION_STATE_KO :
775	{
776	// Doesn't have update predictor
777	reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
778	break;
779	}
780	default :
781	{
782	// reg_UPDATE_PREDICTION_TABLE [context][top]._state = UPDATE_PREDICTION_STATE_EVENT;
783	// break;
784
785	#ifdef DEBUG_TEST
786	throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
787	#endif
788	}
789	}
790	}
791
792	if (reg_UPT_BOTTOM [context] == reg_UPT_TOP [context])
793	reg_UPT_EMPTY [context] = true;
794
795	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_KO (branch_complete, ifetch hit)",context,depth);
796	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_KO;
797
798	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE [%d] : %d",context,reg_UFPT_NB_NEED_UPDATE [context]);
799
800	// if ( (reg_UFPT_NB_NEED_UPDATE [context] > 0) or
801	// (reg_UFPT_NB_UPDATE [context] > 0))
802	// {
803	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT (branch_complete - miss)",context);
804	// reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT;
805	// }
806	// else
807	// {
808	// // if (not previous_update_ras)
809	// {
810	// // have ras prediction ?
811	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_MISS_FLUSH_UPT (branch_complete - miss)",context);
812
813	// reg_EVENT_STATE [context] = EVENT_STATE_MISS_FLUSH_UPT;
814
815	// }
816	// }
817
818	reg_UPT_EVENT_STATE [context] = UPT_EVENT_STATE_KO_MISS_FLUSH_UPT;
819	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT_STATE [%d] <- %s (branch_complete, ifetch hit)",context,toString(reg_UPT_EVENT_STATE [context]).c_str());
820
821	// reg_EVENT_SOURCE [context] = EVENT_SOURCE_UPT;
822
823	// else no update
824
825	// reg_EVENT_IS_BRANCH [context] = true;
826	reg_EVENT_DEPTH [context] = depth;
827	reg_EVENT_ADDRESS_SRC [context] = address_src; // delay_slot is compute in Context_State
828	reg_EVENT_ADDRESS_DEST_VAL[context] = good_take;
829	reg_EVENT_ADDRESS_DEST [context] = good_addr;
830	reg_EVENT_CAN_CONTINUE [context] = true;
831	// reg_EVENT_CAN_CONTINUE [context] = false;
832	}
833
834	reg_UPDATE_PREDICTION_TABLE [context][depth]._miss_commit = true;
835	}
836	}
837	else
838	{
839	// Hit case
840
841	// #ifdef DEBUG_TEST
842	// if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state != UPDATE_PREDICTION_STATE_WAIT_END)
843	// throw ERRORMORPHEO(FUNCTION,_("Branch complete : invalid upt state."));
844	// #endif
845
846	// In same cycle, can have a previous branch_complete
847	if (reg_UPDATE_PREDICTION_TABLE [context][depth]._state == UPDATE_PREDICTION_STATE_WAIT_END)
848	{
849	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_OK (branch_complete, ifetch hit)",context,depth);
850	reg_UPDATE_PREDICTION_TABLE [context][depth]._state = UPDATE_PREDICTION_STATE_OK;
851	}
852	}
853
854	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s",toString(reg_UPT_EVENT_STATE [context]).c_str());
855
856	// In all case : update good_take
857	reg_UPDATE_PREDICTION_TABLE [context][depth]._good_take = good_take;
858
859	// Write address_dest if need read register
860	Tbranch_condition_t condition = reg_UPDATE_PREDICTION_TABLE [context][depth]._condition;
861
862	if ((condition == BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK) or
863	(condition == BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK ) or
864	(condition == BRANCH_CONDITION_READ_STACK ) )
865	reg_UPDATE_PREDICTION_TABLE [context][depth]._address_dest = good_addr;
866	}
867	}
868
869	// ===================================================================
870	// =====[ BRANCH_EVENT ]==============================================
871	// ===================================================================
872	for (uint32_t i=0; i<_param->_nb_context; i++)
873	if (internal_BRANCH_EVENT_VAL [i] and PORT_READ(in_BRANCH_EVENT_ACK [i]))
874	{
875	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * BRANCH_EVENT [%d] - Accepted",i);
876
877	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
878
879	switch (upt_event_state)
880	{
881	case UPT_EVENT_STATE_KO_DECODE_UPDATE_CONTEXT : upt_event_state = UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT; break;
882	case UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT; break;
883	default : break; // an other branch is occured
884	}
885
886	reg_UPT_EVENT_STATE [i] = upt_event_state;
887	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s (branch_event)",toString(upt_event_state).c_str());
888	}
889
890	// ===================================================================
891	// =====[ EVENT ]=====================================================
892	// ===================================================================
893	for (uint32_t i=0; i<_param->_nb_context; ++i)
894	if (PORT_READ(in_EVENT_VAL [i]) and internal_EVENT_ACK [i])
895	{
896	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT");
897
898	//----------------------------------------------------------------
899	// Cases
900	//----------------------------------------------------------------
901	// * EVENT_TYPE_NONE - nothing
902	// * EVENT_TYPE_MISS_SPECULATION - Change state, reset pointer
903	// * EVENT_TYPE_EXCEPTION - Flush upft and upt, Change state, reset pointer
904	// * EVENT_TYPE_BRANCH_NO_ACCURATE - nothing : manage in decod and update
905	// * EVENT_TYPE_SPR_ACCESS - nothing
906	// * EVENT_TYPE_MSYNC - nothing
907	// * EVENT_TYPE_PSYNC - nothing
908	// * EVENT_TYPE_CSYNC - nothing
909
910	Tevent_type_t event_type = PORT_READ(in_EVENT_TYPE [i]);
911	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
912
913	// Test if end of miss -> all previous branch is complete
914	// -> all next branch is finish
915
916	switch (event_type)
917	{
918	case EVENT_TYPE_BRANCH_MISS_SPECULATION :
919	{
920	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_BRANCH_MISS_SPECULATION");
921
922	switch (upt_event_state)
923	{
924	case UPT_EVENT_STATE_KO_COMMIT_WAIT_END_EVENT :
925	{
926	Tdepth_t depth = reg_EVENT_UPT_PTR [i];
927	Tdepth_t update = reg_UPT_UPDATE [i];
928
929	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * depth : %d",depth);
930
931	if (reg_UPDATE_PREDICTION_TABLE [i][depth]._state == UPDATE_PREDICTION_STATE_END_KO)
932	{
933	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d][%d].state <- UPDATE_PREDICTION_STATE_END (event)",i,depth);
934
935	reg_UPDATE_PREDICTION_TABLE [i][depth]._state = UPDATE_PREDICTION_STATE_END;
936	}
937
938	// Special case : branch_complete a speculative branch and the context_state signal the end of this event before the complete of previous branch
939	if (depth != update)
940	{
941	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_COMMIT_WAIT_END_UPDATE (event)",i);
942	upt_event_state = UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE;
943
944	break; // stop here
945	}
946
947	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
948	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
949
950	// break; continue
951	}
952	case UPT_EVENT_STATE_KO_DECODE_WAIT_END_EVENT :
953	{
954	// Change state
955	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * EVENT [%d] <- EVENT_STATE_OK (event)",i);
956
957	upt_event_state = UPT_EVENT_STATE_OK;
958	reg_IS_ACCURATE [i] = true;
959
960	break;
961	}
962	default : break; // an other branch is occured
963	}
964
965	break;
966	}
967	case EVENT_TYPE_LOAD_MISS_SPECULATION :
968	case EVENT_TYPE_EXCEPTION :
969	{
970	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * type : EVENT_TYPE_LOAD_MISS_SPECULATION");
971
972	// Have a miss !!!
973	// Flush UPFT
974	flush_UFPT [i] = true;
975
976	if (upt_event_state == UPT_EVENT_STATE_KO_COMMIT_WAIT_END_UPDATE)
977	{
978	reg_UPT_TOP [i] = reg_UPT_TOP_EVENT [i];
979	reg_UPT_UPDATE [i] = reg_UPT_TOP_EVENT [i];
980	reg_IS_ACCURATE [i] = true;
981
982	upt_event_state = UPT_EVENT_STATE_OK;
983	}
984
985	// Flush UPT
986	uint32_t bottom = reg_UPT_BOTTOM [i];
987
988	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * bottom : %d",bottom);
989
990	// event_state_t event_state = reg_EVENT_STATE [i];
991	// bool previous_update_ras = ((event_state == EVENT_STATE_MISS_FLUSH_UFPT_AND_UPT ) or
992	// (event_state == EVENT_STATE_MISS_FLUSH_UPT ) or
993	// (event_state == EVENT_STATE_EVENT_FLUSH_UFPT_AND_UPT) or
994	// (event_state == EVENT_STATE_EVENT_FLUSH_UPT));
995
996	bool find = false; // have slot to update ???
997	bool find_top = false;
998	Tdepth_t top = bottom;
999	Tdepth_t update = bottom;
1000	bool empty = reg_UPT_EMPTY [i];
1001
1002	// flush all slot, because this event is in head of rob
1003	for (uint32_t j=0; j<_param->_size_upt_queue[i]; ++j)
1004	{
1005	Tdepth_t x = (bottom+j)%_param->_size_upt_queue[i];
1006
1007	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT [%d] : %s",x,toString(reg_UPDATE_PREDICTION_TABLE [i][x]._state).c_str());
1008
1009	if ((reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_END) and
1010	(reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY))
1011	{
1012	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find at UPT[%d]",x);
1013
1014	find = true; // find a not empty slot
1015	reg_UPDATE_PREDICTION_TABLE [i][x]._state = UPDATE_PREDICTION_STATE_EVENT;
1016	reg_UPDATE_PREDICTION_TABLE [i][x]._retire_ok = false;
1017	update = x;
1018	}
1019
1020	if (reg_UPDATE_PREDICTION_TABLE [i][x]._state != UPDATE_PREDICTION_STATE_EMPTY)
1021	if (not find_top)
1022	{
1023	top = x;
1024	find_top = true;
1025	}
1026	}
1027
1028	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * find : %d",find);
1029	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * top : %d",top);
1030	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * update : %d",update);
1031
1032	// Test if have update slot
1033	reg_UPT_TOP_EVENT [i] = reg_UPT_TOP[i];
1034	if (find)
1035	{
1036	// TODO : special case : event is an exception on branch, also depth is not valid
1037	reg_UPT_TOP [i] = top; // depth is again valid
1038
1039	if (bottom == reg_UPT_TOP [i])
1040	reg_UPT_EMPTY [i] = true;
1041
1042	reg_UPT_UPDATE [i] = update;
1043	}
1044
1045	// new state :
1046	// * test if ufpt is empty
1047	// * ok : flush upft and upt
1048	// * ko : test if have previous flush upt
1049	// * ok : nothing
1050	// * ko : flush upt
1051	// reg_EVENT_VAL [i] = find;
1052	// reg_EVENT_IS_BRANCH [i] = false;
1053	// reg_EVENT_UPT_PTR [i] = ((top==0)?_param->_size_upt_queue[i]:top)-1; ///// ZE MODIF
1054	reg_EVENT_UPT_PTR [i] = top;
1055	reg_EVENT_UPT_FULL [i] = (not empty and (bottom == reg_UPT_TOP [i]));
1056	// reg_EVENT_DEPTH [i] = PORT_READ(in_EVENT_DEPTH [i]);//(top+1)%_param->_size_upt_queue[i];
1057	reg_EVENT_DEPTH [i] = top;
1058
1059	// reg_EVENT_ADDRESS_SRC [i] = address_src; // delay_slot is compute in I_State
1060	// reg_EVENT_ADDRESS_DEST_VAL[i] = good_take;
1061	// reg_EVENT_ADDRESS_DEST [i] = good_addr;
1062
1063	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
1064	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
1065	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
1066
1067	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d",reg_EVENT_VAL [i]);
1068	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d",reg_EVENT_UPT_PTR [i]);
1069	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d",reg_EVENT_UPT_FULL [i]);
1070	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1071	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
1072
1073	if (find)
1074	{
1075	// have ras prediction ?
1076	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT (event - find)",i);
1077
1078	upt_event_state = UPT_EVENT_STATE_KO_EVENT_FLUSH_UPT;
1079	}
1080	else
1081	{
1082	// special case : nothing
1083	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * UPT_EVENT [%d] <- UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT (event - not find)",i);
1084
1085	// reg_EVENT_VAL [i] = false;
1086
1087	upt_event_state = UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT;
1088	}
1089
1090	break;
1091	}
1092	default :
1093	{
1094	// nothing
1095	break;
1096	}
1097	}
1098
1099	reg_UPT_EVENT_STATE [i] = upt_event_state;
1100	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EVENT_STATE : %s (branch_event)",toString(upt_event_state).c_str());
1101	}
1102
1103	// ===================================================================
1104	// =====[ FLUSH ]=====================================================
1105	// ===================================================================
1106
1107	for (uint32_t i=0; i<_param->_nb_context; ++i)
1108	{
1109	if (flush_UFPT [i])
1110	{
1111	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Flush Update Fetch Prediction Table");
1112	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * context : %d",i);
1113	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1114
1115	// It's to accelerate miss speculation -> associative access
1116	if (reg_UFPT_NB_NEED_UPDATE [i] == 0)
1117	{
1118	// No entry need prediction, flush all entry -> Reset
1119	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
1120	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state = UPDATE_FETCH_PREDICTION_STATE_EMPTY;
1121	reg_UFPT_BOTTOM [i] = 0;
1122	reg_UFPT_TOP [i] = 0;
1123	}
1124	else
1125	{
1126	uint32_t bottom = reg_UFPT_BOTTOM [i];
1127	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; ++j)
1128	{
1129	uint32_t index = (bottom+j)%_param->_size_ufpt_queue[i];
1130	// EMPTY : no event
1131	// END : already update
1132	// EVENT : previous event
1133	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state == UPDATE_FETCH_PREDICTION_STATE_WAIT_DECOD)
1134	{
1135	reg_UFPT_UPDATE [i] = index;
1136	reg_UFPT_NB_UPDATE [i] ++;
1137	reg_UPDATE_FETCH_PREDICTION_TABLE [i][index]._state = UPDATE_FETCH_PREDICTION_STATE_EVENT;
1138	}
1139	}
1140
1141	// Change state
1142	reg_UFPT_EVENT_STATE [i] = UFPT_EVENT_STATE_KO_FLUSH;
1143	}
1144
1145	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE (after ) : %d",reg_UFPT_UPDATE [i]);
1146
1147	}
1148
1149	// Change state on UPT
1150	{
1151	upt_event_state_t upt_event_state = reg_UPT_EVENT_STATE [i];
1152	ufpt_event_state_t ufpt_event_state = reg_UFPT_EVENT_STATE [i];
1153
1154	// Test upt event to change state
1155	// test if upt wait ufpt
1156	if (ufpt_event_state == UFPT_EVENT_STATE_OK)
1157	switch (upt_event_state)
1158	{
1159	// this case when don't need flush upt (miss decod and can continue)
1160	case UPT_EVENT_STATE_KO_MISS_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_KO_COMMIT_UPDATE_CONTEXT; break;
1161	case UPT_EVENT_STATE_KO_EVENT_WAIT_UFPT : upt_event_state = UPT_EVENT_STATE_OK ; break;
1162	default : break;
1163	}
1164
1165	reg_UPT_EVENT_STATE [i] = upt_event_state;
1166	}
1167	}
1168
1169	#ifdef STATISTICS
1170	if (usage_is_set(_usage,USE_STATISTICS))
1171	for (uint32_t i=0; i<_param->_nb_context; i++)
1172	{
1173	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
1174	if (reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state != UPDATE_FETCH_PREDICTION_STATE_EMPTY)
1175	(*_stat_ufpt_queue_nb_elt [i]) ++;
1176	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
1177	if (reg_UPDATE_PREDICTION_TABLE [i][j]._state != UPDATE_PREDICTION_STATE_EMPTY)
1178	(*_stat_upt_queue_nb_elt [i]) ++;
1179	}
1180	#endif
1181
1182	// ===================================================================
1183	// =====[ PRINT ]=====================================================
1184	// ===================================================================
1185
1186	#if (DEBUG >= DEBUG_TRACE)
1187	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump Update_Prediction_Table");
1188	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPDATE_PRIORITY : %d",reg_UPDATE_PRIORITY);
1189	for (uint32_t i=0; i<_param->_nb_context; i++)
1190	{
1191	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_IS_ACCURATE : %d",reg_IS_ACCURATE [i]);
1192	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UFPT_STATE : %s" ,toString(reg_UFPT_EVENT_STATE [i]).c_str());
1193	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_STATE : %s" ,toString(reg_UPT_EVENT_STATE [i]).c_str());
1194	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_VAL : %d" ,reg_EVENT_VAL [i]);
1195	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_PTR : %d" ,reg_EVENT_UPT_PTR [i]);
1196	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_UPT_FULL : %d" ,reg_EVENT_UPT_FULL [i]);
1197	// log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_IS_BRANCH : %d" ,reg_EVENT_IS_BRANCH [i]);
1198	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_DEPTH : %d" ,reg_EVENT_DEPTH [i]);
1199	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_SRC : %.8x (%.8x)",reg_EVENT_ADDRESS_SRC [i],reg_EVENT_ADDRESS_SRC [i]<<2);
1200	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST_VAL: %d" ,reg_EVENT_ADDRESS_DEST_VAL[i]);
1201	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_ADDRESS_DEST : %.8x (%.8x)",reg_EVENT_ADDRESS_DEST [i],reg_EVENT_ADDRESS_DEST [i]<<2);
1202	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_EVENT_CAN_CONTINUE : %d" ,reg_EVENT_CAN_CONTINUE [i]);
1203
1204	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump UFPT [%d] (Update_Fetch_Prediction_Table)",i);
1205	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_BOTTOM : %d",reg_UFPT_BOTTOM [i]);
1206	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_TOP : %d",reg_UFPT_TOP [i]);
1207	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_UPDATE : %d",reg_UFPT_UPDATE [i]);
1208	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_NEED_UPDATE : %d",reg_UFPT_NB_NEED_UPDATE [i]);
1209	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UFPT_NB_UPDATE : %d",reg_UFPT_NB_UPDATE [i]);
1210	for (uint32_t j=0; j<_param->_size_ufpt_queue[i]; j++)
1211	{
1212	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d, %.8lld %.8x (%.8x) %.4d - %s",
1213	j,
1214	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._condition,
1215	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src,
1216	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_src<<2,
1217	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest,
1218	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_dest<<2,
1219	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._last_take,
1220	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._is_accurate,
1221	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._history,
1222	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras,
1223	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._address_ras<<2,
1224	reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._index_ras,
1225	toString(reg_UPDATE_FETCH_PREDICTION_TABLE [i][j]._state).c_str()
1226	);
1227	}
1228
1229	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * Dump UPT [%d] (Update_Prediction_Table)",i);
1230	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_BOTTOM : %d",reg_UPT_BOTTOM [i]);
1231	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP : %d",reg_UPT_TOP [i]);
1232	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_TOP_EVENT : %d",reg_UPT_TOP_EVENT [i]);
1233	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_UPDATE : %d",reg_UPT_UPDATE [i]);
1234	log_printf(TRACE,Update_Prediction_Table,FUNCTION," * reg_UPT_EMPTY : %d",reg_UPT_EMPTY [i]);
1235	for (uint32_t j=0; j<_param->_size_upt_queue[i]; j++)
1236	log_printf(TRACE,Update_Prediction_Table,FUNCTION," [%d] %.4d, %.8x (%.8x) %.8x (%.8x), %.1d %.1d %.1d, %.8lld %.8x (%.8x) %.4d - %s",
1237	j,
1238	reg_UPDATE_PREDICTION_TABLE [i][j]._condition,
1239	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src,
1240	reg_UPDATE_PREDICTION_TABLE [i][j]._address_src<<2,
1241	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest,
1242	reg_UPDATE_PREDICTION_TABLE [i][j]._address_dest<<2,
1243	reg_UPDATE_PREDICTION_TABLE [i][j]._last_take,
1244	reg_UPDATE_PREDICTION_TABLE [i][j]._good_take,
1245	reg_UPDATE_PREDICTION_TABLE [i][j]._is_accurate,
1246	reg_UPDATE_PREDICTION_TABLE [i][j]._history,
1247	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras,
1248	reg_UPDATE_PREDICTION_TABLE [i][j]._address_ras<<2,
1249	reg_UPDATE_PREDICTION_TABLE [i][j]._index_ras,
1250	toString(reg_UPDATE_PREDICTION_TABLE [i][j]._state).c_str()
1251	);
1252	}
1253	#endif
1254
1255	#ifdef DEBUG_TEST
1256	for (uint32_t i=0; i<_param->_nb_context; i++)
1257	{
1258	if (reg_UFPT_NB_NEED_UPDATE [i] > _param->_size_ufpt_queue[i])
1259	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_NEED_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_NEED_UPDATE [i],_param->_size_ufpt_queue[i]));
1260	if (reg_UFPT_NB_UPDATE [i] > _param->_size_ufpt_queue[i])
1261	throw ERRORMORPHEO(FUNCTION,toString(_("reg_UFPT_NB_UPDATE [%d] (%d) is > at size_ufpt_queue (%d).\n"),i,reg_UFPT_NB_UPDATE [i],_param->_size_ufpt_queue[i]));
1262	}
1263	#endif
1264
1265	}
1266
1267
1268	#if defined(STATISTICS) or defined(VHDL_TESTBENCH)
1269	end_cycle ();
1270	#endif
1271
1272	log_end(Update_Prediction_Table,FUNCTION);
1273	};
1274
1275	}; // end namespace update_prediction_table
1276	}; // end namespace prediction_unit
1277	}; // end namespace front_end
1278	}; // end namespace multi_front_end
1279	}; // end namespace core
1280
1281	}; // end namespace behavioural
1282	}; // end namespace morpheo
1283	#endif

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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Update_Prediction_Table/src/Update_Prediction_Table_transition.cpp @ 146

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