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source: trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp @ 131

Last change on this file since 131 was 131, checked in by rosiere, 15 years ago
1) add constant method 2) test with systemc 2.2.0
Property svn:keywords set to `Id`
File size: 10.4 KB

Line
1	/*
2	* $Id: test.cpp 131 2009-07-08 18:40:08Z rosiere $
3	*
4	* [ Description ]
5	*
6	* Test
7	*/
8
9	#define NB_ITERATION 1
10	#define CYCLE_MAX 100000*NB_ITERATION
11	#include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h"
12	#include "Common/include/Test.h"
13
14	void test (string name,
15	morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param)
16	{
17	cout << "<" << name << "> : Simulation SystemC" << endl;
18
19	try
20	{
21	cout << _param->print(1);
22	_param->test();
23	}
24	catch (morpheo::ErrorMorpheo & error)
25	{
26	cout << "<" << name << "> : " << error.what ();
27	return;
28	}
29	catch (...)
30	{
31	cerr << "<" << name << "> : This test must generate a error" << endl;
32	exit (EXIT_FAILURE);
33	}
34
35	_model.set_model(MODEL_SYSTEMC,true);
36
37	Tusage_t _usage = USE_ALL;
38
39	// _usage = usage_unset(_usage,USE_SYSTEMC );
40	// _usage = usage_unset(_usage,USE_VHDL );
41	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH );
42	// _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
43	// _usage = usage_unset(_usage,USE_POSITION );
44	// _usage = usage_unset(_usage,USE_STATISTICS );
45	// _usage = usage_unset(_usage,USE_INFORMATION );
46
47	#ifdef STATISTICS
48	morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,100);
49	#endif
50	RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic
51	(name.c_str()
52	#ifdef STATISTICS
53	,_param_stat
54	#endif
55	,_param
56	,_usage);
57
58	#ifdef SYSTEMC
59	/*********************************************************************
60	* Déclarations des signaux
61	*********************************************************************/
62	sc_clock CLOCK ("clock", 1.0, 0.5);
63	sc_signal<Tcontrol_t> NRESET;
64
65	sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read];
66	sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read];
67	sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read];
68	sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read];
69
70	sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write];
71	sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write];
72	sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write];
73	sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write];
74
75	sc_signal<Tcontrol_t> READ_WRITE_VAL [_param->_nb_port_read_write];
76	sc_signal<Tcontrol_t> READ_WRITE_ACK [_param->_nb_port_read_write];
77	sc_signal<Tcontrol_t> READ_WRITE_RW [_param->_nb_port_read_write];
78	sc_signal<Taddress_t> READ_WRITE_ADDRESS [_param->_nb_port_read_write];
79	sc_signal<Tdata_t> READ_WRITE_RDATA [_param->_nb_port_read_write];
80	sc_signal<Tdata_t> READ_WRITE_WDATA [_param->_nb_port_read_write];
81
82	/********************************************************
83	* Instanciation
84	********************************************************/
85
86	cout << "<" << name << "> Instanciation of registerfile" << endl;
87
88	(*(registerfile->in_CLOCK)) (CLOCK);
89	(*(registerfile->in_NRESET)) (NRESET);
90
91	for (uint32_t i=0; i<_param->_nb_port_read; i++)
92	{
93	(*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]);
94	(*(registerfile->out_READ_ACK [i])) (READ_ACK [i]);
95	if (_param->_have_port_address)
96	(*(registerfile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]);
97	(*(registerfile->out_READ_DATA [i])) (READ_DATA [i]);
98	}
99	for (uint32_t i=0; i<_param->_nb_port_write; i++)
100	{
101	(*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]);
102	(*(registerfile->out_WRITE_ACK [i])) (WRITE_ACK [i]);
103	if (_param->_have_port_address)
104	(*(registerfile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]);
105	(*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]);
106	}
107	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
108	{
109	(*(registerfile-> in_READ_WRITE_VAL [i])) (READ_WRITE_VAL [i]);
110	(*(registerfile->out_READ_WRITE_ACK [i])) (READ_WRITE_ACK [i]);
111	(*(registerfile-> in_READ_WRITE_RW [i])) (READ_WRITE_RW [i]);
112	if (_param->_have_port_address)
113	(*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS [i]);
114	(*(registerfile-> in_READ_WRITE_WDATA [i])) (READ_WRITE_WDATA [i]);
115	(*(registerfile->out_READ_WRITE_RDATA [i])) (READ_WRITE_RDATA [i]);
116	}
117
118	cout << "<" << name << "> Start Simulation ............" << endl;
119	Time * _time = new Time();
120
121	/********************************************************
122	* Simulation - Begin
123	********************************************************/
124
125	// Initialisation
126
127	SC_START(0);
128
129	for (uint32_t i=0; i<_param->_nb_port_write; i++)
130	WRITE_VAL [i] .write (0);
131	for (uint32_t i=0; i<_param->_nb_port_read; i++)
132	READ_VAL [i] .write (0);
133	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
134	READ_WRITE_VAL [i] .write (0);
135
136	NRESET.write(0);
137
138	SC_START(5);
139
140	NRESET.write(1);
141
142	for (uint32_t i=0; i<_param->_nb_port_write; i++)
143	TEST(Tcontrol_t,WRITE_ACK [i],1);
144	for (uint32_t i=0; i<_param->_nb_port_read; i++)
145	TEST(Tcontrol_t,READ_ACK [i],1);
146	for (uint32_t i=0; i<_param->_nb_port_read_write; i++)
147	TEST(Tcontrol_t,READ_WRITE_ACK [i],1);
148
149	for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++)
150	{
151	cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl;
152
153	// random init
154	uint32_t grain = 0;
155	//uint32_t grain = static_cast<uint32_t>(time(NULL));
156
157	srand(grain);
158
159	Tdata_t tab [_param->_nb_word];
160
161	for (uint32_t i=0; i<_param->_nb_word; i++)
162	tab[i]= rand()%(1<<(_param->_size_word-1));
163
164	Taddress_t address_next = 0;
165	Taddress_t nb_ack = 0;
166
167	while (nb_ack < _param->_nb_word)
168	{
169
170	cout << "cycle : " << static_cast<uint32_t> (simulation_cycle()) << endl;
171
172	for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
173	{
174	if ((address_next < _param->_nb_word) and
175	(WRITE_VAL [num_port].read() == 0))
176	{
177	cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
178
179	WRITE_VAL [num_port] .write(1);
180	WRITE_DATA [num_port] .write(tab[address_next]);
181	WRITE_ADDRESS [num_port] .write(address_next++);
182
183	// Address can be not a multiple of nb_port_write
184	if (address_next >= _param->_nb_word)
185	break;
186	}
187	}
188
189	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
190	{
191	if ((address_next < _param->_nb_word) and
192	(READ_WRITE_VAL [num_port].read() == 0))
193	{
194	cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl;
195
196	READ_WRITE_VAL [num_port] .write(1);
197	READ_WRITE_RW [num_port] .write(RW_WRITE);
198	READ_WRITE_WDATA [num_port] .write(tab[address_next]);
199	READ_WRITE_ADDRESS [num_port] .write(address_next++);
200
201	// Address can be not a multiple of nb_port_write
202	if (address_next >= _param->_nb_word)
203	break;
204	}
205	}
206
207	SC_START(1);
208
209	// reset write_val port
210	for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++)
211	{
212	if ((WRITE_ACK [num_port].read() == 1) and
213	(WRITE_VAL [num_port].read() == 1))
214	{
215	WRITE_VAL [num_port] .write(0);
216	nb_ack ++;
217	}
218	}
219	// reset write_val port
220	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
221	{
222	if ((READ_WRITE_ACK [num_port].read() == 1) and
223	(READ_WRITE_VAL [num_port].read() == 1))
224	{
225	READ_WRITE_VAL [num_port] .write(0);
226	nb_ack ++;
227	}
228	}
229
230	// SC_START(0);
231	}
232
233	address_next = 0;
234	nb_ack = 0;
235
236	cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl;
237
238	Tdata_t read_address [_param->_nb_port_read];
239	Tdata_t read_write_address [_param->_nb_port_read_write];
240
241	while (nb_ack < _param->_nb_word)
242	{
243	cout << "cycle : " << static_cast<uint32_t> (simulation_cycle()) << endl;
244
245	for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
246	{
247	if ((address_next < _param->_nb_word) and
248	(READ_VAL [num_port].read() == 0))
249	{
250	read_address [num_port] = address_next++;
251
252	READ_VAL [num_port].write(1);
253	READ_ADDRESS [num_port].write(read_address [num_port]);
254
255	if (address_next >= _param->_nb_word)
256	break;
257	}
258	}
259
260	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
261	{
262	if ((address_next < _param->_nb_word) and
263	(READ_WRITE_VAL [num_port].read() == 0))
264	{
265	read_write_address [num_port] = address_next++;
266
267	READ_WRITE_VAL [num_port].write(1);
268	READ_WRITE_RW [num_port].write(RW_READ);
269	READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]);
270
271	if (address_next >= _param->_nb_word)
272	break;
273	}
274	}
275
276
277	SC_START(1);
278
279	// reset write_val port
280	for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++)
281	{
282	if ((READ_ACK [num_port].read() == 1) and
283	(READ_VAL [num_port].read() == 1))
284	{
285	READ_VAL [num_port] .write(0);
286
287	cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl;
288
289	TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]);
290	nb_ack ++;
291	}
292	}
293
294	for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++)
295	{
296	if ((READ_WRITE_ACK [num_port].read() == 1) and
297	(READ_WRITE_VAL [num_port].read() == 1))
298	{
299	READ_WRITE_VAL [num_port] .write(0);
300
301	cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl;
302
303	TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]);
304	nb_ack ++;
305	}
306	}
307
308	// SC_START(0);
309	}
310	}
311
312	/********************************************************
313	* Simulation - End
314	********************************************************/
315
316	TEST_STR(bool,true,true, "End of Simulation");
317	delete _time;
318	cout << "<" << name << "> ............ Stop Simulation" << endl;
319
320	#endif
321
322	delete registerfile;
323	}

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