1 | /* |
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2 | * $Id: test.cpp 146 2011-02-01 20:57:54Z rosiere $ |
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3 | * |
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4 | * [ Description ] |
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5 | * |
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6 | * Test |
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7 | */ |
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8 | |
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9 | #define NB_ITERATION 1 |
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10 | #define CYCLE_MAX 100000*NB_ITERATION |
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11 | #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h" |
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12 | #include "Common/include/Test.h" |
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13 | |
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14 | void test (string name, |
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15 | morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param) |
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16 | { |
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17 | cout << "<" << name << "> : Simulation SystemC" << endl; |
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18 | |
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19 | try |
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20 | { |
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21 | cout << _param->print(1); |
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22 | _param->test(); |
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23 | } |
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24 | catch (morpheo::ErrorMorpheo & error) |
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25 | { |
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26 | cout << "<" << name << "> : " << error.what (); |
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27 | return; |
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28 | } |
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29 | catch (...) |
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30 | { |
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31 | cerr << "<" << name << "> : This test must generate a error" << endl; |
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32 | exit (EXIT_FAILURE); |
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33 | } |
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34 | |
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35 | _model.set_model(MODEL_SYSTEMC,true); |
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36 | |
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37 | Tusage_t _usage = USE_ALL; |
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38 | |
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39 | // _usage = usage_unset(_usage,USE_SYSTEMC ); |
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40 | // _usage = usage_unset(_usage,USE_VHDL ); |
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41 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH ); |
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42 | // _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT); |
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43 | // _usage = usage_unset(_usage,USE_POSITION ); |
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44 | // _usage = usage_unset(_usage,USE_STATISTICS ); |
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45 | // _usage = usage_unset(_usage,USE_INFORMATION ); |
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46 | |
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47 | #ifdef STATISTICS |
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48 | morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,100); |
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49 | #endif |
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50 | RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic |
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51 | (name.c_str() |
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52 | #ifdef STATISTICS |
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53 | ,_param_stat |
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54 | #endif |
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55 | ,_param |
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56 | ,_usage); |
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57 | |
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58 | #ifdef SYSTEMC |
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59 | /********************************************************************* |
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60 | * Déclarations des signaux |
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61 | *********************************************************************/ |
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62 | sc_clock CLOCK ("clock", 1.0, 0.5); |
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63 | sc_signal<Tcontrol_t> NRESET; |
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64 | |
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65 | sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read]; |
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66 | sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read]; |
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67 | sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read]; |
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68 | sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read]; |
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69 | |
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70 | sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write]; |
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71 | sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write]; |
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72 | sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write]; |
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73 | sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write]; |
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74 | |
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75 | /******************************************************** |
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76 | * Instanciation |
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77 | ********************************************************/ |
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78 | |
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79 | cout << "<" << name << "> Instanciation of registerfile" << endl; |
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80 | |
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81 | (*(registerfile->in_CLOCK)) (CLOCK); |
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82 | (*(registerfile->in_NRESET)) (NRESET); |
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83 | |
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84 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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85 | { |
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86 | (*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]); |
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87 | (*(registerfile->out_READ_ACK [i])) (READ_ACK [i]); |
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88 | if (_param->_have_port_address) |
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89 | (*(registerfile-> in_READ_ADDRESS [i])) (READ_ADDRESS [i]); |
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90 | (*(registerfile->out_READ_DATA [i])) (READ_DATA [i]); |
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91 | } |
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92 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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93 | { |
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94 | (*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]); |
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95 | (*(registerfile->out_WRITE_ACK [i])) (WRITE_ACK [i]); |
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96 | if (_param->_have_port_address) |
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97 | (*(registerfile-> in_WRITE_ADDRESS [i])) (WRITE_ADDRESS [i]); |
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98 | (*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]); |
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99 | } |
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100 | |
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101 | cout << "<" << name << "> Start Simulation ............" << endl; |
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102 | Time * _time = new Time(); |
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103 | |
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104 | /******************************************************** |
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105 | * Simulation - Begin |
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106 | ********************************************************/ |
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107 | |
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108 | // Initialisation |
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109 | |
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110 | SC_START(0); |
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111 | |
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112 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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113 | WRITE_VAL [i] .write (0); |
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114 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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115 | READ_VAL [i] .write (0); |
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116 | |
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117 | NRESET.write(0); |
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118 | |
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119 | SC_START(5); |
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120 | |
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121 | NRESET.write(1); |
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122 | |
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123 | for (uint32_t i=0; i<_param->_nb_port_write; i++) |
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124 | TEST(Tcontrol_t,WRITE_ACK [i],1); |
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125 | for (uint32_t i=0; i<_param->_nb_port_read; i++) |
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126 | TEST(Tcontrol_t,READ_ACK [i],1); |
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127 | |
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128 | for (uint32_t nb_iteration=0; nb_iteration < NB_ITERATION; nb_iteration ++) |
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129 | { |
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130 | cout << "<" << name << "> 1) Write the RegisterFile (no read)" << endl; |
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131 | |
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132 | // random init |
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133 | uint32_t grain = 0; |
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134 | //uint32_t grain = static_cast<uint32_t>(time(NULL)); |
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135 | |
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136 | srand(grain); |
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137 | |
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138 | Tdata_t tab [_param->_nb_word]; |
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139 | |
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140 | for (uint32_t i=0; i<_param->_nb_word; i++) |
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141 | tab[i]= rand()%(1<<(_param->_size_word-1)); |
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142 | |
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143 | Taddress_t address_next = 0; |
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144 | Taddress_t nb_ack = 0; |
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145 | |
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146 | while (nb_ack < _param->_nb_word) |
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147 | { |
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148 | |
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149 | cout << "cycle : " << static_cast<uint32_t> (simulation_cycle()) << endl; |
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150 | |
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151 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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152 | { |
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153 | if ((address_next < _param->_nb_word) and |
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154 | (WRITE_VAL [num_port].read() == 0)) |
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155 | { |
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156 | cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl; |
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157 | |
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158 | WRITE_VAL [num_port] .write(1); |
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159 | WRITE_DATA [num_port] .write(tab[address_next]); |
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160 | WRITE_ADDRESS [num_port] .write(address_next++); |
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161 | |
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162 | // Address can be not a multiple of nb_port_write |
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163 | if (address_next >= _param->_nb_word) |
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164 | break; |
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165 | } |
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166 | } |
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167 | |
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168 | SC_START(1); |
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169 | |
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170 | // reset write_val port |
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171 | for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) |
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172 | { |
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173 | if ((WRITE_ACK [num_port].read() == 1) and |
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174 | (WRITE_VAL [num_port].read() == 1)) |
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175 | { |
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176 | WRITE_VAL [num_port] .write(0); |
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177 | nb_ack ++; |
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178 | } |
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179 | } |
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180 | |
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181 | // SC_START(0); |
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182 | } |
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183 | |
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184 | address_next = 0; |
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185 | nb_ack = 0; |
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186 | |
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187 | cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; |
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188 | |
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189 | Tdata_t read_address [_param->_nb_port_read]; |
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190 | |
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191 | while (nb_ack < _param->_nb_word) |
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192 | { |
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193 | cout << "cycle : " << static_cast<uint32_t> (simulation_cycle()) << endl; |
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194 | |
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195 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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196 | { |
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197 | if ((address_next < _param->_nb_word) and |
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198 | (READ_VAL [num_port].read() == 0)) |
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199 | { |
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200 | read_address [num_port] = address_next++; |
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201 | |
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202 | READ_VAL [num_port].write(1); |
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203 | READ_ADDRESS [num_port].write(read_address [num_port]); |
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204 | |
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205 | if (address_next >= _param->_nb_word) |
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206 | break; |
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207 | } |
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208 | } |
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209 | |
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210 | |
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211 | SC_START(1); |
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212 | |
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213 | // reset write_val port |
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214 | for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) |
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215 | { |
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216 | if ((READ_ACK [num_port].read() == 1) and |
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217 | (READ_VAL [num_port].read() == 1)) |
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218 | { |
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219 | READ_VAL [num_port] .write(0); |
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220 | |
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221 | cout << "(" << num_port << ") [" << read_address [num_port] << "] => " << READ_DATA [num_port].read() << endl; |
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222 | |
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223 | TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]); |
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224 | nb_ack ++; |
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225 | } |
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226 | } |
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227 | |
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228 | // SC_START(0); |
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229 | } |
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230 | } |
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231 | |
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232 | /******************************************************** |
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233 | * Simulation - End |
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234 | ********************************************************/ |
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235 | |
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236 | TEST_STR(bool,true,true, "End of Simulation"); |
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237 | delete _time; |
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238 | cout << "<" << name << "> ............ Stop Simulation" << endl; |
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239 | |
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240 | #endif |
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241 | |
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242 | delete registerfile; |
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243 | } |
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