source: trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_testbench_generate_file.cpp @ 88

Last change on this file since 88 was 88, checked in by rosiere, 15 years ago

Almost complete design
with Test and test platform

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Line 
1#ifdef VHDL_TESTBENCH
2
3/*
4 * $Id: Interfaces_testbench_generate_file.cpp 88 2008-12-10 18:31:39Z rosiere $
5 *
6 * [ Description ]
7 *
8 */
9
10#include "Behavioural/include/Interfaces.h"
11
12namespace morpheo              {
13namespace behavioural          {
14
15  void Interfaces::testbench_generate_file  (void) 
16  {
17    log_printf(FUNC,Behavioural,"generate_file","Begin");
18
19    Vhdl   *    vhdl        = new Vhdl(_name+"_Testbench");
20    std::string counter     = "counter";
21    Signal *    clock       = this->get_clock();
22    Signal *    reset       = this->get_reset();
23    std::string clock_name  = clock->get_name();
24    std::string reset_name  = reset->get_name();
25    uint32_t    cycle       = this->get_cycle();
26
27    vhdl->set_signal    (clock_name, 1, 0);
28    vhdl->set_signal    (reset_name, 1, 0);
29    vhdl->set_signal    (counter, "natural");
30    this->set_signal    (vhdl);
31
32    vhdl->set_body("");
33    vhdl->set_body("------------------------------------------------------");
34    vhdl->set_body("-- Component - Intanciation");
35    vhdl->set_body("------------------------------------------------------");
36    vhdl->set_body("");
37
38    std::list<std::string> * list_signal = new std::list<std::string>;
39    this->get_signal (list_signal);
40
41    vhdl->set_library_work (_name + "_Pack");
42    vhdl->set_body("instance_"+_name+" : "+_name);
43    vhdl->set_body("port map (");
44
45    std::list<std::string>::iterator i   = list_signal->begin();
46    if (i != list_signal->end())
47      {
48        vhdl->set_body("\t "+*i+"\t=>\t"+*i);
49        ++i;
50      }
51    while (i != list_signal->end())
52      {
53        vhdl->set_body("\t,"+*i+"\t=>\t"+*i);
54        ++i;
55      }
56    vhdl->set_body("         );");
57
58    delete list_signal;
59
60    std::string test_name = this->testbench_body(vhdl,counter, reset_name);
61
62    vhdl->set_body("");
63    vhdl->set_body("------------------------------------------------------");
64    vhdl->set_body("-- reset");
65    vhdl->set_body("------------------------------------------------------");
66    vhdl->set_body("");
67    vhdl->set_body("-- if the systemC simulate have multiple reset, we make the last");
68    vhdl->set_body(reset_name+" <= '1' after 150 ns;");   
69
70    vhdl->set_body("");
71    vhdl->set_body("------------------------------------------------------");
72    vhdl->set_body("-- process clock_name");
73    vhdl->set_body("------------------------------------------------------");
74    vhdl->set_body("");
75    vhdl->set_body(clock_name+" <= not "+clock_name+" after 50 ns;");
76    vhdl->set_body("");
77    vhdl->set_body("process ("+clock_name+")");
78    vhdl->set_body("begin");
79    vhdl->set_body("\tif ("+clock_name+"'event and "+clock_name+" = '1') then");
80    vhdl->set_body("");
81    vhdl->set_body("\t\tif ("+reset_name+" = '0') then");
82    vhdl->set_body("");
83    vhdl->set_body("\t\t\t"+counter+" <= "+toString(reset->get_reset_cycle(true))+";");
84    vhdl->set_body("");
85    vhdl->set_body("\t\telse");
86    vhdl->set_body("");
87    vhdl->set_body("\t\t\t"+counter+" <= "+counter+"+1;");
88    vhdl->set_body("");
89#ifdef VHDL_TESTBENCH_ASSERT
90    for (uint32_t cpt=0; cpt<=cycle; cpt++)
91      vhdl->set_body("\t\t\tassert not ("+counter+" = "+toString(cpt)+") report \"===== Test number "+toString(cpt)+" =====\" severity NOTE;");
92
93    for (std::list<Interface_fifo*>::iterator it=_list_interface->begin();
94         it!=_list_interface->end();
95         ++it)
96      {
97        Vhdl * vhdl_assert = new Vhdl("");
98
99        (*it)->testbench_assert (vhdl_assert,counter);
100
101        vhdl->set_body(vhdl_assert);
102       
103        delete vhdl_assert;
104      }
105#endif
106
107    vhdl->set_body("");
108    vhdl->set_body("\t\t\tassert not ("+counter+" >= "+toString(cycle)+") report \"Test OK\" severity FAILURE;");
109    vhdl->set_body("\t\t\tassert not ("+test_name+" = '0') report \"Test KO\" severity FAILURE;");
110    vhdl->set_body("\t\tend if;");
111    vhdl->set_body("\tend if;");
112    vhdl->set_body("end process;");
113
114    vhdl->generate_file(false,true);
115
116    delete vhdl;
117   
118    log_printf(FUNC,Behavioural,"generate_file","End");
119  };
120
121}; // end namespace behavioural         
122}; // end namespace morpheo             
123
124#endif
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