Ignore:
Timestamp:
Dec 10, 2008, 7:31:39 PM (15 years ago)
Author:
rosiere
Message:

Almost complete design
with Test and test platform

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Interfaces_testbench_generate_file.cpp

    r81 r88  
    1717    log_printf(FUNC,Behavioural,"generate_file","Begin");
    1818
    19     Vhdl   * vhdl        = new Vhdl(_name+"_Testbench");
    20     std::string   counter     = "counter";
    21     Signal * clock       = this->get_clock();
    22     Signal * reset       = this->get_reset();
    23     std::string   clock_name  = clock->get_name();
    24     std::string   reset_name  = reset->get_name();
    25     uint32_t cycle       = this->get_cycle();
     19    Vhdl   *    vhdl        = new Vhdl(_name+"_Testbench");
     20    std::string counter     = "counter";
     21    Signal *    clock       = this->get_clock();
     22    Signal *    reset       = this->get_reset();
     23    std::string clock_name  = clock->get_name();
     24    std::string reset_name  = reset->get_name();
     25    uint32_t    cycle       = this->get_cycle();
    2626
    2727    vhdl->set_signal    (clock_name, 1, 0);
     
    8787    vhdl->set_body("\t\t\t"+counter+" <= "+counter+"+1;");
    8888    vhdl->set_body("");
    89     vhdl->set_body("\t\t\tassert not ("+counter+" >= "+toString(cycle)+") report \"Test OK\" severity FAILURE;");
    90     vhdl->set_body("\t\t\tassert not ("+test_name+" = '0') report \"Test KO\" severity FAILURE;");
    91 
    9289#ifdef VHDL_TESTBENCH_ASSERT
    93     vhdl->set_body("\t\t\t-- Assert ...");
    9490    for (uint32_t cpt=0; cpt<=cycle; cpt++)
    9591      vhdl->set_body("\t\t\tassert not ("+counter+" = "+toString(cpt)+") report \"===== Test number "+toString(cpt)+" =====\" severity NOTE;");
     92
     93    for (std::list<Interface_fifo*>::iterator it=_list_interface->begin();
     94         it!=_list_interface->end();
     95         ++it)
     96      {
     97        Vhdl * vhdl_assert = new Vhdl("");
     98
     99        (*it)->testbench_assert (vhdl_assert,counter);
     100
     101        vhdl->set_body(vhdl_assert);
     102       
     103        delete vhdl_assert;
     104      }
    96105#endif
    97106
    98107    vhdl->set_body("");
     108    vhdl->set_body("\t\t\tassert not ("+counter+" >= "+toString(cycle)+") report \"Test OK\" severity FAILURE;");
     109    vhdl->set_body("\t\t\tassert not ("+test_name+" = '0') report \"Test KO\" severity FAILURE;");
    99110    vhdl->set_body("\t\tend if;");
    100111    vhdl->set_body("\tend if;");
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