Ignore:
Timestamp:
Jan 16, 2009, 5:55:32 PM (15 years ago)
Author:
moulu
Message:

1) write queue vhdl
2) bug fix : in generic queue

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Write_unit/Write_unit/Write_queue/src/Write_queue_vhdl_body.cpp

    r81 r103  
    2525    log_printf(FUNC,Write_queue,FUNCTION,"Begin");
    2626    vhdl->set_body ("");
     27    vhdl->set_comment(0,"");
     28    vhdl->set_comment(0,"-----------------------------------");
     29    vhdl->set_comment(0,"-- Instance queue                  ");
     30    vhdl->set_comment(0,"-----------------------------------");
     31    vhdl->set_comment(0,"");
     32
     33    vhdl->set_body   (0,"instance_"+_name+"_queue : "+_name+"_queue");
     34    vhdl->set_body   (0,"port map (");
     35    vhdl->set_body   (1,"  in_CLOCK       \t=>\t      in_CLOCK ");
     36    vhdl->set_body   (1,", in_NRESET      \t=>\t      in_NRESET");
     37    vhdl->set_body   (1,", in_INSERT_VAL  \t=>\tsig_QUEUE_INSERT_VAL");
     38    vhdl->set_body   (1,",out_INSERT_ACK  \t=>\tsig_QUEUE_INSERT_ACK");
     39    vhdl->set_body   (1,", in_INSERT_DATA \t=>\tsig_QUEUE_INSERT_DATA");
     40    vhdl->set_body   (1,",out_RETIRE_VAL  \t=>\tsig_QUEUE_RETIRE_VAL");
     41    vhdl->set_body   (1,", in_RETIRE_ACK  \t=>\tsig_QUEUE_RETIRE_ACK");
     42    vhdl->set_body   (1,",out_RETIRE_DATA \t=>\tsig_QUEUE_RETIRE_DATA");
     43    for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
     44      {
     45        vhdl->set_body (1,",out_SLOT_"+toString(i)+"_VAL    \t=>\tsig_QUEUE_SLOT_"+toString(i)+"_VAL");
     46        vhdl->set_body (1,",out_SLOT_"+toString(i)+"_DATA   \t=>\tsig_QUEUE_SLOT_"+toString(i)+"_DATA");
     47      }
     48    vhdl->set_body   (0,");");
     49
     50    vhdl->set_body   (0,"");
     51
     52
     53    vhdl->set_comment(0,"");
     54    vhdl->set_comment(0,"-----------------------------------");
     55    vhdl->set_comment(0,"-- Insides                         ");
     56    vhdl->set_comment(0,"-----------------------------------");
     57    vhdl->set_comment(0,"");
     58
     59    vhdl->set_body   (0,"write_rd_re_bis: process (in_CLOCK)");
     60    vhdl->set_body   (0,"begin  -- process write rd/re bis");
     61    vhdl->set_body   (1,"if in_CLOCK'event and in_CLOCK = '1' then");
     62// #ifdef SYSTEMC_VHDL_COMPATIBILITY
     63//     vhdl->set_body   (2,"if (in_NRESET = '0') then");   
     64//     vhdl->set_body   (2,"reg_GPR_WRITE <= '0';");
     65//     vhdl->set_body   (2,"reg_SPR_WRITE <= '0';");
     66//     vhdl->set_body   (2,"else");
     67// #endif
     68      vhdl->set_body   (2,"reg_UPDATE <= (in_WRITE_QUEUE_OUT_ACK and sig_WRITE_QUEUE_OUT_VAL) or (not sig_QUEUE_RETIRE_VAL);");
     69
     70    vhdl->set_body   (2,"if (sig_GPR_WRITE_0_VAL = '1' and in_GPR_WRITE_0_ACK = '1') then");   
     71    vhdl->set_body   (3,"reg_GPR_WRITE <= '0';");
     72    vhdl->set_body   (2,"else");
     73    vhdl->set_body   (3,"reg_GPR_WRITE <= sig_GPR_WRITE;");
     74    vhdl->set_body   (2,"end if;");
     75
     76    vhdl->set_body   (2,"if (sig_SPR_WRITE_0_VAL = '1' and in_SPR_WRITE_0_ACK = '1') then");   
     77    vhdl->set_body   (3,"reg_SPR_WRITE <= '0';");
     78    vhdl->set_body   (2,"else");
     79    vhdl->set_body   (3,"reg_SPR_WRITE <= sig_SPR_WRITE;");
     80    vhdl->set_body   (2,"end if;");
     81
     82// #ifdef SYSTEMC_VHDL_COMPATIBILITY
     83//     vhdl->set_body   (2,"end if;");
     84// #endif
     85    vhdl->set_body   (1,"end if;");
     86    vhdl->set_body   (0,"end process write_rd_re_bis;");
     87
     88    vhdl->set_body   (0,"sig_GPR_WRITE <= sig_WRITE_RD when (reg_UPDATE = '1') else reg_GPR_WRITE;");
     89    vhdl->set_body   (0,"sig_SPR_WRITE <= sig_WRITE_RE when (reg_UPDATE = '1') else reg_SPR_WRITE;");
     90    vhdl->set_body   (0,"sig_GPR_WRITE_0_VAL <= sig_QUEUE_RETIRE_VAL and sig_GPR_WRITE;");
     91    vhdl->set_body   (0,"sig_SPR_WRITE_0_VAL <= sig_QUEUE_RETIRE_VAL and sig_SPR_WRITE;");
     92    vhdl->set_body   (0,"sig_DELETE_QUEUE_FRONT <= sig_QUEUE_RETIRE_VAL and not sig_GPR_WRITE and not sig_SPR_WRITE when (sig_WRITE_QUEUE_OUT_EXCEPTION = "+toString(EXCEPTION_MEMORY_LOAD_SPECULATIVE)+") else '0';");
     93    vhdl->set_body   (0,"sig_WRITE_QUEUE_OUT_VAL <= sig_QUEUE_RETIRE_VAL and not sig_DELETE_QUEUE_FRONT and not sig_GPR_WRITE and not sig_SPR_WRITE;");
     94    vhdl->set_body   (0,"sig_QUEUE_RETIRE_ACK <= sig_DELETE_QUEUE_FRONT or (in_WRITE_QUEUE_OUT_ACK and sig_WRITE_QUEUE_OUT_VAL);");
     95
     96    if (_param->_nb_bypass_write > 0)
     97      {
     98        vhdl->set_body (0,"sig_BYPASS_WRITE_0_GPR_VAL <= sig_GPR_WRITE_0_VAL;");
     99        vhdl->set_body (0,"sig_BYPASS_WRITE_0_SPR_VAL <= sig_SPR_WRITE_0_VAL;");
     100      }
     101
     102    for (uint32_t i=1; i<_param->_nb_bypass_write; i++)
     103      {
     104        vhdl->set_body (0,"sig_BYPASS_WRITE_"+toString(i)+"_GPR_VAL <= sig_QUEUE_SLOT_"+toString(i)+"_VAL and sig_BYPASS_WRITE_"+toString(i)+"_WRITE_RD;");
     105        vhdl->set_body (0,"sig_BYPASS_WRITE_"+toString(i)+"_SPR_VAL <= sig_QUEUE_SLOT_"+toString(i)+"_VAL and sig_BYPASS_WRITE_"+toString(i)+"_WRITE_RE;");
     106      }
     107
     108    vhdl->set_body   (0,"");
     109
     110
     111    vhdl->set_comment(0,"");
     112    vhdl->set_comment(0,"-----------------------------------");
     113    vhdl->set_comment(0,"-- Input  Buffer                   ");
     114    vhdl->set_comment(0,"-----------------------------------");
     115    vhdl->set_comment(0,"");
     116
     117    {
     118    uint32_t min = 0;
     119    uint32_t max, size;
     120
     121    if(_param->_have_port_context_id   )
     122      {
     123    size = _param->_size_context_id;
     124    max = min-1+size;
     125    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_CONTEXT_ID;");
     126    min = max+1;
     127      }
     128    if(_param->_have_port_front_end_id   )
     129      {
     130    size = _param->_size_front_end_id;
     131    max = min-1+size;
     132    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_FRONT_END_ID;");
     133    min = max+1;
     134      }
     135    if(_param->_have_port_ooo_engine_id   )
     136      {
     137    size = _param->_size_ooo_engine_id;
     138    max = min-1+size;
     139    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_OOO_ENGINE_ID;");
     140    min = max+1;
     141      }
     142    if(_param->_have_port_rob_ptr)
     143      {
     144    size = _param->_size_rob_ptr;
     145    max = min-1+size;
     146    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_PACKET_ID;");
     147    min = max+1;
     148      }
     149
     150    size = 1;
     151    max = min-1+size;
     152    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_WRITE_RD;");
     153    min = max+1;
     154
     155    size = _param->_size_general_register;
     156    max = min-1+size;
     157    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_NUM_REG_RD;");
     158    min = max+1;
     159
     160    size = _param->_size_general_data;
     161    max = min-1+size;
     162    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_DATA_RD;");
     163    min = max+1;
     164
     165    size = 1;
     166    max = min-1+size;
     167    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_WRITE_RE;");
     168    min = max+1;
     169
     170    size = _param->_size_special_register;
     171    max = min-1+size;
     172    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_NUM_REG_RE;");
     173    min = max+1;
     174
     175    size = _param->_size_special_data;
     176    max = min-1+size;
     177    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_DATA_RE;");
     178    min = max+1;
     179
     180    size = _param->_size_exception;   
     181    max = min-1+size;
     182    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_EXCEPTION;");
     183    min = max+1;
     184
     185    size = 1;
     186    max = min-1+size;
     187    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_NO_SEQUENCE;");
     188    min = max+1;
     189
     190    size = _param->_size_instruction_address;
     191    max = min-1+size;
     192    vhdl->set_body   (0,"sig_QUEUE_INSERT_DATA "+std_logic_range(_param->_size_internal_queue,max,min)+" <= in_WRITE_QUEUE_IN_ADDRESS;");
     193    min = max+1;
     194    }
     195
     196    vhdl->set_body   (0,"");
     197
     198
     199    vhdl->set_comment(0,"");
     200    vhdl->set_comment(0,"-----------------------------------");
     201    vhdl->set_comment(0,"-- Output Buffer                   ");
     202    vhdl->set_comment(0,"-----------------------------------");
     203    vhdl->set_comment(0,"");
     204    vhdl->set_body   (0,"out_WRITE_QUEUE_OUT_VAL    <= sig_WRITE_QUEUE_OUT_VAL;");
     205    if(_param->_have_port_context_id)
     206    vhdl->set_body   (0,"out_WRITE_QUEUE_OUT_CONTEXT_ID    <= sig_WRITE_QUEUE_OUT_CONTEXT_ID   ;");
     207    if(_param->_have_port_front_end_id)
     208    vhdl->set_body   (0,"out_WRITE_QUEUE_OUT_FRONT_END_ID  <= sig_WRITE_QUEUE_OUT_FRONT_END_ID ;");
     209    if(_param->_have_port_ooo_engine_id)
     210    vhdl->set_body   (0,"out_WRITE_QUEUE_OUT_OOO_ENGINE_ID <= sig_WRITE_QUEUE_OUT_OOO_ENGINE_ID;");
     211    if(_param->_have_port_rob_ptr)
     212    vhdl->set_body   (0,"out_WRITE_QUEUE_OUT_PACKET_ID     <= sig_WRITE_QUEUE_OUT_PACKET_ID    ;");
     213    vhdl->set_body   (0,"out_WRITE_QUEUE_OUT_FLAGS         <= sig_WRITE_QUEUE_OUT_FLAGS        ;");
     214    vhdl->set_body   (0,"out_WRITE_QUEUE_OUT_EXCEPTION     <= sig_WRITE_QUEUE_OUT_EXCEPTION    ;");
     215    vhdl->set_body   (0,"out_WRITE_QUEUE_OUT_NO_SEQUENCE   <= sig_WRITE_QUEUE_OUT_NO_SEQUENCE  ;");
     216    vhdl->set_body   (0,"out_WRITE_QUEUE_OUT_ADDRESS       <= sig_WRITE_QUEUE_OUT_ADDRESS      ;");
     217    vhdl->set_body   (0,"out_WRITE_QUEUE_OUT_DATA          <= sig_WRITE_QUEUE_OUT_DATA         ;");
     218    vhdl->set_body ("");
     219
     220    vhdl->set_body (0,"out_GPR_WRITE_0_VAL                 <= sig_GPR_WRITE_0_VAL;");
     221    if(_param->_have_port_ooo_engine_id)
     222    vhdl->set_body (0,"out_GPR_WRITE_0_OOO_ENGINE_ID       <= sig_GPR_WRITE_0_OOO_ENGINE_ID;");
     223    vhdl->set_body (0,"out_GPR_WRITE_0_NUM_REG             <= sig_GPR_WRITE_0_NUM_REG;");
     224    vhdl->set_body (0,"out_GPR_WRITE_0_DATA                <= sig_GPR_WRITE_0_DATA;");
     225
     226    for (uint32_t i=1; i<_param->_nb_gpr_write; i++)
     227      vhdl->set_body (0,"out_GPR_WRITE_"+toString(i)+"_VAL                 <= '0';");
     228
     229    vhdl->set_body (0,"out_SPR_WRITE_0_VAL                 <= sig_SPR_WRITE_0_VAL;");
     230    if(_param->_have_port_ooo_engine_id)
     231    vhdl->set_body (0,"out_SPR_WRITE_0_OOO_ENGINE_ID       <= sig_SPR_WRITE_0_OOO_ENGINE_ID;");
     232    vhdl->set_body (0,"out_SPR_WRITE_0_NUM_REG             <= sig_SPR_WRITE_0_NUM_REG;");
     233    vhdl->set_body (0,"out_SPR_WRITE_0_DATA                <= sig_SPR_WRITE_0_DATA;");
     234
     235    for (uint32_t i=1; i<_param->_nb_spr_write; i++)
     236      vhdl->set_body (0,"out_SPR_WRITE_"+toString(i)+"_VAL                 <= '0';");
     237
     238    vhdl->set_body ("");
     239
     240    for (uint32_t i=0; i<_param->_nb_bypass_write; i++)
     241      {
     242        vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_GPR_VAL          <= sig_BYPASS_WRITE_"+toString(i)+"_GPR_VAL;");
     243        vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG      <= sig_BYPASS_WRITE_"+toString(i)+"_GPR_NUM_REG;");
     244        vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_GPR_DATA         <= sig_BYPASS_WRITE_"+toString(i)+"_GPR_DATA;");
     245
     246        vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_SPR_VAL          <= sig_BYPASS_WRITE_"+toString(i)+"_SPR_VAL;");
     247        vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG      <= sig_BYPASS_WRITE_"+toString(i)+"_SPR_NUM_REG;");
     248        vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_SPR_DATA         <= sig_BYPASS_WRITE_"+toString(i)+"_SPR_DATA;");
     249
     250        if(_param->_have_port_ooo_engine_id)
     251        vhdl->set_body (0,"out_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID    <= sig_BYPASS_WRITE_"+toString(i)+"_OOO_ENGINE_ID;");
     252      }
     253
    27254    log_printf(FUNC,Write_queue,FUNCTION,"End");
    28255  };
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