Changeset 106 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
- Timestamp:
- Feb 9, 2009, 11:55:26 PM (15 years ago)
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_transition.cpp
r104 r106 18 18 namespace load_store_unit { 19 19 20 template <typename T> 21 T swapBytes (T data, uint32_t size_data, uint32_t size_access) 22 { 23 uint64_t x = static_cast<uint64_t>(data); 24 25 // switch (size_data) 26 // { 27 // case 2 : // 16 bits 28 // { 29 // switch (size_access) 30 // { 31 // case 2 : 32 // { 33 // x = ((((x>> 8)&0xff) << 0) | 34 // (((x>> 0)&0xff) << 8) ); 35 // break; 36 // } 37 // default : 38 // { 39 // break; 40 // } 41 // } 42 // break; 43 // } 44 // case 4 : // 32 bits 45 // { 46 // switch (size_access) 47 // { 48 // case 2 : 49 // { 50 // x = ((((x>> 8)&0xff) << 0) | 51 // (((x>> 0)&0xff) << 8) | 52 // (((x>>24)&0xff) << 16) | 53 // (((x>>16)&0xff) << 24) ); 54 // break; 55 // } 56 // case 4 : 57 // { 58 // x = ((((x>>24)&0xff) << 0) | 59 // (((x>>16)&0xff) << 8) | 60 // (((x>> 8)&0xff) << 16) | 61 // (((x>> 0)&0xff) << 24) ); 62 // break; 63 // } 64 // default : 65 // { 66 // break; 67 // } 68 // } 69 // break; 70 // } 71 // case 8 : // 64 bits 72 // { 73 // switch (size_access) 74 // { 75 // case 2 : 76 // { 77 // x = ((((x>> 8)&0xff) << 0) | 78 // (((x>> 0)&0xff) << 8) | 79 // (((x>>24)&0xff) << 16) | 80 // (((x>>16)&0xff) << 24) | 81 // (((x>>40)&0xff) << 32) | 82 // (((x>>32)&0xff) << 40) | 83 // (((x>>56)&0xff) << 48) | 84 // (((x>>48)&0xff) << 56) ); 85 // break; 86 // } 87 // case 4 : 88 // { 89 // x = ((((x>>24)&0xff) << 0) | 90 // (((x>>16)&0xff) << 8) | 91 // (((x>> 8)&0xff) << 16) | 92 // (((x>> 0)&0xff) << 24) | 93 // (((x>>56)&0xff) << 32) | 94 // (((x>>48)&0xff) << 40) | 95 // (((x>>40)&0xff) << 48) | 96 // (((x>>32)&0xff) << 56) ); 97 // break; 98 // } 99 // case 8 : 100 // { 101 // x = ((((x>>56)&0xff) << 0) | 102 // (((x>>48)&0xff) << 8) | 103 // (((x>>40)&0xff) << 16) | 104 // (((x>>32)&0xff) << 24) | 105 // (((x>>24)&0xff) << 32) | 106 // (((x>>16)&0xff) << 40) | 107 // (((x>> 8)&0xff) << 48) | 108 // (((x>> 0)&0xff) << 56) ); 109 // break; 110 // } 111 // default : 112 // { 113 // break; 114 // } 115 // } 116 // break; 117 // } 118 // default : 119 // { 120 // break; 121 // } 122 // } 123 124 125 uint64_t y=0; 126 127 for (uint32_t i=0; i<size_data; i+=size_access) 128 { 129 uint32_t offset = i<<3; 130 131 switch (size_access) 132 { 133 case 1 : 134 { 135 y = x; 136 break; 137 } 138 case 2 : 139 { 140 y |= ((((x>>( 8+offset))&0xff) << ( 0+offset)) | 141 (((x>>( 0+offset))&0xff) << ( 8+offset)) ); 142 break; 143 } 144 case 4 : 145 { 146 y |= ((((x>>(24+offset))&0xff) << ( 0+offset)) | 147 (((x>>(16+offset))&0xff) << ( 8+offset)) | 148 (((x>>( 8+offset))&0xff) << (16+offset)) | 149 (((x>>( 0+offset))&0xff) << (24+offset)) ); 150 break; 151 } 152 case 8 : 153 { 154 y |= ((((x>>(56+offset))&0xff) << ( 0+offset)) | 155 (((x>>(48+offset))&0xff) << ( 8+offset)) | 156 (((x>>(40+offset))&0xff) << (16+offset)) | 157 (((x>>(32+offset))&0xff) << (24+offset)) | 158 (((x>>(24+offset))&0xff) << (32+offset)) | 159 (((x>>(16+offset))&0xff) << (40+offset)) | 160 (((x>>( 8+offset))&0xff) << (48+offset)) | 161 (((x>>( 0+offset))&0xff) << (56+offset)) ); 162 break; 163 } 164 default : 165 { 166 break; 167 } 168 } 169 } 170 171 return static_cast<T>(y); 172 } 173 174 template <typename T> 175 T swapBits (T data, uint32_t size_data, uint32_t size_access) 176 { 177 uint8_t x = static_cast<uint8_t>(data); 178 179 uint8_t y=0; 180 181 for (uint32_t i=0; i<size_data; i+=size_access) 182 { 183 uint32_t offset = i; 184 185 switch (size_access) 186 { 187 case 1 : 188 { 189 y = x; 190 break; 191 } 192 case 2 : 193 { 194 y |= ((((x>>( 1+offset))&0x1) << ( 0+offset)) | 195 (((x>>( 0+offset))&0x1) << ( 1+offset)) ); 196 break; 197 } 198 case 4 : 199 { 200 y |= ((((x>>( 3+offset))&0x1) << ( 0+offset)) | 201 (((x>>( 2+offset))&0x1) << ( 1+offset)) | 202 (((x>>( 1+offset))&0x1) << ( 2+offset)) | 203 (((x>>( 0+offset))&0x1) << ( 3+offset)) ); 204 break; 205 } 206 case 8 : 207 { 208 y |= ((((x>>( 7+offset))&0x1) << ( 0+offset)) | 209 (((x>>( 6+offset))&0x1) << ( 1+offset)) | 210 (((x>>( 5+offset))&0x1) << ( 2+offset)) | 211 (((x>>( 4+offset))&0x1) << ( 3+offset)) | 212 (((x>>( 3+offset))&0x1) << ( 4+offset)) | 213 (((x>>( 2+offset))&0x1) << ( 5+offset)) | 214 (((x>>( 1+offset))&0x1) << ( 6+offset)) | 215 (((x>>( 0+offset))&0x1) << ( 7+offset)) ); 216 break; 217 } 218 default : 219 { 220 break; 221 } 222 } 223 } 224 225 return static_cast<T>(y); 226 } 20 227 21 228 #undef FUNCTION … … 83 290 84 291 log_printf(TRACE,Load_store_unit,FUNCTION," * index_store : %d",index_store); 292 log_printf(TRACE,Load_store_unit,FUNCTION," * ptr_read : %d",reg_STORE_QUEUE_PTR_READ); 293 85 294 if (index_store == reg_STORE_QUEUE_PTR_READ) 86 295 { … … 148 357 149 358 // Read data 150 Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ; 151 Tgeneral_data_t store_data = _store_queue[index_store]._wdata ; 152 153 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (before): 0x%.8x",load_data); 154 log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (before): 0x%.8x",store_data); 359 bool is_big_endian = true; 360 361 Tgeneral_data_t load_data = _load_queue [index_load ]._rdata ; 362 Tgeneral_data_t store_data = _store_queue[index_store]._wdata ; 363 Tdcache_address_t check_hit_byte = _load_queue [index_load ]._check_hit_byte; 364 Tcontrol_t check_hit = _load_queue [index_load ]._check_hit; 365 uint32_t load_size_access = memory_size(_load_queue [index_load ]._operation)>>3; 366 uint32_t store_size_access = memory_size(_store_queue[index_store]._operation)>>3; 367 368 log_printf(TRACE,Load_store_unit,FUNCTION," * is_big_endian : %d",is_big_endian); 369 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data : 0x%.8x",load_data); 370 log_printf(TRACE,Load_store_unit,FUNCTION," * store_data : 0x%.8x",store_data); 371 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte); 372 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %d",check_hit); 373 374 log_printf(TRACE,Load_store_unit,FUNCTION," * load_size_access : %d",load_size_access ); 375 log_printf(TRACE,Load_store_unit,FUNCTION," * store_size_access : %d",store_size_access); 376 377 if (is_big_endian) 378 { 379 // swap in little endian 380 load_data = swapBytes<Tgeneral_data_t >(load_data , _param->_size_general_data>>3,load_size_access); 381 store_data = swapBytes<Tgeneral_data_t >(store_data , _param->_size_general_data>>3,store_size_access); 382 check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access); 383 384 385 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 1) : 0x%.8x",load_data); 386 log_printf(TRACE,Load_store_unit,FUNCTION," * store_data (swap 1) : 0x%.8x",store_data); 387 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 1) : %x",check_hit_byte); 388 } 155 389 156 390 uint32_t store_nb_byte = (1<<memory_access(_store_queue[index_store]._operation)); … … 160 394 uint32_t store_num_byte_max = store_num_byte_min+store_nb_byte; 161 395 162 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_min : %d",store_num_byte_min); 163 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_max : %d",store_num_byte_max); 164 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",_load_queue[index_load]._check_hit); 165 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",_load_queue[index_load]._check_hit_byte); 396 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_min : %d",store_num_byte_min); 397 log_printf(TRACE,Load_store_unit,FUNCTION," * store_num_byte_max : %d",store_num_byte_max); 398 399 // uint32_t load_nb_byte = (1<<memory_access(_load_queue[index_load]._operation)); 400 401 // uint32_t load_num_byte_min = (load_addr & _param->_mask_address_lsb); 402 // uint32_t load_num_byte_max = load_num_byte_min+load_nb_byte; 403 404 // log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_min : %d",load_num_byte_min); 405 // log_printf(TRACE,Load_store_unit,FUNCTION," * load_num_byte_max : %d",load_num_byte_max); 406 407 // for (uint32_t num_load_byte=load_num_byte_min; num_load_byte<load_num_byte_max; num_load_byte ++) 408 // { 409 // // Make a mask 410 // uint32_t num_store_byte = num_load_byte; 411 412 413 166 414 // The bypass is checked byte per byte 167 415 // Is same endianness : because to change endianness, we must write in special register. Also the pipeline is flushed. 168 bool is_big_endian = true;169 170 416 for (uint32_t num_store_byte=store_num_byte_min; num_store_byte<store_num_byte_max; num_store_byte ++) 171 417 { 172 418 // Make a mask 173 uint32_t num_load_byte; 174 175 if (is_big_endian) 176 { 177 // sd 0 : 0 1 2 3 4 5 6 7 178 // ld 0 : 0 1 2 3 4 5 6 7 >> 0 179 // lw 0 : 0 1 2 3 >> 0 -4 180 // lw 4 : 4 5 6 7 >> 32 +4 181 // lh 0 : 0 1 >> 0 -6 182 // lh 2 : 2 3 >> 16 -2 183 // lh 4 : 4 5 >> 32 +2 184 // lh 6 : 6 7 >> 48 +6 185 // lb 0 : 0 >> 0 -7 186 // lb 1 : 1 >> 8 -5 187 // lb 2 : 2 >> 16 -3 188 // lb 3 : 3 >> 24 -1 189 // lb 4 : 4 >> 32 +1 190 // lb 5 : 5 >> 40 +3 191 // lb 6 : 6 >> 48 +5 192 // lb 7 : 7 >> 56 +7 193 194 // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1) 195 196 // store duplicate = all store access can be see as full size_data store 197 uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load ]._operation)); 198 199 // log_printf(TRACE,Load_store_unit,FUNCTION," * num_store_byte : %d",num_store_byte); 200 // log_printf(TRACE,Load_store_unit,FUNCTION," * size_general_data>>3 : %d",(_param->_size_general_data>>3)); 201 // log_printf(TRACE,Load_store_unit,FUNCTION," * load_nb_byte : %d",load_nb_byte); 202 // log_printf(TRACE,Load_store_unit,FUNCTION," * x = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*(num_store_byte/load_nb_byte+1)) = %d+%d-%d*%d = %d" 203 // , (_param->_size_general_data>>3) 204 // , load_nb_byte 205 // , 2*load_nb_byte 206 // ,((num_store_byte/load_nb_byte)+1) 207 // ,((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1))); 419 uint32_t num_load_byte = num_store_byte; 420 421 // if (is_big_endian) 422 // { 423 // // sd 0 : 0 1 2 3 4 5 6 7 424 // // ld 0 : 0 1 2 3 4 5 6 7 >> 0 425 // // lw 0 : 0 1 2 3 >> 0 -4 426 // // lw 4 : 4 5 6 7 >> 32 +4 427 // // lh 0 : 0 1 >> 0 -6 428 // // lh 2 : 2 3 >> 16 -2 429 // // lh 4 : 4 5 >> 32 +2 430 // // lh 6 : 6 7 >> 48 +6 431 // // lb 0 : 0 >> 0 -7 432 // // lb 1 : 1 >> 8 -5 433 // // lb 2 : 2 >> 16 -3 434 // // lb 3 : 3 >> 24 -1 435 // // lb 4 : 4 >> 32 +1 436 // // lb 5 : 5 >> 40 +3 437 // // lb 6 : 6 >> 48 +5 438 // // lb 7 : 7 >> 56 +7 439 440 // // diff : (store_nb_byte + load_nb_byte) - 2*nb_load_byte*((num_store_byte+1) 441 442 // // store duplicate = all store access can be see as full size_data store 443 // // uint32_t load_nb_byte = (1<<memory_access(_load_queue [index_load ]._operation)); 444 445 // // int32_t diff = ((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1)); 446 447 // // num_load_byte =num_store_byte+diff; 448 449 // // log_printf(TRACE,Load_store_unit,FUNCTION," * load_nb_byte : %d",load_nb_byte); 450 // // log_printf(TRACE,Load_store_unit,FUNCTION," * diff : %d",diff); 451 452 453 // num_load_byte = num_store_byte; 454 // } 455 // else 456 // { 457 // // sd 0 : 0 1 2 3 4 5 6 7 458 // // ld 0 : 0 1 2 3 4 5 6 7 >> 0 459 // // lw 0 : 4 5 6 7 >> 0 460 // // lw 4 : 0 1 2 3 >> 32 461 // // lh 0 : 6 7 >> 0 462 // // lh 2 : 4 5 >> 16 463 // // lh 4 : 2 3 >> 32 464 // // lh 6 : 0 1 >> 48 465 // // lb 0 : 7 >> 0 466 // // lb 1 : 6 >> 8 467 // // lb 2 : 5 >> 16 468 // // lb 3 : 4 >> 24 469 // // lb 4 : 3 >> 32 470 // // lb 5 : 2 >> 40 471 // // lb 6 : 1 >> 48 472 // // lb 7 : 0 >> 56 208 473 209 210 num_load_byte =num_store_byte+((_param->_size_general_data>>3)+load_nb_byte-2*load_nb_byte*((num_store_byte/load_nb_byte)+1)); 211 } 212 else 213 { 214 // sd 0 : 0 1 2 3 4 5 6 7 215 // ld 0 : 0 1 2 3 4 5 6 7 >> 0 216 // lw 0 : 4 5 6 7 >> 0 217 // lw 4 : 0 1 2 3 >> 32 218 // lh 0 : 6 7 >> 0 219 // lh 2 : 4 5 >> 16 220 // lh 4 : 2 3 >> 32 221 // lh 6 : 0 1 >> 48 222 // lb 0 : 7 >> 0 223 // lb 1 : 6 >> 8 224 // lb 2 : 5 >> 16 225 // lb 3 : 4 >> 24 226 // lb 4 : 3 >> 32 227 // lb 5 : 2 >> 40 228 // lb 6 : 1 >> 48 229 // lb 7 : 0 >> 56 230 231 num_load_byte = num_store_byte; 232 } 233 474 // num_load_byte = num_store_byte; 475 // } 476 234 477 uint32_t mask = 1<<num_load_byte; 235 478 … … 241 484 // * they have not a previous bypass with an another store 242 485 // * it's a valid request of load 243 if (( _load_queue[index_load]._check_hit_byte&mask)==0)486 if ((check_hit_byte&mask)==0) 244 487 { 245 488 // Note : Store is duplicate = all store access can be see as full size_data store 246 489 247 490 uint32_t num_store_bit_min = num_store_byte<<3; //*8 248 // 491 // uint32_t num_store_bit_max = num_store_bit_min+8-1; 249 492 uint32_t num_load_bit_min = num_load_byte <<3; //*8 250 493 uint32_t num_load_bit_max = num_load_bit_min+8-1; … … 259 502 mask_not<Tdcache_data_t>(load_data,num_load_bit_max,num_load_bit_min)); 260 503 261 _load_queue[index_load]._check_hit_byte |= mask;262 _load_queue[index_load]._check_hit = 1;504 check_hit_byte |= mask; 505 check_hit = 1; 263 506 change_state = true; 264 507 … … 267 510 } 268 511 269 _load_queue[index_load]._rdata = load_data; 512 if (is_big_endian) 513 { 514 // swap in little endian 515 load_data = swapBytes<Tgeneral_data_t >(load_data , _param->_size_general_data>>3,load_size_access); 516 check_hit_byte = swapBits <Tdcache_address_t>(check_hit_byte, _param->_size_general_data>>3,load_size_access); 517 518 519 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (swap 2) : 0x%.8x",load_data); 520 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte (swap 2) : %x",check_hit_byte); 521 } 522 523 _load_queue[index_load]._rdata = load_data; 524 _load_queue[index_load]._check_hit_byte = check_hit_byte; 525 _load_queue[index_load]._check_hit = check_hit; 526 270 527 log_printf(TRACE,Load_store_unit,FUNCTION," * load_data (after) : 0x%.8x",load_data); 271 528 272 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x", _load_queue[index_load]._check_hit);273 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x", _load_queue[index_load]._check_hit_byte);529 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit : %x",check_hit); 530 log_printf(TRACE,Load_store_unit,FUNCTION," * check_hit_byte : %x",check_hit_byte); 274 531 275 532 log_printf(TRACE,Load_store_unit,FUNCTION," * mask_end_check : %x",(-1& _param->_mask_address_lsb)); … … 295 552 { 296 553 log_printf(TRACE,Load_store_unit,FUNCTION," * next"); 554 log_printf(TRACE,Load_store_unit,FUNCTION," * new store_queue_ptr_write : %d",index_store); 297 555 // if (_load_queue[index_load]._store_queue_ptr_write == 0) 298 556 // _load_queue[index_load]._store_queue_ptr_write = _param->_size_store_queue-1; … … 312 570 { 313 571 log_printf(TRACE,Load_store_unit,FUNCTION," * change_state"); 572 log_printf(TRACE,Load_store_unit,FUNCTION," * end_check : %d",end_check); 573 574 log_printf(TRACE,Load_store_unit,FUNCTION," * state old : %s",toString(_load_queue[index_load]._state).c_str()); 314 575 315 576 switch (_load_queue[index_load]._state) 316 577 { 317 case LOAD_QUEUE_WAIT_CHECK : _load_queue[index_load]._state = LOAD_QUEUE_WAIT ; break; 578 case LOAD_QUEUE_WAIT_CHECK : 579 { 580 if (end_check) 581 _load_queue[index_load]._state = LOAD_QUEUE_WAIT ; 582 break; 583 } 318 584 case LOAD_QUEUE_COMMIT_CHECK : 319 585 { … … 321 587 _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; 322 588 else 323 _load_queue[index_load]._state = LOAD_QUEUE_CHECK; 589 _load_queue[index_load]._state = LOAD_QUEUE_CHECK; // No commit : check hit and no end 324 590 break; 325 591 } … … 328 594 if (end_check) 329 595 _load_queue[index_load]._state = LOAD_QUEUE_COMMIT; 596 330 597 // check find a bypass. A speculative load have been committed : report a speculation miss. 331 if (_load_queue[index_load]._check_hit != 0) 598 if ((_load_queue[index_load]._check_hit != 0)// and 599 // (_load_queue[index_load]._write_rd == 0) 600 ) 332 601 { 333 602 _load_queue[index_load]._exception = EXCEPTION_MEMORY_MISS_SPECULATION; … … 339 608 default : break; 340 609 } 341 log_printf(TRACE,Load_store_unit,FUNCTION," * new state : %d",_load_queue[index_load]._state);610 log_printf(TRACE,Load_store_unit,FUNCTION," * state new : %s",toString(_load_queue[index_load]._state).c_str()); 342 611 log_printf(TRACE,Load_store_unit,FUNCTION," * exception : %d",_load_queue[index_load]._exception); 343 612 } … … 712 981 713 982 log_printf(TRACE,Load_store_unit,FUNCTION," * original packet_id : %d" , packet_id); 983 log_printf(TRACE,Load_store_unit,FUNCTION," * packet_id : %d" , packet_id>>1); 714 984 log_printf(TRACE,Load_store_unit,FUNCTION," * rdata : %.8x", rdata); 715 985 log_printf(TRACE,Load_store_unit,FUNCTION," * error : %d" , error); … … 719 989 packet_id >>= 1; 720 990 721 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD : %d", packet_id);991 log_printf(TRACE,Load_store_unit,FUNCTION," * packet is a LOAD"); 722 992 723 724 993 #ifdef DEBUG_TEST 725 994 if (not have_dcache_rsp(_load_queue [packet_id]._operation)) … … 754 1023 { 755 1024 log_printf(TRACE,Load_store_unit,FUNCTION," * have no bus error."); 756 log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : % d.",_load_queue [packet_id]._state);1025 log_printf(TRACE,Load_store_unit,FUNCTION," * previous state : %s",toString(_load_queue [packet_id]._state).c_str()); 757 1026 758 1027 // FIXME : convention : if bus error, the cache return the fautive address !
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