Ignore:
Timestamp:
Jul 17, 2009, 10:59:05 AM (15 years ago)
Author:
rosiere
Message:

1) Add Vhdl component
2) Inhib VHDL Seltest interface

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_genMealy.cpp

    r134 r135  
    200200                PORT_WRITE(out_DECOD_NUM_REG_RE    [i], _decod_instruction->_num_reg_re    );
    201201                PORT_WRITE(out_DECOD_EXCEPTION_USE [i], _decod_instruction->_exception_use );
    202 //              PORT_WRITE(out_DECOD_EXCEPTION     [i], _decod_instruction->_exception     );
     202                PORT_WRITE(out_DECOD_EXCEPTION     [i], _decod_instruction->_exception     );
    203203
    204204                // Branch predictor can accept : the depth is valid
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