Changeset 135 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_vhdl_body.cpp
- Timestamp:
- Jul 17, 2009, 10:59:05 AM (15 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_vhdl_body.cpp
r81 r135 23 23 { 24 24 log_printf(FUNC,Address_management,FUNCTION,"Begin"); 25 vhdl->set_body (""); 25 26 vhdl->set_body (0,""); 27 vhdl->set_comment(0,"========================================="); 28 vhdl->set_comment(0,"===== CONSTANT =========================="); 29 vhdl->set_comment(0,"========================================="); 30 vhdl->set_body (0,""); 31 vhdl->set_body (0,"internal_EVENT_ACK <= '1';"); 32 vhdl->set_body (0," out_EVENT_ACK <= internal_EVENT_ACK;"); 33 34 vhdl->set_body (0,""); 35 vhdl->set_comment(0,"========================================="); 36 vhdl->set_comment(0,"===== TRANSITION ========================"); 37 vhdl->set_comment(0,"========================================="); 38 vhdl->set_body (0,""); 39 40 vhdl->set_body (0,"TRANSITION : process (in_CLOCK)"); 41 42 vhdl->set_body (0,""); 43 vhdl->set_body (0,"variable var_PC_ACCESS_VAL : "+std_logic(1)+";"); 44 vhdl->set_body (0,"variable var_PC_ACCESS : "+std_logic(_param->_size_instruction_address)+";"); 45 vhdl->set_body (0,"variable var_PC_ACCESS_IS_DS_TAKE : "+std_logic(1)+";"); 46 vhdl->set_body (0,"variable var_PC_ACCESS_INSTRUCTION_ENABLE : Tinstruction_enable;"); 47 if (_param->_have_port_inst_ifetch_ptr) 48 vhdl->set_body (0,"variable var_PC_ACCESS_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); 49 vhdl->set_body (0,"variable var_PC_ACCESS_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); 50 if (_param->_have_port_depth) 51 vhdl->set_body (0,"variable var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); 52 vhdl->set_body (0,""); 53 vhdl->set_body (0,"variable var_PC_CURRENT_VAL : "+std_logic(1)+";"); 54 vhdl->set_body (0,"variable var_PC_CURRENT : "+std_logic(_param->_size_instruction_address)+";"); 55 vhdl->set_body (0,"variable var_PC_CURRENT_IS_DS_TAKE : "+std_logic(1)+";"); 56 vhdl->set_body (0,"variable var_PC_CURRENT_INSTRUCTION_ENABLE : Tinstruction_enable;"); 57 if (_param->_have_port_inst_ifetch_ptr) 58 vhdl->set_body (0,"variable var_PC_CURRENT_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); 59 vhdl->set_body (0,"variable var_PC_CURRENT_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); 60 if (_param->_have_port_depth) 61 vhdl->set_body (0,"variable var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); 62 vhdl->set_body (0,""); 63 vhdl->set_body (0,"variable var_PC_NEXT_VAL : "+std_logic(1)+";"); 64 vhdl->set_body (0,"variable var_PC_NEXT : "+std_logic(_param->_size_instruction_address)+";"); 65 vhdl->set_body (0,"variable var_PC_NEXT_IS_DS_TAKE : "+std_logic(1)+";"); 66 vhdl->set_body (0,"variable var_PC_NEXT_INSTRUCTION_ENABLE : Tinstruction_enable;"); 67 if (_param->_have_port_inst_ifetch_ptr) 68 vhdl->set_body (0,"variable var_PC_NEXT_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); 69 vhdl->set_body (0,"variable var_PC_NEXT_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); 70 if (_param->_have_port_depth) 71 vhdl->set_body (0,"variable var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); 72 vhdl->set_body (0,""); 73 vhdl->set_body (0,"variable var_PC_NEXT_NEXT_VAL : "+std_logic(1)+";"); 74 vhdl->set_body (0,"variable var_PC_NEXT_NEXT : "+std_logic(_param->_size_instruction_address)+";"); 75 vhdl->set_body (0,"variable var_PC_NEXT_NEXT_IS_DS_TAKE : "+std_logic(1)+";"); 76 // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_INSTRUCTION_ENABLE : Tinstruction_enable;"); 77 // if (_param->_have_port_inst_ifetch_ptr) 78 // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_INST_IFETCH_PTR : "+std_logic(_param->_size_inst_ifetch_ptr)+";"); 79 // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_BRANCH_STATE : "+std_logic(_param->_size_branch_state)+";"); 80 // if (_param->_have_port_depth) 81 // vhdl->set_body (0,"variable var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID : "+std_logic(_param->_size_depth)+";"); 82 vhdl->set_body (0,""); 83 vhdl->set_body (0,"begin -- TRANSITION"); 84 vhdl->set_body (1,"if (in_CLOCK'event and in_CLOCK = '1')then"); 85 vhdl->set_body (1,""); 86 vhdl->set_body (2,"if (in_NRESET = '0') then"); 87 vhdl->set_body (3,""); 88 89 { 90 vhdl->set_body (3,"reg_PC_ACCESS_VAL <= '0';"); 91 #ifdef SYSTEMC_VHDL_COMPATIBILITY 92 vhdl->set_body (3,"reg_PC_ACCESS <= "+std_logic_cst(_param->_size_instruction_address,0)+";"); 93 #endif 94 vhdl->set_body (3,"reg_PC_CURRENT_VAL <= '0';"); 95 #ifdef SYSTEMC_VHDL_COMPATIBILITY 96 vhdl->set_body (3,"reg_PC_CURRENT <= "+std_logic_cst(_param->_size_instruction_address,0)+";"); 97 #endif 98 vhdl->set_body (3,"reg_PC_NEXT_VAL <= '1';"); 99 vhdl->set_body (3,"reg_PC_NEXT <= "+std_logic_cst(_param->_size_instruction_address,0x100>>2)+";"); 100 vhdl->set_body (3,"reg_PC_NEXT_IS_DS_TAKE <= '0';"); 101 uint32_t index = reg_PC_NEXT % _param->_nb_instruction; 102 for (uint32_t i=0; i<_param->_nb_instruction; i++) 103 { 104 std::string value = (i != index)?"'0'":"'1'"; 105 vhdl->set_body (3,"reg_PC_NEXT_INSTRUCTION_ENABLE ("+toString(i)+") <= "+value+";"); 106 } 107 if (_param->_have_port_inst_ifetch_ptr) 108 vhdl->set_body (3,"reg_PC_NEXT_INST_IFETCH_PTR <= "+std_logic_cst(_param->_size_inst_ifetch_ptr,0)+";"); 109 vhdl->set_body (3,"reg_PC_NEXT_BRANCH_STATE <= "+std_logic_cst(_param->_size_branch_state ,0)+";"); 110 if (_param->_have_port_depth) 111 vhdl->set_body (3,"reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID <= "+std_logic_cst(_param->_size_depth ,0)+";"); 112 vhdl->set_body (3,"reg_PC_NEXT_NEXT_VAL <= '0';"); 113 #ifdef SYSTEMC_VHDL_COMPATIBILITY 114 vhdl->set_body (3,"reg_PC_NEXT_NEXT <= "+std_logic_cst(_param->_size_instruction_address,0)+";"); 115 #endif 116 } 117 vhdl->set_body (3,""); 118 vhdl->set_body (2,"else"); 119 120 vhdl->set_body (3,"var_PC_ACCESS_VAL := reg_PC_ACCESS_VAL ;"); 121 vhdl->set_body (3,"var_PC_ACCESS := reg_PC_ACCESS ;"); 122 vhdl->set_body (3,"var_PC_ACCESS_IS_DS_TAKE := reg_PC_ACCESS_IS_DS_TAKE ;"); 123 vhdl->set_body (3,"var_PC_ACCESS_INSTRUCTION_ENABLE := reg_PC_ACCESS_INSTRUCTION_ENABLE ;"); 124 if (_param->_have_port_inst_ifetch_ptr) 125 vhdl->set_body (3,"var_PC_ACCESS_INST_IFETCH_PTR := reg_PC_ACCESS_INST_IFETCH_PTR ;"); 126 vhdl->set_body (3,"var_PC_ACCESS_BRANCH_STATE := reg_PC_ACCESS_BRANCH_STATE ;"); 127 if (_param->_have_port_depth) 128 vhdl->set_body (3,"var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID := reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID ;"); 129 vhdl->set_body (3,""); 130 vhdl->set_body (3,"var_PC_CURRENT_VAL := reg_PC_CURRENT_VAL ;"); 131 vhdl->set_body (3,"var_PC_CURRENT := reg_PC_CURRENT ;"); 132 vhdl->set_body (3,"var_PC_CURRENT_IS_DS_TAKE := reg_PC_CURRENT_IS_DS_TAKE ;"); 133 vhdl->set_body (3,"var_PC_CURRENT_INSTRUCTION_ENABLE := reg_PC_CURRENT_INSTRUCTION_ENABLE ;"); 134 if (_param->_have_port_inst_ifetch_ptr) 135 vhdl->set_body (3,"var_PC_CURRENT_INST_IFETCH_PTR := reg_PC_CURRENT_INST_IFETCH_PTR ;"); 136 vhdl->set_body (3,"var_PC_CURRENT_BRANCH_STATE := reg_PC_CURRENT_BRANCH_STATE ;"); 137 if (_param->_have_port_depth) 138 vhdl->set_body (3,"var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID := reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID ;"); 139 vhdl->set_body (3,""); 140 vhdl->set_body (3,"var_PC_NEXT_VAL := reg_PC_NEXT_VAL ;"); 141 vhdl->set_body (3,"var_PC_NEXT := reg_PC_NEXT ;"); 142 vhdl->set_body (3,"var_PC_NEXT_IS_DS_TAKE := reg_PC_NEXT_IS_DS_TAKE ;"); 143 vhdl->set_body (3,"var_PC_NEXT_INSTRUCTION_ENABLE := reg_PC_NEXT_INSTRUCTION_ENABLE ;"); 144 if (_param->_have_port_inst_ifetch_ptr) 145 vhdl->set_body (3,"var_PC_NEXT_INST_IFETCH_PTR := reg_PC_NEXT_INST_IFETCH_PTR ;"); 146 vhdl->set_body (3,"var_PC_NEXT_BRANCH_STATE := reg_PC_NEXT_BRANCH_STATE ;"); 147 if (_param->_have_port_depth) 148 vhdl->set_body (3,"var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID := reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); 149 vhdl->set_body (3,""); 150 vhdl->set_body (3,"var_PC_NEXT_NEXT_VAL := reg_PC_NEXT_NEXT_VAL ;"); 151 vhdl->set_body (3,"var_PC_NEXT_NEXT := reg_PC_NEXT_NEXT ;"); 152 vhdl->set_body (3,"var_PC_NEXT_NEXT_IS_DS_TAKE := reg_PC_NEXT_NEXT_IS_DS_TAKE ;"); 153 // vhdl->set_body (3,"var_PC_NEXT_NEXT_INSTRUCTION_ENABLE := reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE ;"); 154 // if (_param->_have_port_inst_ifetch_ptr) 155 // vhdl->set_body (3,"var_PC_NEXT_NEXT_INST_IFETCH_PTR := reg_PC_NEXT_NEXT_INST_IFETCH_PTR ;"); 156 // vhdl->set_body (3,"var_PC_NEXT_NEXT_BRANCH_STATE := reg_PC_NEXT_NEXT_BRANCH_STATE ;"); 157 // if (_param->_have_port_depth) 158 // vhdl->set_body (3,"var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID := reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); 159 160 { 161 vhdl->set_comment(3,"========================================="); 162 vhdl->set_comment(3,"===== PREDICT ==========================="); 163 vhdl->set_comment(3,"========================================="); 164 165 vhdl->set_body (3,"if ((internal_PREDICT_VAL and in_PREDICT_ACK) = '1') then"); 166 vhdl->set_body (4,"if (var_PC_NEXT_IS_DS_TAKE = '1') then"); 167 if (_param->_have_port_inst_ifetch_ptr) 168 vhdl->set_body (5,"var_PC_CURRENT_INST_IFETCH_PTR := in_PREDICT_INST_IFETCH_PTR;"); 169 vhdl->set_body (5,"var_PC_CURRENT_BRANCH_STATE := in_PREDICT_BRANCH_STATE;"); 170 if (_param->_have_port_depth) 171 vhdl->set_body (5,"var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID := in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;"); 172 vhdl->set_body (5,"else"); 173 if (_param->_have_port_inst_ifetch_ptr) 174 vhdl->set_body (5,"var_PC_NEXT_INST_IFETCH_PTR := in_PREDICT_INST_IFETCH_PTR;"); 175 vhdl->set_body (5,"var_PC_NEXT_BRANCH_STATE := in_PREDICT_BRANCH_STATE;"); 176 if (_param->_have_port_depth) 177 vhdl->set_body (5,"var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID := in_PREDICT_BRANCH_UPDATE_PREDICTION_ID;"); 178 vhdl->set_body (4,"end if;"); 179 180 vhdl->set_body (4,"var_PC_NEXT_NEXT_VAL := '1'; -- address is valid"); 181 vhdl->set_body (4,"var_PC_NEXT_NEXT := in_PREDICT_PC_NEXT;"); 182 vhdl->set_body (4,"var_PC_NEXT_NEXT_IS_DS_TAKE := in_PREDICT_PC_NEXT_IS_DS_TAKE;"); 183 for (uint32_t i=0; i<_param->_nb_instruction; i++) 184 vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := in_PREDICT_"+toString(i)+"_INSTRUCTION_ENABLE;"); 185 186 vhdl->set_body (3,"end if;"); 187 } 188 189 { 190 vhdl->set_comment(3,"========================================="); 191 vhdl->set_comment(3,"===== ADDRESS ==========================="); 192 vhdl->set_comment(3,"========================================="); 193 194 vhdl->set_body (3,"if ((internal_ADDRESS_VAL and in_ADDRESS_ACK) = '1') then"); 195 196 vhdl->set_body (4,"var_PC_ACCESS_VAL := '0'; -- transaction with icache"); 197 198 vhdl->set_body (3,"end if;"); 199 } 200 201 { 202 vhdl->set_comment(3,"========================================="); 203 vhdl->set_comment(3,"===== Shift Register ===================="); 204 vhdl->set_comment(3,"========================================="); 205 206 vhdl->set_body (3,"if ((var_PC_NEXT_NEXT_VAL and var_PC_NEXT_VAL and var_PC_CURRENT_VAL and not var_PC_ACCESS_VAL) = '1') then"); 207 vhdl->set_body (4,"var_PC_ACCESS_VAL := '1'; -- new request"); 208 vhdl->set_body (4,"var_PC_CURRENT_VAL := '0'; -- invalid current"); 209 vhdl->set_body (4,"var_PC_ACCESS := var_PC_CURRENT;"); 210 vhdl->set_body (4,"var_PC_ACCESS_IS_DS_TAKE := var_PC_CURRENT_IS_DS_TAKE;"); 211 if (_param->_have_port_inst_ifetch_ptr) 212 vhdl->set_body (4,"var_PC_ACCESS_INST_IFETCH_PTR := var_PC_CURRENT_INST_IFETCH_PTR;"); 213 vhdl->set_body (4,"var_PC_ACCESS_BRANCH_STATE := var_PC_CURRENT_BRANCH_STATE;"); 214 if (_param->_have_port_depth) 215 vhdl->set_body (4,"var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID := var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID;"); 216 // for (uint32_t i=0; i<_param->_nb_instruction; i++) 217 // vhdl->set_body (4,"var_PC_ACCESS_INSTRUCTION_ENABLE("+toString(i)+") := var_PC_CURRENT_INSTRUCTION_ENABLE("+toString(i)+");"); 218 vhdl->set_body (4,"var_PC_ACCESS_INSTRUCTION_ENABLE := var_PC_CURRENT_INSTRUCTION_ENABLE;"); 219 vhdl->set_body (3,"end if;"); 220 221 vhdl->set_body (3,"if ((var_PC_NEXT_NEXT_VAL and var_PC_NEXT_VAL and not var_PC_CURRENT_VAL) = '1') then"); 222 vhdl->set_body (4,"var_PC_CURRENT_VAL := '1'; -- new request"); 223 vhdl->set_body (4,"var_PC_NEXT_VAL := '0'; -- invalid next"); 224 vhdl->set_body (4,"var_PC_CURRENT := var_PC_NEXT;"); 225 vhdl->set_body (4,"var_PC_CURRENT_IS_DS_TAKE := var_PC_NEXT_IS_DS_TAKE;"); 226 if (_param->_have_port_inst_ifetch_ptr) 227 vhdl->set_body (4,"var_PC_CURRENT_INST_IFETCH_PTR := var_PC_NEXT_INST_IFETCH_PTR;"); 228 vhdl->set_body (4,"var_PC_CURRENT_BRANCH_STATE := var_PC_NEXT_BRANCH_STATE;"); 229 if (_param->_have_port_depth) 230 vhdl->set_body (4,"var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID := var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID;"); 231 // for (uint32_t i=0; i<_param->_nb_instruction; i++) 232 // vhdl->set_body (4,"var_PC_CURRENT_INSTRUCTION_ENABLE("+toString(i)+") := var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+");"); 233 vhdl->set_body (4,"var_PC_CURRENT_INSTRUCTION_ENABLE := var_PC_NEXT_INSTRUCTION_ENABLE;"); 234 vhdl->set_body (3,"end if;"); 235 236 vhdl->set_body (3,"if ((var_PC_NEXT_NEXT_VAL and not var_PC_NEXT_VAL) = '1') then"); 237 vhdl->set_body (4,"var_PC_NEXT_VAL := '1'; -- new request"); 238 vhdl->set_body (4,"var_PC_NEXT_NEXT_VAL := '0'; -- invalid next_next"); 239 vhdl->set_body (4,"var_PC_NEXT := var_PC_NEXT_NEXT;"); 240 vhdl->set_body (4,"var_PC_NEXT_IS_DS_TAKE := var_PC_NEXT_NEXT_IS_DS_TAKE;"); 241 // if (_param->_have_port_inst_ifetch_ptr) 242 // vhdl->set_body (4,"var_PC_NEXT_INST_IFETCH_PTR := var_PC_NEXT_NEXT_INST_IFETCH_PTR;"); 243 // vhdl->set_body (4,"var_PC_NEXT_BRANCH_STATE := var_PC_NEXT_NEXT_BRANCH_STATE;"); 244 // if (_param->_have_port_depth) 245 // vhdl->set_body (4,"var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID := var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID;"); 246 // for (uint32_t i=0; i<_param->_nb_instruction; i++) 247 // vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := var_PC_NEXT_NEXT_INSTRUCTION_ENABLE("+toString(i)+");"); 248 // vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE := var_PC_NEXT_NEXT_INSTRUCTION_ENABLE;"); 249 vhdl->set_body (3,"end if;"); 250 } 251 252 { 253 vhdl->set_comment(3,"========================================="); 254 vhdl->set_comment(3,"===== EVENT ============================="); 255 vhdl->set_comment(3,"========================================="); 256 257 vhdl->set_body (3,"if ((in_EVENT_VAL and internal_EVENT_ACK) = '1') then"); 258 vhdl->set_body (4,"var_PC_ACCESS_VAL := '0';"); 259 vhdl->set_body (4,"var_PC_CURRENT_VAL := '0';"); 260 vhdl->set_body (4,"var_PC_NEXT_VAL := '1';"); 261 vhdl->set_body (4,"var_PC_NEXT := in_EVENT_ADDRESS;"); 262 vhdl->set_body (4,"var_PC_NEXT_IS_DS_TAKE := in_EVENT_IS_DS_TAKE;"); 263 264 if (is_power2(_param->_nb_instruction)) 265 { 266 uint32_t size = log2(_param->_nb_instruction); 267 268 if (size != 0) 269 { 270 std::string range = "var_PC_NEXT"+std_logic_range(size-1,0); 271 272 for (uint32_t i=0; i<_param->_nb_instruction; i++) 273 { 274 vhdl->set_body (4,"if ("+range+" = "+std_logic_cst(size,i)+") then"); 275 vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := '1';"); 276 vhdl->set_body (4,"else"); 277 vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE("+toString(i)+") := '0';"); 278 vhdl->set_body (4,"end if;"); 279 } 280 } 281 else 282 vhdl->set_body (4,"var_PC_NEXT_INSTRUCTION_ENABLE(0) := '1';"); 283 } 284 else 285 { 286 throw ERRORMORPHEO(FUNCTION,_("Not Yet supported, Comming Soon.")); 287 } 288 289 vhdl->set_body (4,"var_PC_NEXT_NEXT_VAL := in_EVENT_ADDRESS_NEXT_VAL;"); 290 vhdl->set_body (4,"var_PC_NEXT_NEXT := in_EVENT_ADDRESS_NEXT;"); 291 vhdl->set_body (4,"var_PC_NEXT_NEXT_IS_DS_TAKE := '0';"); 292 293 vhdl->set_body (3,"end if;"); 294 } 295 296 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 297 vhdl->set_comment(3,"WRITE Register"); 298 vhdl->set_comment(3,"---------------------------------------------------------------------------"); 299 300 vhdl->set_body (3,"reg_PC_ACCESS_VAL <= var_PC_ACCESS_VAL ;"); 301 vhdl->set_body (3,"reg_PC_ACCESS <= var_PC_ACCESS ;"); 302 vhdl->set_body (3,"reg_PC_ACCESS_IS_DS_TAKE <= var_PC_ACCESS_IS_DS_TAKE ;"); 303 vhdl->set_body (3,"reg_PC_ACCESS_INSTRUCTION_ENABLE <= var_PC_ACCESS_INSTRUCTION_ENABLE ;"); 304 if (_param->_have_port_inst_ifetch_ptr) 305 vhdl->set_body (3,"reg_PC_ACCESS_INST_IFETCH_PTR <= var_PC_ACCESS_INST_IFETCH_PTR ;"); 306 vhdl->set_body (3,"reg_PC_ACCESS_BRANCH_STATE <= var_PC_ACCESS_BRANCH_STATE ;"); 307 if (_param->_have_port_depth) 308 vhdl->set_body (3,"reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID <= var_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID ;"); 309 vhdl->set_body (3,""); 310 vhdl->set_body (3,"reg_PC_CURRENT_VAL <= var_PC_CURRENT_VAL ;"); 311 vhdl->set_body (3,"reg_PC_CURRENT <= var_PC_CURRENT ;"); 312 vhdl->set_body (3,"reg_PC_CURRENT_IS_DS_TAKE <= var_PC_CURRENT_IS_DS_TAKE ;"); 313 vhdl->set_body (3,"reg_PC_CURRENT_INSTRUCTION_ENABLE <= var_PC_CURRENT_INSTRUCTION_ENABLE ;"); 314 if (_param->_have_port_inst_ifetch_ptr) 315 vhdl->set_body (3,"reg_PC_CURRENT_INST_IFETCH_PTR <= var_PC_CURRENT_INST_IFETCH_PTR ;"); 316 vhdl->set_body (3,"reg_PC_CURRENT_BRANCH_STATE <= var_PC_CURRENT_BRANCH_STATE ;"); 317 if (_param->_have_port_depth) 318 vhdl->set_body (3,"reg_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID <= var_PC_CURRENT_BRANCH_UPDATE_PREDICTION_ID ;"); 319 vhdl->set_body (3,""); 320 vhdl->set_body (3,"reg_PC_NEXT_VAL <= var_PC_NEXT_VAL ;"); 321 vhdl->set_body (3,"reg_PC_NEXT <= var_PC_NEXT ;"); 322 vhdl->set_body (3,"reg_PC_NEXT_IS_DS_TAKE <= var_PC_NEXT_IS_DS_TAKE ;"); 323 vhdl->set_body (3,"reg_PC_NEXT_INSTRUCTION_ENABLE <= var_PC_NEXT_INSTRUCTION_ENABLE ;"); 324 if (_param->_have_port_inst_ifetch_ptr) 325 vhdl->set_body (3,"reg_PC_NEXT_INST_IFETCH_PTR <= var_PC_NEXT_INST_IFETCH_PTR ;"); 326 vhdl->set_body (3,"reg_PC_NEXT_BRANCH_STATE <= var_PC_NEXT_BRANCH_STATE ;"); 327 if (_param->_have_port_depth) 328 vhdl->set_body (3,"reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID <= var_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); 329 vhdl->set_body (3,""); 330 vhdl->set_body (3,"reg_PC_NEXT_NEXT_VAL <= var_PC_NEXT_NEXT_VAL ;"); 331 vhdl->set_body (3,"reg_PC_NEXT_NEXT <= var_PC_NEXT_NEXT ;"); 332 vhdl->set_body (3,"reg_PC_NEXT_NEXT_IS_DS_TAKE <= var_PC_NEXT_NEXT_IS_DS_TAKE ;"); 333 // vhdl->set_body (3,"reg_PC_NEXT_NEXT_INSTRUCTION_ENABLE <= var_PC_NEXT_NEXT_INSTRUCTION_ENABLE ;"); 334 // if (_param->_have_port_inst_ifetch_ptr) 335 // vhdl->set_body (3,"reg_PC_NEXT_NEXT_INST_IFETCH_PTR <= var_PC_NEXT_NEXT_INST_IFETCH_PTR ;"); 336 // vhdl->set_body (3,"reg_PC_NEXT_NEXT_BRANCH_STATE <= var_PC_NEXT_NEXT_BRANCH_STATE ;"); 337 // if (_param->_have_port_depth) 338 // vhdl->set_body (3,"reg_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID <= var_PC_NEXT_NEXT_BRANCH_UPDATE_PREDICTION_ID ;"); 339 340 341 vhdl->set_body (2,"end if; -- reset"); 342 vhdl->set_body (1,"end if; -- clock"); 343 vhdl->set_body (0,"end process; -- TRANSITION"); 344 345 vhdl->set_comment(0,"========================================="); 346 vhdl->set_comment(0,"===== ADDRESS ==========================="); 347 vhdl->set_comment(0,"========================================="); 348 349 vhdl->set_body (0,"internal_ADDRESS_VAL <= reg_PC_ACCESS_VAL;"); 350 vhdl->set_body (0," out_ADDRESS_VAL <= internal_ADDRESS_VAL;"); 351 352 if (is_power2(_param->_nb_instruction)) 353 { 354 uint32_t size = log2(_param->_nb_instruction); 355 356 vhdl->set_body (0,"out_ADDRESS_INSTRUCTION_ADDRESS <= reg_PC_ACCESS and not "+std_logic_cst(_param->_size_instruction_address,(1<<size)-1)+";"); 357 } 358 else 359 { 360 throw ERRORMORPHEO(FUNCTION,_("Not Yet supported, Comming Soon.")); 361 } 362 363 364 if (_param->_have_port_inst_ifetch_ptr) 365 vhdl->set_body (0,"out_ADDRESS_INST_IFETCH_PTR <= reg_PC_ACCESS_INST_IFETCH_PTR;"); 366 vhdl->set_body (0,"out_ADDRESS_BRANCH_STATE <= reg_PC_ACCESS_BRANCH_STATE;"); 367 if (_param->_have_port_depth) 368 vhdl->set_body (0,"out_ADDRESS_BRANCH_UPDATE_PREDICTION_ID<= reg_PC_ACCESS_BRANCH_UPDATE_PREDICTION_ID;"); 369 for (uint32_t i=0; i<_param->_nb_instruction; i++) 370 vhdl->set_body (0,"out_ADDRESS_"+toString(i)+"_INSTRUCTION_ENABLE <= reg_PC_ACCESS_INSTRUCTION_ENABLE ("+toString(i)+");"); 371 372 vhdl->set_comment(0,"========================================="); 373 vhdl->set_comment(0,"===== PREDICT ==========================="); 374 vhdl->set_comment(0,"========================================="); 375 376 vhdl->set_body (0,"internal_PREDICT_VAL <= not reg_PC_NEXT_NEXT_VAL;"); 377 vhdl->set_body (0," out_PREDICT_VAL <= internal_PREDICT_VAL; "); 378 vhdl->set_body (0,"out_PREDICT_PC_PREVIOUS <= reg_PC_CURRENT; "); 379 vhdl->set_body (0,"out_PREDICT_PC_CURRENT <= reg_PC_NEXT; "); 380 vhdl->set_body (0,"out_PREDICT_PC_CURRENT_IS_DS_TAKE <= reg_PC_NEXT_IS_DS_TAKE;"); 381 26 382 log_printf(FUNC,Address_management,FUNCTION,"End"); 27 383 };
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