Ignore:
Timestamp:
Feb 1, 2011, 9:57:54 PM (13 years ago)
Author:
rosiere
Message:

1) Integration of RegisterFile_Internal_Banked in RegisterFile?
2) Erase "read_write" interface in RegisterFile_Monolithic component
3) Add smith predictor parameters in Load_store_pointer_unit.
4) Fix not statistics flags

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp

    r145 r146  
    2929    for (uint32_t i = 0; i < _param->_nb_port_write; i++)
    3030      vhdl->set_body   (0,"out_WRITE_"+toString(i)+"_ACK <= '1';");
    31     for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
    32       vhdl->set_body   (0,"out_READ_WRITE_"+toString(i)+"_ACK  <= '1';");
    3331
    3432    vhdl->set_body   (0,"");
     
    4745
    4846        vhdl->set_body   (0,"out_READ_"+toString(i)+"_DATA <= reg_DATA ("+str_address+") when in_READ_"+toString(i)+"_VAL = '1' else "+std_logic_others(_param->_size_word,0)+";");
    49       }
    50     for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
    51       {
    52         std::string str_address;
    53         if (_param->_have_port_address)
    54           str_address = "conv_integer(in_READ_WRITE_"+toString(i)+"_ADDRESS)";
    55         else
    56           str_address = "0";
    57         vhdl->set_body   (0,"out_READ_WRITE_"+toString(i)+"_RDATA <= reg_DATA ("+str_address+") when in_READ_WRITE_"+toString(i)+"_VAL = '1' and in_READ_WRITE_"+toString(i)+"_RW = '"+toString(RW_READ)+"' else "+std_logic_others(_param->_size_word,0)+";");
    5847      }
    5948
     
    9281        vhdl->set_body   (2,"end if;");
    9382      }
    94     for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
    95       {
    96         std::string str_address;
    97         if (_param->_have_port_address)
    98           str_address = "conv_integer(in_READ_WRITE_"+toString(i)+"_ADDRESS)";
    99         else
    100           str_address = "0";
    101        
    102         vhdl->set_body   (2,"if (in_READ_WRITE_"+toString(i)+"_VAL = '1' and in_READ_WRITE_"+toString(i)+"_RW = '"+toString(RW_WRITE)+"') then");
    103         vhdl->set_body   (3,"reg_DATA("+str_address+") <= in_READ_WRITE_"+toString(i)+"_WDATA;");
    104         vhdl->set_body   (2,"end if;");
    105       }
    10683
    10784    vhdl->set_body   (1,"end if;");
     
    12299    // for (uint32_t i = 0; i < _param->_nb_port_write; i++)
    123100    //   vhdl->set_body   (0,"out_WRITE_"+toString(i)+"_ACK <= '1';");
    124     // for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
    125     //   vhdl->set_body   (0,"out_READ_WRITE_"+toString(i)+"_ACK  <= '1';");
    126101
    127102    // vhdl->set_body   (0,"");
     
    195170    for (uint32_t i = 0; i < _param->_nb_port_write; i++)
    196171      vhdl->set_body   (1,"out_WRITE_"+toString(i)+"_ACK <= '1';");
    197     for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
    198       vhdl->set_body   (1,"out_READ_WRITE_"+toString(i)+"_ACK  <= '1';");
    199172    vhdl->set_body   (1,"");
    200173    vhdl->set_body   (1," -- Read");
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