Changeset 55 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp
- Timestamp:
- Sep 24, 2007, 2:00:35 PM (17 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/src/test.cpp
r50 r55 7 7 */ 8 8 9 #define NB_ITERATION 329 #define NB_ITERATION 2 10 10 11 11 #include "Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/SelfTest/include/test.h" … … 13 13 14 14 void test (string name, 15 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters param)15 morpheo::behavioural::generic::registerfile::registerfile_monolithic::Parameters * _param) 16 16 { 17 17 cout << "<" << name << "> : Simulation SystemC" << endl; … … 19 19 try 20 20 { 21 cout << param.print(1);22 param.test();21 cout << _param->print(1); 22 _param->test(); 23 23 } 24 24 catch (morpheo::ErrorMorpheo & error) … … 33 33 } 34 34 35 #ifdef STATISTICS 36 morpheo::behavioural::Parameters_Statistics * _param_stat = new morpheo::behavioural::Parameters_Statistics (5,1000); 37 #endif 35 38 RegisterFile_Monolithic * registerfile = new RegisterFile_Monolithic (name.c_str() 36 39 #ifdef STATISTICS 37 , morpheo::behavioural::Parameters_Statistics(5,1000)40 ,_param_stat 38 41 #endif 39 , param);42 ,_param); 40 43 41 44 #ifdef SYSTEMC … … 46 49 sc_signal<Tcontrol_t> NRESET; 47 50 48 sc_signal<Tcontrol_t> READ_VAL [param._nb_port_read]; 49 sc_signal<Tcontrol_t> READ_ACK [param._nb_port_read]; 50 sc_signal<Taddress_t> READ_ADDRESS [param._nb_port_read]; 51 sc_signal<Tdata_t> READ_DATA [param._nb_port_read]; 52 53 sc_signal<Tcontrol_t> WRITE_VAL [param._nb_port_write]; 54 sc_signal<Tcontrol_t> WRITE_ACK [param._nb_port_write]; 55 sc_signal<Taddress_t> WRITE_ADDRESS [param._nb_port_write]; 56 sc_signal<Tdata_t> WRITE_DATA [param._nb_port_write]; 51 sc_signal<Tcontrol_t> READ_VAL [_param->_nb_port_read]; 52 sc_signal<Tcontrol_t> READ_ACK [_param->_nb_port_read]; 53 sc_signal<Taddress_t> READ_ADDRESS [_param->_nb_port_read]; 54 sc_signal<Tdata_t> READ_DATA [_param->_nb_port_read]; 55 56 sc_signal<Tcontrol_t> WRITE_VAL [_param->_nb_port_write]; 57 sc_signal<Tcontrol_t> WRITE_ACK [_param->_nb_port_write]; 58 sc_signal<Taddress_t> WRITE_ADDRESS [_param->_nb_port_write]; 59 sc_signal<Tdata_t> WRITE_DATA [_param->_nb_port_write]; 60 61 sc_signal<Tcontrol_t> READ_WRITE_VAL [_param->_nb_port_read_write]; 62 sc_signal<Tcontrol_t> READ_WRITE_ACK [_param->_nb_port_read_write]; 63 sc_signal<Tcontrol_t> READ_WRITE_RW [_param->_nb_port_read_write]; 64 sc_signal<Taddress_t> READ_WRITE_ADDRESS [_param->_nb_port_read_write]; 65 sc_signal<Tdata_t> READ_WRITE_RDATA [_param->_nb_port_read_write]; 66 sc_signal<Tdata_t> READ_WRITE_WDATA [_param->_nb_port_read_write]; 57 67 58 68 /******************************************************** … … 65 75 (*(registerfile->in_NRESET)) (NRESET); 66 76 67 for (uint32_t i=0; i< param._nb_port_read; i++)77 for (uint32_t i=0; i<_param->_nb_port_read; i++) 68 78 { 69 79 (*(registerfile-> in_READ_VAL [i])) (READ_VAL [i]); … … 72 82 (*(registerfile->out_READ_DATA [i])) (READ_DATA [i]); 73 83 } 74 75 for (uint32_t i=0; i<param._nb_port_write; i++) 84 for (uint32_t i=0; i<_param->_nb_port_write; i++) 76 85 { 77 86 (*(registerfile-> in_WRITE_VAL [i])) (WRITE_VAL [i]); … … 80 89 (*(registerfile-> in_WRITE_DATA [i])) (WRITE_DATA [i]); 81 90 } 91 for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 92 { 93 (*(registerfile-> in_READ_WRITE_VAL [i])) (READ_WRITE_VAL [i]); 94 (*(registerfile->out_READ_WRITE_ACK [i])) (READ_WRITE_ACK [i]); 95 (*(registerfile-> in_READ_WRITE_RW [i])) (READ_WRITE_RW [i]); 96 (*(registerfile-> in_READ_WRITE_ADDRESS [i])) (READ_WRITE_ADDRESS [i]); 97 (*(registerfile-> in_READ_WRITE_WDATA [i])) (READ_WRITE_WDATA [i]); 98 (*(registerfile->out_READ_WRITE_RDATA [i])) (READ_WRITE_RDATA [i]); 99 } 82 100 83 101 cout << "<" << name << "> Start Simulation ............" << endl; … … 92 110 sc_start(0); 93 111 94 for (uint32_t i=0; i< param._nb_port_write; i++)112 for (uint32_t i=0; i<_param->_nb_port_write; i++) 95 113 WRITE_VAL [i] .write (0); 96 97 for (uint32_t i=0; i<param._nb_port_read; i++) 114 for (uint32_t i=0; i<_param->_nb_port_read; i++) 98 115 READ_VAL [i] .write (0); 116 for (uint32_t i=0; i<_param->_nb_port_read_write; i++) 117 READ_WRITE_VAL [i] .write (0); 99 118 100 119 NRESET.write(0); … … 115 134 srand(grain); 116 135 117 Tdata_t tab [ param._nb_word];118 119 for (uint32_t i=0; i< param._nb_word; i++)120 tab[i]= rand()%(1<<( param._size_word-1));136 Tdata_t tab [_param->_nb_word]; 137 138 for (uint32_t i=0; i<_param->_nb_word; i++) 139 tab[i]= rand()%(1<<(_param->_size_word-1)); 121 140 122 141 Taddress_t address_next = 0; 123 142 Taddress_t nb_ack = 0; 124 143 125 while (nb_ack < param._nb_word)144 while (nb_ack < _param->_nb_word) 126 145 { 127 146 cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; 128 147 129 for (uint32_t num_port=0; num_port < param._nb_port_write; num_port ++)130 { 131 if ((address_next < param._nb_word) and148 for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) 149 { 150 if ((address_next < _param->_nb_word) and 132 151 (WRITE_VAL [num_port].read() == 0)) 133 152 { … … 139 158 140 159 // Address can be not a multiple of nb_port_write 141 if (address_next >= param._nb_word) 160 if (address_next >= _param->_nb_word) 161 break; 162 } 163 } 164 165 for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) 166 { 167 if ((address_next < _param->_nb_word) and 168 (READ_WRITE_VAL [num_port].read() == 0)) 169 { 170 cout << "(" << num_port << ") [" << address_next << "] <= " << tab[address_next] << endl; 171 172 READ_WRITE_VAL [num_port] .write(1); 173 READ_WRITE_RW [num_port] .write(RW_WRITE); 174 READ_WRITE_WDATA [num_port] .write(tab[address_next]); 175 READ_WRITE_ADDRESS [num_port] .write(address_next++); 176 177 // Address can be not a multiple of nb_port_write 178 if (address_next >= _param->_nb_word) 142 179 break; 143 180 } … … 147 184 148 185 // reset write_val port 149 for (uint32_t num_port=0; num_port < param._nb_port_write; num_port ++)186 for (uint32_t num_port=0; num_port < _param->_nb_port_write; num_port ++) 150 187 { 151 188 if ((WRITE_ACK [num_port].read() == 1) and … … 156 193 } 157 194 } 195 // reset write_val port 196 for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) 197 { 198 if ((READ_WRITE_ACK [num_port].read() == 1) and 199 (READ_WRITE_VAL [num_port].read() == 1)) 200 { 201 READ_WRITE_VAL [num_port] .write(0); 202 nb_ack ++; 203 } 204 } 158 205 159 206 sc_start(0); … … 165 212 cout << "<" << name << "> 2) Read the RegisterFile (no write)" << endl; 166 213 167 Tdata_t read_address [param._nb_port_read]; 168 169 while (nb_ack < param._nb_word) 214 Tdata_t read_address [_param->_nb_port_read]; 215 Tdata_t read_write_address [_param->_nb_port_read_write]; 216 217 while (nb_ack < _param->_nb_word) 170 218 { 171 219 cout << "cycle : " << static_cast<uint32_t> (sc_simulation_time()) << endl; 172 220 173 for (uint32_t num_port=0; num_port < param._nb_port_read; num_port ++)174 { 175 if ((address_next < param._nb_word) and221 for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) 222 { 223 if ((address_next < _param->_nb_word) and 176 224 (READ_VAL [num_port].read() == 0)) 177 225 { … … 181 229 READ_ADDRESS [num_port].write(read_address [num_port]); 182 230 183 if (address_next >= param._nb_word) 184 break; 185 } 186 } 231 if (address_next >= _param->_nb_word) 232 break; 233 } 234 } 235 236 for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) 237 { 238 if ((address_next < _param->_nb_word) and 239 (READ_WRITE_VAL [num_port].read() == 0)) 240 { 241 read_write_address [num_port] = address_next++; 242 243 READ_WRITE_VAL [num_port].write(1); 244 READ_WRITE_RW [num_port].write(RW_READ); 245 READ_WRITE_ADDRESS [num_port].write(read_write_address [num_port]); 246 247 if (address_next >= _param->_nb_word) 248 break; 249 } 250 } 251 187 252 188 253 sc_start(1); 189 254 190 255 // reset write_val port 191 for (uint32_t num_port=0; num_port < param._nb_port_read; num_port ++)256 for (uint32_t num_port=0; num_port < _param->_nb_port_read; num_port ++) 192 257 { 193 258 if ((READ_ACK [num_port].read() == 1) and … … 199 264 200 265 TEST(Tdata_t,READ_DATA [num_port].read(), tab[read_address [num_port]]); 266 nb_ack ++; 267 } 268 } 269 270 for (uint32_t num_port=0; num_port < _param->_nb_port_read_write; num_port ++) 271 { 272 if ((READ_WRITE_ACK [num_port].read() == 1) and 273 (READ_WRITE_VAL [num_port].read() == 1)) 274 { 275 READ_WRITE_VAL [num_port] .write(0); 276 277 cout << "(" << num_port << ") [" << read_write_address [num_port] << "] => " << READ_WRITE_RDATA [num_port].read() << endl; 278 279 TEST(Tdata_t,READ_WRITE_RDATA [num_port].read(), tab[read_write_address [num_port]]); 201 280 nb_ack ++; 202 281 }
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