Changeset 57 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp

Timestamp:

Sep 28, 2007, 2:58:08 PM (17 years ago)

Author:

rosiere

Message:

• VHDL - RegisterFile_Multi_Banked (only partial_crossbar)
• SystemC - modif Component, interface and co -> ajout du type Tusage_T pour instancier un coposant mais ne demander que le VHDL ou le systemC.
• Séminaire interne

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp (modified) (2 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_partial_crossbar_genMealy_write.cpp

@@ -21 +21 @@
     log_printf(FUNC,RegisterFile_Multi_Banked,"partial_crossbar_genMealy_write","Begin");
 
-    bool write_port_use [_param._nb_bank][_param._nb_port_write_by_bank];
-    for (uint32_t i=0; i<_param._nb_bank; i++)
-      for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
+    bool write_port_use [_param->_nb_bank][_param->_nb_port_write_by_bank];
+    for (uint32_t i=0; i<_param->_nb_bank; i++)
+      for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++)
         write_port_use [i][j]=false;
 
-    for (uint32_t i=0; i<_param._nb_port_write; i++)
+    for (uint32_t i=0; i<_param->_nb_port_write; i++)
       {
         bool val = PORT_READ(in_WRITE_VAL    [i]);
@@ -43 +43 @@
 
 //          // Search loop
-//          for (uint32_t j=0; j<_param._nb_port_write_by_bank; j++)
+//          for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j++)
 //            {
-            uint32_t j = _param._link_port_write_to_bank_write [i];
+            uint32_t j = _param->_link_port_write_to_bank_write [i];
 
                 // find a unbusy port on this bank