Changeset 57 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_declaration.cpp

Timestamp:

Sep 28, 2007, 2:58:08 PM (17 years ago)

Author:

rosiere

Message:

• VHDL - RegisterFile_Multi_Banked (only partial_crossbar)
• SystemC - modif Component, interface and co -> ajout du type Tusage_T pour instancier un coposant mais ne demander que le VHDL ou le systemC.
• Séminaire interne

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_declaration.cpp (modified) (1 diff)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked_vhdl_declaration.cpp

@@ -20 +20 @@
     log_printf(FUNC,RegisterFile_Multi_Banked,"vhdl_declaration","Begin");
 
-    vhdl->set_type   ("Tregfile", "array (" + toString(_param._nb_word_by_bank-1) + " downto 0) of " + std_logic(_param._size_word));
+    for (uint32_t i=0; i<_param->_nb_bank; i++)
+      {
+        for (uint32_t j=0; j<_param->_nb_port_read; j ++)
+          {
+            vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1);
+            vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_ACK" ,1);
+            vhdl->set_signal ("internal_SELECT_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1);
 
-    vhdl->set_type   ("Tbank"   , "array (" + toString(_param._nb_bank)           + " downto 0) of Tregfile");
-
-    vhdl->set_signal ("reg_DATA", "Tbank");
-
-    for (uint32_t i=0; i<_param._nb_bank; i++)
-      {
-        for (uint32_t j=0; j<_param._nb_port_read_by_bank; j ++)
+          }
+        for (uint32_t j=0; j<_param->_nb_port_read_by_bank; j ++)
           {
-            vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_VAL"  ,1);
-            vhdl->set_signal ("internal_READ_"+toString(i)+"_"+toString(j)+"_PORT" ,static_cast<uint32_t>(ceil(log2(_param._nb_port_read))));
+            vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_VAL" ,1);
+            vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ACK"    ,1);
+            vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_ADDRESS",_param->_size_address_by_bank);
+            vhdl->set_signal ("internal_BANK_READ_"+toString(i)+"_"+toString(j)+"_DATA"   ,_param->_size_word);
           }
-        for (uint32_t j=0; j<_param._nb_port_write_by_bank; j ++)
+        for (uint32_t j=0; j<_param->_nb_port_write; j ++)
           {
             vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_VAL" ,1);
-            vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_PORT",static_cast<uint32_t>(ceil(log2(_param._nb_port_write))));
+            vhdl->set_signal ("internal_WRITE_"+toString(i)+"_"+toString(j)+"_ACK" ,1);
+            vhdl->set_signal ("internal_SELECT_WRITE_"+toString(i)+"_"+toString(j)+"_VAL"    ,1);
+          }
+        for (uint32_t j=0; j<_param->_nb_port_write_by_bank; j ++)
+          {
+            vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_VAL"    ,1);
+            vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ACK"    ,1);
+            vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_ADDRESS",_param->_size_address_by_bank);
+            vhdl->set_signal ("internal_BANK_WRITE_"+toString(i)+"_"+toString(j)+"_DATA"   ,_param->_size_word);
           }
       }