Changeset 62 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp

Timestamp:

Dec 4, 2007, 2:31:54 PM (17 years ago)

Author:

rosiere

Message:

Modification en profondeur de Component-port_map.
Compilation ok pour Register_unit ... a tester (systemC et vhdl)

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp (modified) (5 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_function_speculative_load_commit_genMoore.cpp

@@ -28 +28 @@
     // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
-    // Test store and load queue
     Tcontext_t         memory_out_context_id = 0;
     Tpacket_t          memory_out_packet_id  = 0;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-    Toperation_t       memory_out_operation  = 0;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-    Ttype_t            memory_out_type       = 0;
-#endif
     Tcontrol_t         memory_out_write_rd   = 0;
     Tgeneral_address_t memory_out_num_reg_rd = 0;
@@ -47 +40 @@
     internal_MEMORY_OUT_VAL          = 0;
 
-    // TODO : now only store queue
+    // Test store and load queue
+    // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!!
 
     // Test an store must be commited.
-
-    
     if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_COMMIT)
       {
@@ -59 +51 @@
         memory_out_context_id= _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id;
         memory_out_packet_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ;
-#ifdef HAVE_MEMORY_OUT_OPERATION
-        memory_out_operation = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._operation;
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-        memory_out_type      = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._type;
-#endif
 //      memory_out_write_rd  
 //      memory_out_num_reg_rd
@@ -71 +57 @@
       }
 
+    // write output
     PORT_WRITE(out_MEMORY_OUT_VAL       , internal_MEMORY_OUT_VAL);
 
     PORT_WRITE(out_MEMORY_OUT_CONTEXT_ID, memory_out_context_id);
     PORT_WRITE(out_MEMORY_OUT_PACKET_ID , memory_out_packet_id );
-#ifdef HAVE_MEMORY_OUT_OPERATION
-    PORT_WRITE(out_MEMORY_OUT_OPERATION , memory_out_operation );
-#endif
-#ifdef HAVE_MEMORY_OUT_TYPE
-    PORT_WRITE(out_MEMORY_OUT_TYPE      , memory_out_type      );
-#endif
     PORT_WRITE(out_MEMORY_OUT_WRITE_RD  , memory_out_write_rd  );
     PORT_WRITE(out_MEMORY_OUT_NUM_REG_RD, memory_out_num_reg_rd);
@@ -89 +70 @@
     PORT_WRITE(out_MEMORY_OUT_EXCEPTION , memory_out_exception );
 
+    // ~~~~~[ Interface "dache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
+    Tcontext_t        dcache_req_context_id;
+    Tpacket_t         dcache_req_packet_id ;
+    Tdcache_address_t dcache_req_address   ;
+    Tdcache_type_t    dcache_req_type      ;
+    Tcontrol_t        dcache_req_uncached  ;
+    Tdcache_data_t    dcache_req_wdata     ;
+
+    internal_DCACHE_REQ_VAL          = 0;
+
+    // Test store and load queue
+
+    // TODO : il faut d'abord tester si un elment de l'access queue n'est pas commitable !!!!!!!
+
+    // Test an store must be commited.
+    if (_store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._state == STORE_QUEUE_VALID_NO_SPECULATIVE)
+      {
+        internal_DCACHE_REQ_VAL          = 1;
+        internal_DCACHE_REQ_SELECT_QUEUE = SELECT_STORE_QUEUE;
+
+        dcache_req_context_id = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._context_id;
+        dcache_req_packet_id  = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._packet_id ;
+        dcache_req_address    = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._address   ;
+        dcache_req_type       = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._dcache_type;
+        dcache_req_uncached   = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._uncached  ;
+        dcache_req_wdata      = _store_queue [internal_MEMORY_STORE_QUEUE_PTR_READ]._wdata     ;
+      }
+
+    PORT_WRITE(out_DCACHE_REQ_VAL       , internal_DCACHE_REQ_VAL);
+    PORT_WRITE(out_DCACHE_REQ_CONTEXT_ID, dcache_req_context_id);
+    PORT_WRITE(out_DCACHE_REQ_PACKET_ID , dcache_req_packet_id );
+    PORT_WRITE(out_DCACHE_REQ_ADDRESS   , dcache_req_address   );
+    PORT_WRITE(out_DCACHE_REQ_TYPE      , dcache_req_type      );
+    PORT_WRITE(out_DCACHE_REQ_UNCACHED  , dcache_req_uncached  );
+    PORT_WRITE(out_DCACHE_REQ_WDATA     , dcache_req_wdata     );
+    
     log_printf(FUNC,Load_store_unit,FUNCTION,"End");
   };