Changeset 62 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis

Timestamp:

Dec 4, 2007, 2:31:54 PM (17 years ago)

Author:

rosiere

Message:

Modification en profondeur de Component-port_map.
Compilation ok pour Register_unit ... a tester (systemC et vhdl)

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis (modified) (5 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Makefile.Synthesis

@@ -22 +22 @@
                                   $(patsubst $(DIR_CFG_USER)/%.cfg,$(DIR_LOG)/%.fpga.log,$(wildcard $(DIR_CFG_USER)/*.cfg))
 #-----[ Rules ]--------------------------------------------
-.PRECIOUS                       : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.vhdl_sim.log
+.PRECIOUS                       : $(DIR_LOG)/%.vhdl.log $(DIR_LOG)/%.sim.log
 
 vhdl                            : execute $(DIR_WORK)
@@ -36 +36 @@
                                 if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
 
-vhdl_sim                        : vhdl
+sim                             : vhdl
                                 @\
                                 declare -a vhdl_files=($$($(LS) $(DIR_VHDL)/*_Testbench.vhdl));                                         \
-                                declare -a log_files=($${vhdl_files[*]/%.vhdl/.vhdl_sim.log});                                          \
+                                declare -a log_files=($${vhdl_files[*]/%.vhdl/.sim.log});                                               \
                                 if $(TEST) $${#log_files[*]} -ne 0; then $(MAKE) $${log_files[*]/#$(DIR_VHDL)/$(DIR_LOG)}; fi;
 
-fpga                            : vhdl_sim
+fpga                            : sim
                                 @\
                                 $(ECHO) -e "" > $(FPGA_CFG_FILE_LOCAL); \
@@ -54 +54 @@
                                         $(ECHO) -e ""                                     >> $(FPGA_CFG_FILE_LOCAL);                    \
                                 done;                                   \
-                                ($(XILINX_ENV); $(CD) $(FPGA_CFG_FILE_GLOBAL_DIR); ./$(FPGA_CFG_FILE_GLOBAL));                          \
+                                ($(XILINX_ENV); $(CD) $(FPGA_CFG_FILE_GLOBAL_DIR); $(FPGA_CFG_FILE_GLOBAL));                            \
                                 $(MAKE) $(FPGA_LOG_FILES);
 
@@ -67 +67 @@
                                 $(MODELTECH_VLIB) $@;
 
-$(DIR_LOG)/%.vhdl_sim.log       : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log
+$(DIR_LOG)/%.sim.log            : $(DIR_VHDL)/%.vhdl $(DIR_LOG)/%.vhdl.log
                                 @\
                                 $(ECHO) "VHDL's Simulation  : $*"; \
@@ -92 +92 @@
                                 $(ECHO) "";\
                                 $(ECHO) " * vhdl                 : compile all vhdl's file";\
-                                $(ECHO) " * vhdl_sim             : simulate all testbench's file";\
+                                $(ECHO) " * sim                  : simulate all testbench's file";\
                                 $(ECHO) " * fpga                 : synthetis with fpga's tools";\
                                 $(ECHO) "";