Ignore:
Timestamp:
Dec 4, 2007, 2:31:54 PM (17 years ago)
Author:
rosiere
Message:

Modification en profondeur de Component-port_map.
Compilation ok pour Register_unit ... a tester (systemC et vhdl)

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/src/Signal.cpp

    r44 r62  
    2222    log_printf(FUNC,Behavioural,"Signal","Begin");
    2323    _is_allocate   = false;
    24     _is_map        = false;
     24    _is_map_as_src = false;
     25    _is_map_as_dest= false;
    2526    _connect_from_signal = NULL;
    2627    _connect_to_signal   = NULL;
     
    4142  {
    4243    log_printf(FUNC,Behavioural,"Signal (copy)","Begin");
    43     _is_allocate= signal._is_allocate;
    44     _is_map     = signal._is_map    ;
     44    _is_allocate    = signal._is_allocate;
     45    _is_map_as_src  = signal._is_map_as_src ;
     46    _is_map_as_dest = signal._is_map_as_dest;
    4547    _connect_from_signal = signal._connect_from_signal;
    4648    _connect_to_signal   = signal._connect_to_signal;
    47     _sc_signal     = signal._sc_signal    ;
    48     _sc_signal_map = signal._sc_signal_map;
    49     _type_info  = signal._type_info ;
     49    _sc_signal      = signal._sc_signal    ;
     50    _sc_signal_map  = signal._sc_signal_map;
     51    _type_info      = signal._type_info ;
    5052#ifdef VHDL_TESTBENCH
    51     _list_value = signal._list_value;
     53    _list_value     = signal._list_value;
    5254#endif
    5355    log_printf(FUNC,Behavioural,"Signal (copy)","End");
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