Ignore:
Timestamp:
Dec 6, 2007, 8:57:49 PM (17 years ago)
Author:
rosiere
Message:

Ajout d'un nouveau composant : fifo generic (un port lecture et un port ecriture).

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Multi_Banked/src/RegisterFile_Multi_Banked.cpp

    r62 r67  
    7373    SC_METHOD (transition);
    7474    dont_initialize ();
    75     sensitive_pos << *(in_CLOCK);
     75    sensitive << (*(in_CLOCK)).pos();
    7676
    7777#ifdef SYSTEMCASS_SPECIFIC
     
    8383    SC_METHOD (genMealy_read);
    8484    dont_initialize ();
    85     sensitive_neg << *(in_CLOCK);
     85    sensitive << (*(in_CLOCK)).neg();
    8686    for (uint32_t i=0; i<_param->_nb_port_read; i++)
    8787      {
     
    112112    SC_METHOD (genMealy_write);
    113113    dont_initialize ();
    114     sensitive_neg << *(in_CLOCK);
     114    sensitive<< (*(in_CLOCK)).neg();
    115115    for (uint32_t i=0; i<_param->_nb_port_write; i++)
    116116      {
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