Ignore:
Timestamp:
Jan 19, 2008, 12:09:01 PM (16 years ago)
Author:
rosiere
Message:

Modification of Statisctics
Add a new systemC component : Load_Store_Queue (tested with one benchmark and one configuration). Store don't supported the Data Buss Error (Load is supported)

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_transition.cpp

    r62 r71  
    1717  {
    1818    log_printf(FUNC,RegisterFile,"transition","Begin");
    19 #ifdef STATISTICS
    20     _stat_nb_write = 0;
    21 #endif   
    2219
    2320    for (uint32_t i=0; i<_param->_nb_port_write; i++)
     
    2724          {
    2825#ifdef STATISTICS
    29             _stat_nb_write ++;
     26            (*_stat_nb_write) ++;
    3027#endif   
    3128
     
    4744      {
    4845        // Have a read_write?
    49         if ( (PORT_READ(in_READ_WRITE_VAL[i]) == true) and
    50              (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE))
    51           {
     46        if (PORT_READ(in_READ_WRITE_VAL[i]) == true)
     47          {
     48            if (PORT_READ(in_READ_WRITE_RW [i]) == RW_WRITE)
     49              {
    5250#ifdef STATISTICS
    53             _stat_nb_write ++;
     51                (*_stat_nb_write) ++;
    5452#endif   
    55 
    56             Taddress_t address;
    57             if (_param->_have_port_address)
    58               address = PORT_READ(in_READ_WRITE_ADDRESS[i]);
     53               
     54                Taddress_t address;
     55                if (_param->_have_port_address)
     56                  address = PORT_READ(in_READ_WRITE_ADDRESS[i]);
     57                else
     58                  address = 0;
     59                Tdata_t    data    = PORT_READ(in_READ_WRITE_WDATA  [i]);
     60               
     61                log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));
     62               
     63                // Write in registerFile
     64                REGISTER_WRITE(reg_DATA[address],data);
     65              }
     66#ifdef STATISTICS
    5967            else
    60               address = 0;
    61             Tdata_t    data    = PORT_READ(in_READ_WRITE_WDATA  [i]);
    62            
    63             log_printf(TRACE,RegisterFile,"transition","[%d] <- %.8x",static_cast<uint32_t>(address),static_cast<uint32_t>(data));
    64 
    65             // Write in registerFile
    66             REGISTER_WRITE(reg_DATA[address],data);
    67           }
     68              {
     69                (*_stat_nb_read) ++;
     70              }
     71#endif   
     72          }
    6873      }
    6974
    7075#ifdef STATISTICS
    71     _stat->add(_stat_nb_read,_stat_nb_write);
     76    for (uint32_t i=0; i<_param->_nb_port_read; i++)
     77      if ( PORT_READ(in_READ_VAL [i]) == 1)
     78        (*_stat_nb_read) ++;
    7279#endif   
    7380
    74 #ifdef VHDL_TESTBENCH
    75     vhdl_testbench_transition ();
    76 #endif
     81    end_cycle();
     82
    7783    log_printf(FUNC,RegisterFile,"transition","End");
    7884  };
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