Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (15 years ago)
- File:
-
- 1 edited
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- Unmodified
- Added
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h
r82 r88 90 90 91 91 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 92 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_VAL ;93 public : SC_OUT(Tcontrol_t ) * out_MEMORY_IN_ACK ;94 public : SC_IN (Tcontext_t ) * in_MEMORY_IN_CONTEXT_ID ;95 public : SC_IN (Tcontext_t ) * in_MEMORY_IN_FRONT_END_ID;96 public : SC_IN (Tcontext_t ) * in_MEMORY_IN_OOO_ENGINE_ID;97 public : SC_IN (Tpacket_t ) * in_MEMORY_IN_PACKET_ID ;98 public : SC_IN (Toperation_t ) * in_MEMORY_IN_OPERATION ;99 public : SC_IN (Ttype_t ) * in_MEMORY_IN_TYPE ;100 public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;101 public : SC_IN (Tlsq_ptr_t ) * in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;102 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_HAS_IMMEDIAT;103 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_IMMEDIAT ;// memory address104 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RA ;// memory address105 public : SC_IN (Tgeneral_data_t ) * in_MEMORY_IN_DATA_RB ;// data (store)106 public : SC_IN (Tspecial_data_t ) * in_MEMORY_IN_DATA_RC ;107 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RD ;// = (operation==load)108 public : SC_IN (Tgeneral_address_t) * in_MEMORY_IN_NUM_REG_RD ;// destination (load)109 public : SC_IN (Tcontrol_t ) * in_MEMORY_IN_WRITE_RE ;110 public : SC_IN (Tspecial_address_t) * in_MEMORY_IN_NUM_REG_RE ;92 public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_VAL ;//[nb_inst_memory] 93 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_IN_ACK ;//[nb_inst_memory] 94 public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_CONTEXT_ID ;//[nb_inst_memory] 95 public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_FRONT_END_ID ;//[nb_inst_memory] 96 public : SC_IN (Tcontext_t ) ** in_MEMORY_IN_OOO_ENGINE_ID ;//[nb_inst_memory] 97 public : SC_IN (Tpacket_t ) ** in_MEMORY_IN_PACKET_ID ;//[nb_inst_memory] 98 public : SC_IN (Toperation_t ) ** in_MEMORY_IN_OPERATION ;//[nb_inst_memory] 99 public : SC_IN (Ttype_t ) ** in_MEMORY_IN_TYPE ;//[nb_inst_memory] 100 public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_STORE_QUEUE_PTR_WRITE;//[nb_inst_memory] 101 public : SC_IN (Tlsq_ptr_t ) ** in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ;//[nb_inst_memory] 102 public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_HAS_IMMEDIAT ;//[nb_inst_memory] 103 public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_IMMEDIAT ;//[nb_inst_memory] // memory address 104 public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_DATA_RA ;//[nb_inst_memory] // memory address 105 public : SC_IN (Tgeneral_data_t ) ** in_MEMORY_IN_DATA_RB ;//[nb_inst_memory] // data (store) 106 public : SC_IN (Tspecial_data_t ) ** in_MEMORY_IN_DATA_RC ;//[nb_inst_memory] 107 public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_WRITE_RD ;//[nb_inst_memory] // = (operation==load) 108 public : SC_IN (Tgeneral_address_t) ** in_MEMORY_IN_NUM_REG_RD ;//[nb_inst_memory] // destination (load) 109 public : SC_IN (Tcontrol_t ) ** in_MEMORY_IN_WRITE_RE ;//[nb_inst_memory] 110 public : SC_IN (Tspecial_address_t) ** in_MEMORY_IN_NUM_REG_RE ;//[nb_inst_memory] 111 111 112 112 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 113 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_VAL ;114 public : SC_IN (Tcontrol_t ) * in_MEMORY_OUT_ACK ;115 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_CONTEXT_ID;116 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_FRONT_END_ID;117 public : SC_OUT(Tcontext_t ) * out_MEMORY_OUT_OOO_ENGINE_ID;118 public : SC_OUT(Tpacket_t ) * out_MEMORY_OUT_PACKET_ID ;119 //public : SC_OUT(Toperation_t ) * out_MEMORY_OUT_OPERATION ;120 public : SC_OUT(Ttype_t ) * out_MEMORY_OUT_TYPE ;121 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RD ;// = (operation==load)122 public : SC_OUT(Tgeneral_address_t) * out_MEMORY_OUT_NUM_REG_RD;// destination (load)123 public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_DATA_RD ;// data (load)124 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_WRITE_RE ;125 public : SC_OUT(Tspecial_address_t) * out_MEMORY_OUT_NUM_REG_RE;126 public : SC_OUT(Tspecial_data_t ) * out_MEMORY_OUT_DATA_RE ;127 public : SC_OUT(Texception_t ) * out_MEMORY_OUT_EXCEPTION ;128 public : SC_OUT(Tcontrol_t ) * out_MEMORY_OUT_NO_SEQUENCE;129 public : SC_OUT(Tgeneral_data_t ) * out_MEMORY_OUT_ADDRESS ;113 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_VAL ;//[nb_inst_memory] 114 public : SC_IN (Tcontrol_t ) ** in_MEMORY_OUT_ACK ;//[nb_inst_memory] 115 public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_CONTEXT_ID ;//[nb_inst_memory] 116 public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_FRONT_END_ID ;//[nb_inst_memory] 117 public : SC_OUT(Tcontext_t ) ** out_MEMORY_OUT_OOO_ENGINE_ID ;//[nb_inst_memory] 118 public : SC_OUT(Tpacket_t ) ** out_MEMORY_OUT_PACKET_ID ;//[nb_inst_memory] 119 //public : SC_OUT(Toperation_t ) ** out_MEMORY_OUT_OPERATION ;//[nb_inst_memory] 120 public : SC_OUT(Ttype_t ) ** out_MEMORY_OUT_TYPE ;//[nb_inst_memory] 121 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RD ;//[nb_inst_memory] // = (operation==load) 122 public : SC_OUT(Tgeneral_address_t) ** out_MEMORY_OUT_NUM_REG_RD ;//[nb_inst_memory] // destination (load) 123 public : SC_OUT(Tgeneral_data_t ) ** out_MEMORY_OUT_DATA_RD ;//[nb_inst_memory] // data (load) 124 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_WRITE_RE ;//[nb_inst_memory] 125 public : SC_OUT(Tspecial_address_t) ** out_MEMORY_OUT_NUM_REG_RE ;//[nb_inst_memory] 126 public : SC_OUT(Tspecial_data_t ) ** out_MEMORY_OUT_DATA_RE ;//[nb_inst_memory] 127 public : SC_OUT(Texception_t ) ** out_MEMORY_OUT_EXCEPTION ;//[nb_inst_memory] 128 public : SC_OUT(Tcontrol_t ) ** out_MEMORY_OUT_NO_SEQUENCE ;//[nb_inst_memory] 129 public : SC_OUT(Tgeneral_data_t ) ** out_MEMORY_OUT_ADDRESS ;//[nb_inst_memory] 130 130 131 132 131 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 133 public : SC_OUT(Tcontrol_t ) * out_DCACHE_REQ_VAL ;134 public : SC_IN (Tcontrol_t ) * in_DCACHE_REQ_ACK ;135 public : SC_OUT(Tcontext_t ) * out_DCACHE_REQ_CONTEXT_ID;136 public : SC_OUT(Tpacket_t ) * out_DCACHE_REQ_PACKET_ID ;137 public : SC_OUT(Tdcache_address_t ) * out_DCACHE_REQ_ADDRESS ;138 public : SC_OUT(Tdcache_type_t ) * out_DCACHE_REQ_TYPE ;139 public : SC_OUT(Tdcache_data_t ) * out_DCACHE_REQ_WDATA ;132 public : SC_OUT(Tcontrol_t ) ** out_DCACHE_REQ_VAL ;//[nb_cache_port] 133 public : SC_IN (Tcontrol_t ) ** in_DCACHE_REQ_ACK ;//[nb_cache_port] 134 public : SC_OUT(Tcontext_t ) ** out_DCACHE_REQ_CONTEXT_ID ;//[nb_cache_port] 135 public : SC_OUT(Tpacket_t ) ** out_DCACHE_REQ_PACKET_ID ;//[nb_cache_port] 136 public : SC_OUT(Tdcache_address_t ) ** out_DCACHE_REQ_ADDRESS ;//[nb_cache_port] 137 public : SC_OUT(Tdcache_type_t ) ** out_DCACHE_REQ_TYPE ;//[nb_cache_port] 138 public : SC_OUT(Tdcache_data_t ) ** out_DCACHE_REQ_WDATA ;//[nb_cache_port] 140 139 141 140 // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 142 public : SC_IN (Tcontrol_t ) * in_DCACHE_RSP_VAL ;143 public : SC_OUT(Tcontrol_t ) * out_DCACHE_RSP_ACK ;144 public : SC_IN (Tcontext_t ) * in_DCACHE_RSP_CONTEXT_ID;145 public : SC_IN (Tpacket_t ) * in_DCACHE_RSP_PACKET_ID ;146 public : SC_IN (Tdcache_data_t ) * in_DCACHE_RSP_RDATA ;147 public : SC_IN (Tdcache_error_t ) * in_DCACHE_RSP_ERROR ;141 public : SC_IN (Tcontrol_t ) ** in_DCACHE_RSP_VAL ;//[nb_cache_port] 142 public : SC_OUT(Tcontrol_t ) ** out_DCACHE_RSP_ACK ;//[nb_cache_port] 143 public : SC_IN (Tcontext_t ) ** in_DCACHE_RSP_CONTEXT_ID ;//[nb_cache_port] 144 public : SC_IN (Tpacket_t ) ** in_DCACHE_RSP_PACKET_ID ;//[nb_cache_port] 145 public : SC_IN (Tdcache_data_t ) ** in_DCACHE_RSP_RDATA ;//[nb_cache_port] 146 public : SC_IN (Tdcache_error_t ) ** in_DCACHE_RSP_ERROR ;//[nb_cache_port] 148 147 149 148 // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 150 public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ;151 public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; 152 public : SC_OUT(Tgeneral_address_t) ** out_BYPASS_MEMORY_NUM_REG ;153 public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ;149 public : SC_OUT(Tcontrol_t ) ** out_BYPASS_MEMORY_VAL ; //[nb_bypass_memory] 150 public : SC_OUT(Tcontext_t ) ** out_BYPASS_MEMORY_OOO_ENGINE_ID; //[nb_bypass_memory] 151 public : SC_OUT(Tgeneral_address_t) ** out_BYPASS_MEMORY_NUM_REG ; //[nb_bypass_memory] 152 public : SC_OUT(Tgeneral_data_t ) ** out_BYPASS_MEMORY_DATA ; //[nb_bypass_memory] 154 153 155 154 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ … … 177 176 // signal 178 177 public : Tlsq_ptr_t internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ ; 179 180 private : Tcontrol_t internal_MEMORY_IN_ACK; 181 private : Tcontrol_t internal_MEMORY_OUT_VAL; 178 179 private : Tcontrol_t internal_MEMORY_IN_ACK ; 180 private : uint32_t internal_MEMORY_IN_PORT ; 181 182 private : Tcontrol_t internal_MEMORY_OUT_VAL ; 182 183 private : Tselect_queue_t internal_MEMORY_OUT_SELECT_QUEUE; 183 p ublic : Tlsq_ptr_t internal_MEMORY_OUT_PTR;184 185 private : Tcontrol_t internal_DCACHE_RSP_ACK ;186 private : Tcontrol_t internal_DCACHE_REQ_VAL ;184 private : Tlsq_ptr_t internal_MEMORY_OUT_PTR ; 185 186 private : Tcontrol_t internal_DCACHE_RSP_ACK ; 187 private : Tcontrol_t internal_DCACHE_REQ_VAL ; 187 188 private : Tselect_queue_t internal_DCACHE_REQ_SELECT_QUEUE; 188 189 #endif
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