Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (15 years ago)
- File:
-
- 1 edited
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trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/src/Load_store_unit_allocation.cpp
r82 r88 3 3 * $Id$ 4 4 * 5 * [ 5 * [ Description ] 6 6 * 7 7 */ 8 8 9 9 #include "Behavioural/Core/Multi_Execute_loop/Execute_loop/Multi_Execute_unit/Execute_unit/Load_store_unit/include/Load_store_unit.h" 10 #include "Behavioural/include/Allocation.h" 10 11 11 12 namespace morpheo { … … 37 38 _interfaces = entity->set_interfaces(); 38 39 39 // ~~~~~[ 40 // ~~~~~[ Interface : "" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 40 41 { 41 42 Interface * interface = _interfaces->set_interface("" … … 43 44 ,IN 44 45 ,SOUTH, 45 "Generalist interface"46 _("Generalist interface") 46 47 #endif 47 48 ); … … 50 51 in_NRESET = interface->set_signal_in <Tcontrol_t> ("nreset",1, RESET_VHDL_YES); 51 52 } 52 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 53 54 // ~~~~~[ Interface "memory_in" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 53 55 { 54 Interface_fifo * interface = _interfaces->set_interface("memory_in" 55 #ifdef POSITION 56 ,IN 57 ,WEST 58 ,"Instruction from Reservations station" 59 #endif 60 ); 56 ALLOC1_INTERFACE("memory_in",IN,WEST,_("Instruction from Reservations station"),_param->_nb_inst_memory); 61 57 62 in_MEMORY_IN_VAL = interface->set_signal_valack_in (VAL); 63 out_MEMORY_IN_ACK = interface->set_signal_valack_out (ACK); 64 65 if (_param->_have_port_context_id) 66 in_MEMORY_IN_CONTEXT_ID = interface->set_signal_in <Tcontext_t > ("context_id" ,_param->_size_context_id ); 67 if (_param->_have_port_front_end_id) 68 in_MEMORY_IN_FRONT_END_ID = interface->set_signal_in <Tcontext_t > ("front_end_id" ,_param->_size_front_end_id ); 69 if (_param->_have_port_ooo_engine_id) 70 in_MEMORY_IN_OOO_ENGINE_ID = interface->set_signal_in <Tcontext_t > ("ooo_engine_id",_param->_size_ooo_engine_id ); 71 if (_param->_have_port_packet_id) 72 in_MEMORY_IN_PACKET_ID = interface->set_signal_in <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 73 in_MEMORY_IN_OPERATION = interface->set_signal_in <Toperation_t > ("operation" ,_param->_size_operation ); 74 in_MEMORY_IN_TYPE = interface->set_signal_in <Ttype_t > ("type" ,_param->_size_type ); 75 in_MEMORY_IN_STORE_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("store_queue_ptr_write" ,_param->_size_address_store_queue+1); // +1 cf load_queue usage 76 if (_param->_have_port_load_queue_ptr) 77 in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE = interface->set_signal_in <Tlsq_ptr_t > ("load_queue_ptr_write" ,_param->_size_address_load_queue ); 78 in_MEMORY_IN_HAS_IMMEDIAT = interface->set_signal_in <Tcontrol_t > ("has_immediat",1 ); 79 in_MEMORY_IN_IMMEDIAT = interface->set_signal_in <Tgeneral_data_t > ("immediat" ,_param->_size_general_data ); 80 in_MEMORY_IN_DATA_RA = interface->set_signal_in <Tgeneral_data_t > ("data_ra" ,_param->_size_general_data ); 81 in_MEMORY_IN_DATA_RB = interface->set_signal_in <Tgeneral_data_t > ("data_rb" ,_param->_size_general_data ); 82 in_MEMORY_IN_DATA_RC = interface->set_signal_in <Tspecial_data_t > ("data_rc" ,_param->_size_special_data ); 83 in_MEMORY_IN_WRITE_RD = interface->set_signal_in <Tcontrol_t > ("write_rd" ,1 ); 84 in_MEMORY_IN_NUM_REG_RD = interface->set_signal_in <Tgeneral_address_t> ("num_reg_rd" ,1 ); 85 in_MEMORY_IN_WRITE_RE = interface->set_signal_in <Tcontrol_t > ("write_re" ,1 ); 86 in_MEMORY_IN_NUM_REG_RE = interface->set_signal_in <Tspecial_address_t> ("num_reg_re" ,1 ); 58 ALLOC1_VALACK_IN ( in_MEMORY_IN_VAL ,VAL); 59 ALLOC1_VALACK_OUT(out_MEMORY_IN_ACK ,ACK); 60 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 61 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 62 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OOO_ENGINE_ID ,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); 63 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 64 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 65 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 66 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_STORE_QUEUE_PTR_WRITE,"store_queue_ptr_write",Tlsq_ptr_t ,_param->_size_store_queue_ptr ); 67 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_LOAD_QUEUE_PTR_WRITE ,"load_queue_ptr_write" ,Tlsq_ptr_t ,_param->_size_load_queue_ptr ); 68 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t ,1 ); 69 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_IMMEDIAT ,"immediat" ,Tgeneral_data_t ,_param->_size_general_data ); 70 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RA ,"data_ra" ,Tgeneral_data_t ,_param->_size_general_data ); 71 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RB ,"data_rb" ,Tgeneral_data_t ,_param->_size_general_data ); 72 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_DATA_RC ,"data_rc" ,Tspecial_data_t ,_param->_size_special_data ); 73 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 74 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,1 ); 75 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 76 ALLOC1_SIGNAL_IN ( in_MEMORY_IN_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,1 ); 87 77 } 88 78 89 // ~~~~~[ 79 // ~~~~~[ Interface "memory_out" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 90 80 { 91 Interface_fifo * interface = _interfaces->set_interface("memory_out" 92 #ifdef POSITION 93 ,OUT 94 ,EAST 95 ,"Instruction to write queue" 96 #endif 97 ); 81 ALLOC1_INTERFACE("memory_out",OUT,EAST,_("Instruction to write queue"),_param->_nb_inst_memory); 98 82 99 out_MEMORY_OUT_VAL = interface->set_signal_valack_out(VAL); 100 in_MEMORY_OUT_ACK = interface->set_signal_valack_in (ACK); 101 if (_param->_have_port_context_id) 102 out_MEMORY_OUT_CONTEXT_ID = interface->set_signal_out <Tcontext_t > ("context_id" ,_param->_size_context_id ); 103 if (_param->_have_port_front_end_id) 104 out_MEMORY_OUT_FRONT_END_ID = interface->set_signal_out <Tcontext_t > ("front_end_id" ,_param->_size_front_end_id ); 105 if (_param->_have_port_ooo_engine_id) 106 out_MEMORY_OUT_OOO_ENGINE_ID = interface->set_signal_out <Tcontext_t > ("ooo_engine_id" ,_param->_size_ooo_engine_id ); 107 if (_param->_have_port_packet_id) 108 out_MEMORY_OUT_PACKET_ID = interface->set_signal_out <Tpacket_t > ("packet_id" ,_param->_size_packet_id ); 109 // out_MEMORY_OUT_OPERATION = interface->set_signal_out <Toperation_t > ("operation" ,_param->_size_operation ); 110 out_MEMORY_OUT_TYPE = interface->set_signal_out <Ttype_t > ("type" ,_param->_size_type ); 111 out_MEMORY_OUT_WRITE_RD = interface->set_signal_out <Tcontrol_t > ("write_rd" ,1 ); 112 out_MEMORY_OUT_NUM_REG_RD = interface->set_signal_out <Tgeneral_address_t> ("num_reg_rd" ,_param->_size_general_register ); 113 out_MEMORY_OUT_DATA_RD = interface->set_signal_out <Tgeneral_data_t > ("data_rd" ,_param->_size_general_data ); 114 out_MEMORY_OUT_WRITE_RE = interface->set_signal_out <Tcontrol_t > ("write_re" ,1 ); 115 out_MEMORY_OUT_NUM_REG_RE = interface->set_signal_out <Tspecial_address_t> ("num_reg_re" ,_param->_size_general_register ); 116 out_MEMORY_OUT_DATA_RE = interface->set_signal_out <Tspecial_data_t > ("data_re" ,_param->_size_general_data ); 117 out_MEMORY_OUT_EXCEPTION = interface->set_signal_out <Texception_t > ("exception" ,_param->_size_exception ); 118 out_MEMORY_OUT_NO_SEQUENCE = interface->set_signal_out <Tcontrol_t > ("no_sequence" ,1 ); 119 out_MEMORY_OUT_ADDRESS = interface->set_signal_out <Tgeneral_data_t > ("address" ,_param->_size_general_data ); 83 ALLOC1_VALACK_OUT(out_MEMORY_OUT_VAL ,VAL); 84 ALLOC1_VALACK_IN ( in_MEMORY_OUT_ACK ,ACK); 85 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_CONTEXT_ID ,"context_id" ,Tcontext_t ,_param->_size_context_id ); 86 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_FRONT_END_ID ,"front_end_id" ,Tcontext_t ,_param->_size_front_end_id ); 87 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OOO_ENGINE_ID,"ooo_engine_id" ,Tcontext_t ,_param->_size_ooo_engine_id ); 88 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_rob_ptr ); 89 // ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_OPERATION ,"operation" ,Toperation_t ,_param->_size_operation ); 90 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_TYPE ,"type" ,Ttype_t ,_param->_size_type ); 91 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RD ,"write_rd" ,Tcontrol_t ,1 ); 92 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RD ,"num_reg_rd" ,Tgeneral_address_t,_param->_size_general_register ); 93 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RD ,"data_rd" ,Tgeneral_data_t ,_param->_size_general_data ); 94 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_WRITE_RE ,"write_re" ,Tcontrol_t ,1 ); 95 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NUM_REG_RE ,"num_reg_re" ,Tspecial_address_t,_param->_size_general_register ); 96 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_DATA_RE ,"data_re" ,Tspecial_data_t ,_param->_size_general_data ); 97 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_EXCEPTION ,"exception" ,Texception_t ,_param->_size_exception ); 98 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_NO_SEQUENCE ,"no_sequence" ,Tcontrol_t ,1 ); 99 ALLOC1_SIGNAL_OUT(out_MEMORY_OUT_ADDRESS ,"address" ,Tgeneral_data_t ,_param->_size_general_data ); 120 100 } 121 101 122 // ~~~~~[ 102 // ~~~~~[ Interface "dcache_req" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 123 103 { 124 Interface_fifo * interface = _interfaces->set_interface("dcache_req" 125 #ifdef POSITION 126 ,OUT 127 ,NORTH 128 ,"Request port to dcache" 129 #endif 130 ); 104 ALLOC1_INTERFACE("dcache_req",OUT,NORTH,_("Request port to dcache"),_param->_nb_cache_port); 131 105 132 out_DCACHE_REQ_VAL = interface->set_signal_valack_out(VAL); 133 in_DCACHE_REQ_ACK = interface->set_signal_valack_in (ACK); 134 if (_param->_have_port_dcache_context_id) 135 out_DCACHE_REQ_CONTEXT_ID = interface->set_signal_out <Tcontext_t > ("context_id",_param->_size_dcache_context_id ); 136 out_DCACHE_REQ_PACKET_ID = interface->set_signal_out <Tpacket_t > ("packet_id" ,_param->_size_dcache_packet_id ); 137 out_DCACHE_REQ_ADDRESS = interface->set_signal_out <Tdcache_address_t > ("address" ,_param->_size_general_data); 138 out_DCACHE_REQ_TYPE = interface->set_signal_out <Tdcache_type_t > ("type" ,_param->_size_dcache_type ); 139 out_DCACHE_REQ_WDATA = interface->set_signal_out <Tdcache_data_t > ("wdata" ,_param->_size_general_data); 106 ALLOC1_VALACK_OUT(out_DCACHE_REQ_VAL ,VAL); 107 ALLOC1_VALACK_IN ( in_DCACHE_REQ_ACK ,ACK); 108 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id ); 109 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id ); 110 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_ADDRESS ,"address" ,Tdcache_address_t,_param->_size_general_data); 111 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_TYPE ,"type" ,Tdcache_type_t ,_param->_size_dcache_type ); 112 ALLOC1_SIGNAL_OUT(out_DCACHE_REQ_WDATA ,"wdata" ,Tdcache_data_t ,_param->_size_general_data); 140 113 } 141 // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 114 115 // ~~~~~[ Interface "dcache_rsp" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 142 116 { 143 Interface_fifo * interface = _interfaces->set_interface("dcache_rsp" 144 #ifdef POSITION 145 ,IN 146 ,NORTH 147 ,"Respons port from dcache" 148 #endif 149 ); 117 ALLOC1_INTERFACE("dcache_rsp",IN,NORTH,_("Respons port from dcache"),_param->_nb_cache_port); 150 118 151 in_DCACHE_RSP_VAL = interface->set_signal_valack_in (VAL); 152 out_DCACHE_RSP_ACK = interface->set_signal_valack_out(ACK); 153 if (_param->_have_port_dcache_context_id) 154 in_DCACHE_RSP_CONTEXT_ID = interface->set_signal_in <Tcontext_t > ("context_id",_param->_size_dcache_context_id ); 155 in_DCACHE_RSP_PACKET_ID = interface->set_signal_in <Tpacket_t > ("packet_id" ,_param->_size_dcache_packet_id ); 156 in_DCACHE_RSP_RDATA = interface->set_signal_in <Tdcache_data_t > ("rdata" ,_param->_size_general_data); 157 in_DCACHE_RSP_ERROR = interface->set_signal_in <Tdcache_error_t> ("error" ,_param->_size_dcache_error); 119 ALLOC1_VALACK_IN ( in_DCACHE_RSP_VAL ,VAL); 120 ALLOC1_VALACK_OUT(out_DCACHE_RSP_ACK ,ACK); 121 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_CONTEXT_ID ,"context_id",Tcontext_t ,_param->_size_dcache_context_id ); 122 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_PACKET_ID ,"packet_id" ,Tpacket_t ,_param->_size_dcache_packet_id ); 123 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_RDATA ,"rdata" ,Tdcache_data_t ,_param->_size_general_data); 124 ALLOC1_SIGNAL_IN ( in_DCACHE_RSP_ERROR ,"error" ,Tdcache_error_t,_param->_size_dcache_error); 158 125 } 159 // ~~~~~[ 126 // ~~~~~[ Interface "bypass_memory" ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 160 127 161 // if (_param->_speculative_load == SPECULATIVE_LOAD_BYPASS) 162 { 163 out_BYPASS_MEMORY_VAL = new SC_OUT(Tcontrol_t ) * [_param->_nb_bypass_memory]; 164 if (_param->_have_port_ooo_engine_id) 165 out_BYPASS_MEMORY_OOO_ENGINE_ID= new SC_OUT(Tcontext_t ) * [_param->_nb_bypass_memory]; 166 out_BYPASS_MEMORY_NUM_REG = new SC_OUT(Tgeneral_address_t) * [_param->_nb_bypass_memory]; 167 out_BYPASS_MEMORY_DATA = new SC_OUT(Tgeneral_data_t ) * [_param->_nb_bypass_memory]; 168 169 for (uint32_t i=0; i<_param->_nb_bypass_memory; i++) 170 { 171 Interface_fifo * interface = _interfaces->set_interface("memory_out" 172 #ifdef POSITION 173 ,OUT 174 ,NORTH 175 ,"Bypass between the load queue and the reservation station" 176 #endif 177 ); 128 { 129 ALLOC1_INTERFACE("bypass_memory",OUT,NORTH,_("Bypass between the load queue and the reservation station"),_param->_nb_bypass_memory); 178 130 179 out_BYPASS_MEMORY_VAL [i] = interface->set_signal_valack_out(VAL); 180 if (_param->_have_port_ooo_engine_id) 181 out_BYPASS_MEMORY_OOO_ENGINE_ID [i] = interface->set_signal_out <Tcontext_t > ("ooo_engine_id", _param->_size_ooo_engine_id); 182 out_BYPASS_MEMORY_NUM_REG [i] = interface->set_signal_out <Tgeneral_address_t> ("num_reg" , _param->_size_general_register); 183 out_BYPASS_MEMORY_DATA [i] = interface->set_signal_out <Tgeneral_data_t > ("data" , _param->_size_general_data); 184 } 185 } 186 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 131 ALLOC1_VALACK_OUT(out_BYPASS_MEMORY_VAL ,VAL); 132 ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_OOO_ENGINE_ID ,"ooo_engine_id",Tcontext_t , _param->_size_ooo_engine_id ); 133 ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_NUM_REG ,"num_reg" ,Tgeneral_address_t, _param->_size_general_register); 134 ALLOC1_SIGNAL_OUT(out_BYPASS_MEMORY_DATA ,"data" ,Tgeneral_data_t , _param->_size_general_data ); 135 } 136 137 // ~~~~~[ Internal ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 138 139 // internal_SPECULATIVE_ACCESS_QUEUE_PTR_READ = new Tlsq_ptr_t [_param->_nb_cache_port]; 140 141 // internal_MEMORY_IN_ACK = new Tcontrol_t [_param->_nb_inst_memory]; 142 // internal_MEMORY_OUT_VAL = new Tcontrol_t [_param->_nb_inst_memory]; 143 // internal_MEMORY_OUT_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_inst_memory]; 144 // internal_MEMORY_OUT_PTR = new Tlsq_ptr_t [_param->_nb_inst_memory]; 145 146 // internal_DCACHE_RSP_ACK = new Tcontrol_t [_param->_nb_cache_port]; 147 // internal_DCACHE_REQ_VAL = new Tcontrol_t [_param->_nb_cache_port]; 148 // internal_DCACHE_REQ_SELECT_QUEUE = new Tselect_queue_t [_param->_nb_cache_port]; 149 150 // ~~~~~[ Component ]~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 187 151 188 152 #ifdef POSITION 189 _component->generate_file(); 153 if (usage_is_set(_usage,USE_POSITION)) 154 _component->generate_file(); 190 155 #endif 191 156
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