Ignore:
Timestamp:
Dec 10, 2008, 7:31:39 PM (15 years ago)
Author:
rosiere
Message:

Almost complete design
with Test and test platform

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Context_State/src/Context_State_genMoore.cpp

    r83 r88  
    2222  {
    2323    log_begin(Context_State,FUNCTION);
     24    log_function(Context_State,FUNCTION,_name.c_str());
    2425
    2526    // -------------------------------------------------------------------
    … …  
    3031        context_state_t state = reg_STATE [i];
    3132
    32         internal_EVENT_VAL [i] = ((state == CONTEXT_STATE_KO_EXCEP_ADDR) or
    33                                   (state == CONTEXT_STATE_KO_MISS_ADDR ) or
    34                                   (state == CONTEXT_STATE_KO_PSYNC_ADDR) or
    35                                   (state == CONTEXT_STATE_KO_CSYNC_ADDR));
    36 
     33        Tcontrol_t val              = ((state == CONTEXT_STATE_KO_EXCEP_ADDR) or
     34                                       (state == CONTEXT_STATE_KO_MISS_ADDR ) or
     35                                       (state == CONTEXT_STATE_KO_PSYNC_ADDR) or
     36                                       (state == CONTEXT_STATE_KO_CSYNC_ADDR));
     37       
     38        // SR can't change in this cycle
     39        // Exception Prefix High
     40        Taddress_t address          = reg_EVENT_ADDRESS [i] | (((state == CONTEXT_STATE_KO_EXCEP_ADDR) and PORT_READ(in_SPR_SR_EPH [i]))?(0xF000000>>2):0);
     41        Taddress_t address_next     = reg_EVENT_ADDRESS_EPCR [i];
     42        Tcontrol_t address_next_val = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]);
     43        Tcontrol_t is_ds_take       = (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]);
    3744        // excep : address exception
    3845        // miss  : address delay_slot, and address dest
    3946        // psync : address next
    4047        // csync : address next
    41         PORT_WRITE(out_EVENT_VAL              [i], internal_EVENT_VAL     [i]);
    42         PORT_WRITE(out_EVENT_ADDRESS          [i], reg_EVENT_ADDRESS      [i]);
    43         PORT_WRITE(out_EVENT_ADDRESS_NEXT     [i], reg_EVENT_ADDRESS_EPCR [i]);
    44         PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_ADDRESS_EPCR_VAL [i]));
    45         PORT_WRITE(out_EVENT_IS_DS_TAKE       [i], (state == CONTEXT_STATE_KO_MISS_ADDR) and (reg_EVENT_IS_DS_TAKE       [i]));
     48        internal_EVENT_VAL [i] = val;
     49        PORT_WRITE(out_EVENT_VAL              [i], val);
     50        PORT_WRITE(out_EVENT_ADDRESS          [i], address);
     51        PORT_WRITE(out_EVENT_ADDRESS_NEXT     [i], address_next);
     52        PORT_WRITE(out_EVENT_ADDRESS_NEXT_VAL [i], address_next_val);
     53        PORT_WRITE(out_EVENT_IS_DS_TAKE       [i], is_ds_take);
     54
     55        log_printf(TRACE,Context_State,FUNCTION,"  * EVENT Context      : %d", i);
     56        log_printf(TRACE,Context_State,FUNCTION,"    * VAL              : %d", val);
     57        log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS          : %.8x (%.8x)", address     , address     <<2);
     58        log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS_NEXT     : %.8x (%.8x)", address_next, address_next<<2);
     59        log_printf(TRACE,Context_State,FUNCTION,"    * ADDRESS_NEXT_VAL : %d", address_next_val);
     60        log_printf(TRACE,Context_State,FUNCTION,"    * IS_DS_TAKE       : %d", is_ds_take);
    4661      }
    4762
    4863    // -------------------------------------------------------------------
    49     // -----[ SPR ]-------------------------------------------------------
     64    // -----[ SPR_EVENT ]-------------------------------------------------
    5065    // -------------------------------------------------------------------
    5166    for (uint32_t i=0; i<_param->_nb_context; i++)
    … …  
    5368        context_state_t state = reg_STATE [i];
    5469
    55         internal_SPR_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR  );
     70        internal_SPR_EVENT_VAL [i] = (state == CONTEXT_STATE_KO_EXCEP_SPR  );
    5671
    57         PORT_WRITE(out_SPR_VAL       [i], internal_SPR_VAL           [i]);
    58         PORT_WRITE(out_SPR_EPCR      [i], reg_EVENT_ADDRESS_EPCR     [i]);
    59         PORT_WRITE(out_SPR_EEAR      [i], reg_EVENT_ADDRESS_EEAR     [i]);
    60         PORT_WRITE(out_SPR_EEAR_WEN  [i], reg_EVENT_ADDRESS_EEAR_VAL [i]);
    61         PORT_WRITE(out_SPR_SR_DSX    [i], reg_EVENT_IS_DELAY_SLOT    [i]);
    62         PORT_WRITE(out_SPR_SR_TO_ESR [i], 1);
     72        PORT_WRITE(out_SPR_EVENT_VAL       [i], internal_SPR_EVENT_VAL     [i]);
     73        PORT_WRITE(out_SPR_EVENT_EPCR      [i], reg_EVENT_ADDRESS_EPCR     [i]);
     74        PORT_WRITE(out_SPR_EVENT_EEAR      [i], reg_EVENT_ADDRESS_EEAR     [i]);
     75        PORT_WRITE(out_SPR_EVENT_EEAR_WEN  [i], reg_EVENT_ADDRESS_EEAR_VAL [i]);
     76        PORT_WRITE(out_SPR_EVENT_SR_DSX    [i], reg_EVENT_IS_DELAY_SLOT    [i]);
     77        PORT_WRITE(out_SPR_EVENT_SR_TO_ESR [i], 1);
    6378      }
    6479
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