Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp
- Timestamp:
- Dec 10, 2008, 7:31:39 PM (15 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/src/Instruction.cpp
r86 r88 14 14 #include "Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/Instruction/include/Instruction.h" 15 15 #include "Behavioural/include/Constants.h" 16 #include "Behavioural/include/Operation.h" 16 17 17 18 namespace morpheo { … … 124 125 125 126 inst->_exception_use = EXCEPTION_USE_ILLEGAL_INSTRUCTION; 127 inst->_exception = EXCEPTION_ILLEGAL_INSTRUCTION; 126 128 127 129 if (inst->_is_delay_slot) … … 138 140 139 141 uint32_t opcod = range<uint32_t>(inst->_instruction,31,26); 140 141 inst->_type = TYPE_CUSTOM; 142 142 143 switch (opcod) 143 144 { 144 case OPCOD_L_CUST1 : {inst->_operation = OPERATION_CUSTOM_L_1; break;} 145 case OPCOD_L_CUST2 : {inst->_operation = OPERATION_CUSTOM_L_2; break;} 146 case OPCOD_L_CUST3 : {inst->_operation = OPERATION_CUSTOM_L_3; break;} 147 case OPCOD_L_CUST4 : {inst->_operation = OPERATION_CUSTOM_L_4; break;} 148 case OPCOD_L_CUST5 : {inst->_operation = OPERATION_CUSTOM_L_5; break;} 149 case OPCOD_L_CUST6 : {inst->_operation = OPERATION_CUSTOM_L_6; break;} 150 case OPCOD_L_CUST7 : {inst->_operation = OPERATION_CUSTOM_L_7; break;} 151 case OPCOD_L_CUST8 : {inst->_operation = OPERATION_CUSTOM_L_8; break;} 145 case OPCOD_L_CUST1 : {inst->_type = instruction_information(INSTRUCTION_L_CUST1)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST1)._operation; break;} 146 case OPCOD_L_CUST2 : {inst->_type = instruction_information(INSTRUCTION_L_CUST2)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST2)._operation; break;} 147 case OPCOD_L_CUST3 : {inst->_type = instruction_information(INSTRUCTION_L_CUST3)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST3)._operation; break;} 148 case OPCOD_L_CUST4 : {inst->_type = instruction_information(INSTRUCTION_L_CUST4)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST4)._operation; break;} 149 case OPCOD_L_CUST5 : {inst->_type = instruction_information(INSTRUCTION_L_CUST5)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST5)._operation; break;} 150 case OPCOD_L_CUST6 : {inst->_type = instruction_information(INSTRUCTION_L_CUST6)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST6)._operation; break;} 151 case OPCOD_L_CUST7 : {inst->_type = instruction_information(INSTRUCTION_L_CUST7)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST7)._operation; break;} 152 case OPCOD_L_CUST8 : {inst->_type = instruction_information(INSTRUCTION_L_CUST8)._type; inst->_operation = instruction_information(INSTRUCTION_L_CUST8)._operation; break;} 153 152 154 default : {throw ERRORMORPHEO("instruction_l_custom",_("Invalid Custom Opcod."));} 153 155 } … … 164 166 uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0); 165 167 166 inst->_type = TYPE_CUSTOM;167 168 switch (opcod) 168 169 { 169 // case OPCOD_LF_CUST1_D : {inst->_ operation = OPERATION_CUSTOM_LF_1_D; break;}170 // case OPCOD_LF_CUST1_S : {inst->_ operation = OPERATION_CUSTOM_LF_1_S; break;}170 // case OPCOD_LF_CUST1_D : {inst->_type = instruction_information(INSTRUCTION_LF_CUST1_D)._type; inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_D)._operation; break;} 171 // case OPCOD_LF_CUST1_S : {inst->_type = instruction_information(INSTRUCTION_LF_CUST1_S)._type; inst->_operation = instruction_information(INSTRUCTION_LF_CUST1_S)._operation; break;} 171 172 default : {throw ERRORMORPHEO("instruction_lf_custom",_("Invalid Custom Opcod."));} 172 173 } … … 183 184 uint32_t opcod = range<uint32_t>(inst->_instruction, 7, 0); 184 185 185 inst->_type = TYPE_CUSTOM;186 186 switch (opcod) 187 187 { 188 // case OPCOD_LV_CUST1 : {inst->_ operation = OPERATION_CUSTOM_LV_1; break;}189 // case OPCOD_LV_CUST2 : {inst->_ operation = OPERATION_CUSTOM_LV_2; break;}190 // case OPCOD_LV_CUST3 : {inst->_ operation = OPERATION_CUSTOM_LV_3; break;}191 // case OPCOD_LV_CUST4 : {inst->_ operation = OPERATION_CUSTOM_LV_4; break;}188 // case OPCOD_LV_CUST1 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST1)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST1)._operation; break;} 189 // case OPCOD_LV_CUST2 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST2)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST2)._operation; break;} 190 // case OPCOD_LV_CUST3 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST3)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST3)._operation; break;} 191 // case OPCOD_LV_CUST4 : {inst->_type = instruction_information(INSTRUCTION_LV_CUST4)._type; inst->_operation = instruction_information(INSTRUCTION_LV_CUST4)._operation; break;} 192 192 default : {throw ERRORMORPHEO("instruction_lv_custom",_("Invalid Custom Opcod."));} 193 193 } … … 252 252 { 253 253 log_printf(TRACE,Decod,"instruction_l_add"," * instruction : l.add"); 254 inst->_type = TYPE_ALU;255 inst->_operation = OPERATION_ALU_L_ADD;254 inst->_type = instruction_information(INSTRUCTION_L_ADD)._type ; //TYPE_ALU; 255 inst->_operation = instruction_information(INSTRUCTION_L_ADD)._operation; //OPERATION_ALU_L_ADD; 256 256 inst->_has_immediat = 0; 257 257 // inst->_immediat = ; … … 267 267 inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; 268 268 inst->_exception_use = EXCEPTION_USE_RANGE; 269 // inst->_branch_condition = ; 270 // inst->_branch_stack_write = ; 271 // inst->_branch_direction = ; 272 // inst->_address_next = ; 269 inst->_exception = EXCEPTION_DECOD_NONE; 270 // inst->_branch_condition = ; 271 // inst->_branch_stack_write = ; 272 // inst->_branch_direction = ; 273 // inst->_address_next = ; 274 inst->_no_execute = 0; 273 275 inst->_event_type = EVENT_TYPE_NONE; 274 276 } … … 278 280 log_printf(TRACE,Decod,"instruction_l_addc"," * instruction : l.addc"); 279 281 280 inst->_type = TYPE_ALU;281 inst->_operation = OPERATION_ALU_L_ADD;282 inst->_type = instruction_information(INSTRUCTION_L_ADDC)._type ; //TYPE_ALU; 283 inst->_operation = instruction_information(INSTRUCTION_L_ADDC)._operation; //OPERATION_ALU_L_ADD; 282 284 inst->_has_immediat = 0; 283 285 // inst->_immediat = ; … … 293 295 inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; 294 296 inst->_exception_use = EXCEPTION_USE_RANGE; 295 // inst->_branch_condition = ; 296 // inst->_branch_stack_write = ; 297 // inst->_branch_direction = ; 298 // inst->_address_next = ; 297 inst->_exception = EXCEPTION_DECOD_NONE; 298 // inst->_branch_condition = ; 299 // inst->_branch_stack_write = ; 300 // inst->_branch_direction = ; 301 // inst->_address_next = ; 302 inst->_no_execute = 0; 299 303 inst->_event_type = EVENT_TYPE_NONE; 300 304 } … … 304 308 log_printf(TRACE,Decod,"instruction_l_addi"," * instruction : l.addi"); 305 309 306 inst->_type = TYPE_ALU;307 inst->_operation = OPERATION_ALU_L_ADD;310 inst->_type = instruction_information(INSTRUCTION_L_ADDI)._type ; //TYPE_ALU; 311 inst->_operation = instruction_information(INSTRUCTION_L_ADDI)._operation; //OPERATION_ALU_L_ADD; 308 312 inst->_has_immediat = 1; 309 313 inst->_immediat = EXTENDS(inst->_instruction,16); … … 319 323 inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; 320 324 inst->_exception_use = EXCEPTION_USE_RANGE; 321 // inst->_branch_condition = ; 322 // inst->_branch_stack_write = ; 323 // inst->_branch_direction = ; 324 // inst->_address_next = ; 325 inst->_exception = EXCEPTION_DECOD_NONE; 326 // inst->_branch_condition = ; 327 // inst->_branch_stack_write = ; 328 // inst->_branch_direction = ; 329 // inst->_address_next = ; 330 inst->_no_execute = 0; 325 331 inst->_event_type = EVENT_TYPE_NONE; 326 332 } … … 330 336 log_printf(TRACE,Decod,"instruction_l_addic"," * instruction : l.addic"); 331 337 332 inst->_type = TYPE_ALU;333 inst->_operation = OPERATION_ALU_L_ADD;338 inst->_type = instruction_information(INSTRUCTION_L_ADDIC)._type ; //TYPE_ALU; 339 inst->_operation = instruction_information(INSTRUCTION_L_ADDIC)._operation; //OPERATION_ALU_L_ADD; 334 340 inst->_has_immediat = 1; 335 341 inst->_immediat = EXTENDS(inst->_instruction,16); … … 345 351 inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; 346 352 inst->_exception_use = EXCEPTION_USE_RANGE; 347 // inst->_branch_condition = ; 348 // inst->_branch_stack_write = ; 349 // inst->_branch_direction = ; 350 // inst->_address_next = ; 353 inst->_exception = EXCEPTION_DECOD_NONE; 354 // inst->_branch_condition = ; 355 // inst->_branch_stack_write = ; 356 // inst->_branch_direction = ; 357 // inst->_address_next = ; 358 inst->_no_execute = 0; 351 359 inst->_event_type = EVENT_TYPE_NONE; 352 360 } … … 356 364 log_printf(TRACE,Decod,"instruction_l_and"," * instruction : l.and"); 357 365 358 inst->_type = TYPE_ALU; 359 inst->_operation = OPERATION_ALU_L_AND; 360 inst->_has_immediat = 0; 361 // inst->_immediat = ; 362 inst->_read_ra = 1; 363 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 364 inst->_read_rb = 1; 365 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 366 inst->_read_rc = 0; 367 // inst->_num_reg_rc = ; 368 inst->_write_rd = 1; 369 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 370 inst->_write_re = 0; 371 // inst->_num_reg_re = ; 372 inst->_exception_use = EXCEPTION_USE_NONE; 373 // inst->_branch_condition = ; 374 // inst->_branch_stack_write = ; 375 // inst->_branch_direction = ; 376 // inst->_address_next = ; 366 inst->_type = instruction_information(INSTRUCTION_L_AND)._type ; //TYPE_ALU; 367 inst->_operation = instruction_information(INSTRUCTION_L_AND)._operation; //OPERATION_ALU_L_AND; 368 inst->_has_immediat = 0; 369 // inst->_immediat = ; 370 inst->_read_ra = 1; 371 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 372 inst->_read_rb = 1; 373 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 374 inst->_read_rc = 0; 375 // inst->_num_reg_rc = ; 376 inst->_write_rd = 1; 377 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 378 inst->_write_re = 0; 379 // inst->_num_reg_re = ; 380 inst->_exception_use = EXCEPTION_USE_NONE; 381 inst->_exception = EXCEPTION_DECOD_NONE; 382 // inst->_branch_condition = ; 383 // inst->_branch_stack_write = ; 384 // inst->_branch_direction = ; 385 // inst->_address_next = ; 386 inst->_no_execute = 0; 377 387 inst->_event_type = EVENT_TYPE_NONE; 378 388 } … … 382 392 log_printf(TRACE,Decod,"instruction_l_andi"," * instruction : l.andi"); 383 393 384 inst->_type = TYPE_ALU;385 inst->_operation = OPERATION_ALU_L_AND;394 inst->_type = instruction_information(INSTRUCTION_L_ANDI)._type ; //TYPE_ALU; 395 inst->_operation = instruction_information(INSTRUCTION_L_ANDI)._operation; //OPERATION_ALU_L_AND; 386 396 inst->_has_immediat = 1; 387 397 inst->_immediat = EXTENDZ(inst->_instruction,16); … … 397 407 // inst->_num_reg_re = ; 398 408 inst->_exception_use = EXCEPTION_USE_NONE; 399 // inst->_branch_condition = ; 400 // inst->_branch_stack_write = ; 401 // inst->_branch_direction = ; 402 // inst->_address_next = ; 409 inst->_exception = EXCEPTION_DECOD_NONE; 410 // inst->_branch_condition = ; 411 // inst->_branch_stack_write = ; 412 // inst->_branch_direction = ; 413 // inst->_address_next = ; 414 inst->_no_execute = 0; 403 415 inst->_event_type = EVENT_TYPE_NONE; 404 416 } … … 408 420 log_printf(TRACE,Decod,"instruction_l_bf"," * instruction : l.bf"); 409 421 410 Tgeneral_data_t address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); 411 412 inst->_type = TYPE_BRANCH; 413 inst->_operation = OPERATION_BRANCH_L_TEST_F; 422 Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 423 ); 424 425 inst->_type = instruction_information(INSTRUCTION_L_BF)._type ; //TYPE_BRANCH; 426 inst->_operation = instruction_information(INSTRUCTION_L_BF)._operation; //OPERATION_BRANCH_L_TEST_F; 414 427 inst->_has_immediat = 1; 415 428 inst->_immediat = address_next; … … 425 438 // inst->_num_reg_re = ; 426 439 inst->_exception_use = EXCEPTION_USE_NONE; 440 inst->_exception = EXCEPTION_DECOD_NONE; 427 441 inst->_branch_condition = BRANCH_CONDITION_FLAG_SET; 428 442 // inst->_branch_stack_write = 0; … … 430 444 inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25); 431 445 inst->_address_next = address_next; 446 inst->_no_execute = 0; 432 447 inst->_event_type = EVENT_TYPE_NONE; 433 448 } … … 437 452 log_printf(TRACE,Decod,"instruction_l_bnf"," * instruction : l.bnf"); 438 453 439 Tgeneral_data_t address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); 440 441 inst->_type = TYPE_BRANCH; 442 inst->_operation = OPERATION_BRANCH_L_TEST_NF; 454 Tgeneral_data_t address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 455 ); 456 457 inst->_type = instruction_information(INSTRUCTION_L_BNF)._type ; //TYPE_BRANCH; 458 inst->_operation = instruction_information(INSTRUCTION_L_BNF)._operation; //OPERATION_BRANCH_L_TEST_NF; 443 459 inst->_has_immediat = 1; 444 460 inst->_immediat = address_next; … … 454 470 // inst->_num_reg_re = ; 455 471 inst->_exception_use = EXCEPTION_USE_NONE; 472 inst->_exception = EXCEPTION_DECOD_NONE; 456 473 inst->_branch_condition = BRANCH_CONDITION_FLAG_UNSET; 457 474 // inst->_branch_stack_write = 0; 458 475 inst->_branch_direction = range<Tgeneral_data_t >(inst->_instruction,25,25); 459 476 inst->_address_next = address_next; 477 inst->_no_execute = 0; 460 478 inst->_event_type = EVENT_TYPE_NONE; 461 479 } … … 465 483 log_printf(TRACE,Decod,"instruction_l_cmov"," * instruction : l.cmov"); 466 484 467 inst->_type = TYPE_MOVE;468 inst->_operation = OPERATION_MOVE_L_CMOV;485 inst->_type = instruction_information(INSTRUCTION_L_CMOV)._type ; //TYPE_MOVE; 486 inst->_operation = instruction_information(INSTRUCTION_L_CMOV)._operation; //OPERATION_MOVE_L_CMOV; 469 487 inst->_has_immediat = 0; 470 488 // inst->_immediat = ; … … 480 498 // inst->_num_reg_re = ; 481 499 inst->_exception_use = EXCEPTION_USE_NONE; 482 // inst->_branch_condition = ; 483 // inst->_branch_stack_write = ; 484 // inst->_branch_direction = ; 485 // inst->_address_next = ; 500 inst->_exception = EXCEPTION_DECOD_NONE; 501 // inst->_branch_condition = ; 502 // inst->_branch_stack_write = ; 503 // inst->_branch_direction = ; 504 // inst->_address_next = ; 505 inst->_no_execute = 0; 486 506 inst->_event_type = EVENT_TYPE_NONE; 487 507 } … … 497 517 else 498 518 { 499 inst->_type = TYPE_SPECIAL;500 inst->_operation = OPERATION_SPECIAL_L_CSYNC;519 inst->_type = instruction_information(INSTRUCTION_L_CSYNC)._type ; //TYPE_SPECIAL; 520 inst->_operation = instruction_information(INSTRUCTION_L_CSYNC)._operation; //OPERATION_SPECIAL_L_CSYNC; 501 521 inst->_has_immediat = 0; 502 522 // inst->_immediat = ; … … 512 532 // inst->_num_reg_re = ; 513 533 inst->_exception_use = EXCEPTION_USE_NONE; 534 inst->_exception = EXCEPTION_DECOD_NONE; 514 535 // inst->_branch_condition = ; 515 536 // inst->_branch_stack_write = ; 516 537 // inst->_branch_direction = ; 517 538 // inst->_address_next = ; // don't change 539 inst->_no_execute = 0; 518 540 inst->_event_type = EVENT_TYPE_CSYNC; 519 541 } … … 533 555 log_printf(TRACE,Decod,"instruction_l_div"," * instruction : l.div"); 534 556 535 inst->_type = TYPE_MUL_DIV;536 inst->_operation = OPERATION_MUL_DIV_L_DIV;557 inst->_type = instruction_information(INSTRUCTION_L_DIV)._type ; //TYPE_DIV; 558 inst->_operation = instruction_information(INSTRUCTION_L_DIV)._operation; //OPERATION_DIV_L_DIV; 537 559 inst->_has_immediat = 0; 538 560 // inst->_immediat = ; … … 548 570 inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; 549 571 inst->_exception_use = EXCEPTION_USE_RANGE; 550 // inst->_branch_condition = ; 551 // inst->_branch_stack_write = ; 552 // inst->_branch_direction = ; 553 // inst->_address_next = ; 572 inst->_exception = EXCEPTION_DECOD_NONE; 573 // inst->_branch_condition = ; 574 // inst->_branch_stack_write = ; 575 // inst->_branch_direction = ; 576 // inst->_address_next = ; 577 inst->_no_execute = 0; 554 578 inst->_event_type = EVENT_TYPE_NONE; 555 579 } … … 559 583 log_printf(TRACE,Decod,"instruction_l_divu"," * instruction : l.divu"); 560 584 561 inst->_type = TYPE_MUL_DIV;562 inst->_operation = OPERATION_MUL_DIV_L_DIVU;585 inst->_type = instruction_information(INSTRUCTION_L_DIVU)._type ; //TYPE_DIV; 586 inst->_operation = instruction_information(INSTRUCTION_L_DIVU)._operation; //OPERATION_DIV_L_DIVU; 563 587 inst->_has_immediat = 0; 564 588 // inst->_immediat = ; … … 574 598 inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; 575 599 inst->_exception_use = EXCEPTION_USE_RANGE; 576 // inst->_branch_condition = ; 577 // inst->_branch_stack_write = ; 578 // inst->_branch_direction = ; 579 // inst->_address_next = ; 600 inst->_exception = EXCEPTION_DECOD_NONE; 601 // inst->_branch_condition = ; 602 // inst->_branch_stack_write = ; 603 // inst->_branch_direction = ; 604 // inst->_address_next = ; 605 inst->_no_execute = 0; 580 606 inst->_event_type = EVENT_TYPE_NONE; 581 607 } … … 585 611 log_printf(TRACE,Decod,"instruction_l_extbs"," * instruction : l.extbs"); 586 612 587 inst->_type = TYPE_EXTEND;588 inst->_operation = OPERATION_EXTEND_L_EXTEND_S;613 inst->_type = instruction_information(INSTRUCTION_L_EXTBS)._type ; //TYPE_EXTEND; 614 inst->_operation = instruction_information(INSTRUCTION_L_EXTBS)._operation; //OPERATION_EXTEND_L_EXTEND_S; 589 615 inst->_has_immediat = 1; 590 616 inst->_immediat = 8; … … 600 626 // inst->_num_reg_re = ; 601 627 inst->_exception_use = EXCEPTION_USE_NONE; 602 // inst->_branch_condition = ; 603 // inst->_branch_stack_write = ; 604 // inst->_branch_direction = ; 605 // inst->_address_next = ; 628 inst->_exception = EXCEPTION_DECOD_NONE; 629 // inst->_branch_condition = ; 630 // inst->_branch_stack_write = ; 631 // inst->_branch_direction = ; 632 // inst->_address_next = ; 633 inst->_no_execute = 0; 606 634 inst->_event_type = EVENT_TYPE_NONE; 607 635 } … … 611 639 log_printf(TRACE,Decod,"instruction_l_extbz"," * instruction : l.extbz"); 612 640 613 inst->_type = TYPE_EXTEND;614 inst->_operation = OPERATION_EXTEND_L_EXTEND_Z;641 inst->_type = instruction_information(INSTRUCTION_L_EXTBZ)._type ; //TYPE_EXTEND; 642 inst->_operation = instruction_information(INSTRUCTION_L_EXTBZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z; 615 643 inst->_has_immediat = 1; 616 644 inst->_immediat = 8; … … 626 654 // inst->_num_reg_re = ; 627 655 inst->_exception_use = EXCEPTION_USE_NONE; 628 // inst->_branch_condition = ; 629 // inst->_branch_stack_write = ; 630 // inst->_branch_direction = ; 631 // inst->_address_next = ; 656 inst->_exception = EXCEPTION_DECOD_NONE; 657 // inst->_branch_condition = ; 658 // inst->_branch_stack_write = ; 659 // inst->_branch_direction = ; 660 // inst->_address_next = ; 661 inst->_no_execute = 0; 632 662 inst->_event_type = EVENT_TYPE_NONE; 633 663 } … … 637 667 log_printf(TRACE,Decod,"instruction_l_exths"," * instruction : l.exths"); 638 668 639 inst->_type = TYPE_EXTEND;640 inst->_operation = OPERATION_EXTEND_L_EXTEND_S;669 inst->_type = instruction_information(INSTRUCTION_L_EXTHS)._type ; //TYPE_EXTEND; 670 inst->_operation = instruction_information(INSTRUCTION_L_EXTHS)._operation; //OPERATION_EXTEND_L_EXTEND_S; 641 671 inst->_has_immediat = 1; 642 672 inst->_immediat = 16; … … 652 682 // inst->_num_reg_re = ; 653 683 inst->_exception_use = EXCEPTION_USE_NONE; 654 // inst->_branch_condition = ; 655 // inst->_branch_stack_write = ; 656 // inst->_branch_direction = ; 657 // inst->_address_next = ; 684 inst->_exception = EXCEPTION_DECOD_NONE; 685 // inst->_branch_condition = ; 686 // inst->_branch_stack_write = ; 687 // inst->_branch_direction = ; 688 // inst->_address_next = ; 689 inst->_no_execute = 0; 658 690 inst->_event_type = EVENT_TYPE_NONE; 659 691 } … … 663 695 log_printf(TRACE,Decod,"instruction_l_exthz"," * instruction : l.exthz"); 664 696 665 inst->_type = TYPE_EXTEND;666 inst->_operation = OPERATION_EXTEND_L_EXTEND_Z;697 inst->_type = instruction_information(INSTRUCTION_L_EXTHZ)._type ; //TYPE_EXTEND; 698 inst->_operation = instruction_information(INSTRUCTION_L_EXTHZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z; 667 699 inst->_has_immediat = 1; 668 700 inst->_immediat = 16; … … 678 710 // inst->_num_reg_re = ; 679 711 inst->_exception_use = EXCEPTION_USE_NONE; 680 // inst->_branch_condition = ; 681 // inst->_branch_stack_write = ; 682 // inst->_branch_direction = ; 683 // inst->_address_next = ; 712 inst->_exception = EXCEPTION_DECOD_NONE; 713 // inst->_branch_condition = ; 714 // inst->_branch_stack_write = ; 715 // inst->_branch_direction = ; 716 // inst->_address_next = ; 717 inst->_no_execute = 0; 684 718 inst->_event_type = EVENT_TYPE_NONE; 685 719 } … … 689 723 log_printf(TRACE,Decod,"instruction_l_extws"," * instruction : l.extws"); 690 724 691 inst->_type = TYPE_EXTEND;692 inst->_operation = OPERATION_EXTEND_L_EXTEND_S;725 inst->_type = instruction_information(INSTRUCTION_L_EXTWS)._type ; //TYPE_EXTEND; 726 inst->_operation = instruction_information(INSTRUCTION_L_EXTWS)._operation; //OPERATION_EXTEND_L_EXTEND_S; 693 727 inst->_has_immediat = 1; 694 728 inst->_immediat = 32; … … 704 738 // inst->_num_reg_re = ; 705 739 inst->_exception_use = EXCEPTION_USE_NONE; 706 // inst->_branch_condition = ; 707 // inst->_branch_stack_write = ; 708 // inst->_branch_direction = ; 709 // inst->_address_next = ; 740 inst->_exception = EXCEPTION_DECOD_NONE; 741 // inst->_branch_condition = ; 742 // inst->_branch_stack_write = ; 743 // inst->_branch_direction = ; 744 // inst->_address_next = ; 745 inst->_no_execute = 0; 710 746 inst->_event_type = EVENT_TYPE_NONE; 711 747 } … … 715 751 log_printf(TRACE,Decod,"instruction_l_extwz"," * instruction : l.extwz"); 716 752 717 inst->_type = TYPE_EXTEND;718 inst->_operation = OPERATION_EXTEND_L_EXTEND_Z;753 inst->_type = instruction_information(INSTRUCTION_L_EXTWZ)._type ; //TYPE_EXTEND; 754 inst->_operation = instruction_information(INSTRUCTION_L_EXTWZ)._operation; //OPERATION_EXTEND_L_EXTEND_Z; 719 755 inst->_has_immediat = 1; 720 756 inst->_immediat = 32; … … 730 766 // inst->_num_reg_re = ; 731 767 inst->_exception_use = EXCEPTION_USE_NONE; 732 // inst->_branch_condition = ; 733 // inst->_branch_stack_write = ; 734 // inst->_branch_direction = ; 735 // inst->_address_next = ; 768 inst->_exception = EXCEPTION_DECOD_NONE; 769 // inst->_branch_condition = ; 770 // inst->_branch_stack_write = ; 771 // inst->_branch_direction = ; 772 // inst->_address_next = ; 773 inst->_no_execute = 0; 736 774 inst->_event_type = EVENT_TYPE_NONE; 737 775 } … … 741 779 log_printf(TRACE,Decod,"instruction_l_ff1"," * instruction : l.ff1"); 742 780 743 inst->_type = TYPE_FIND; 744 inst->_operation = OPERATION_FIND_L_FF1; 745 inst->_has_immediat = 0; 746 // inst->_immediat = ; 747 inst->_read_ra = 1; 748 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 749 inst->_read_rb = 0; 750 // inst->_num_reg_rb = ; 751 inst->_read_rc = 0; 752 // inst->_num_reg_rc = ; 753 inst->_write_rd = 1; 754 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 755 inst->_write_re = 0; 756 // inst->_num_reg_re = ; 757 inst->_exception_use = EXCEPTION_USE_NONE; 758 // inst->_branch_condition = ; 759 // inst->_branch_stack_write = ; 760 // inst->_branch_direction = ; 761 // inst->_address_next = ; 781 inst->_type = instruction_information(INSTRUCTION_L_FF1)._type ; //TYPE_FIND; 782 inst->_operation = instruction_information(INSTRUCTION_L_FF1)._operation; //OPERATION_FIND_L_FF1; 783 inst->_has_immediat = 0; 784 // inst->_immediat = ; 785 inst->_read_ra = 1; 786 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 787 inst->_read_rb = 0; 788 // inst->_num_reg_rb = ; 789 inst->_read_rc = 0; 790 // inst->_num_reg_rc = ; 791 inst->_write_rd = 1; 792 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 793 inst->_write_re = 0; 794 // inst->_num_reg_re = ; 795 inst->_exception_use = EXCEPTION_USE_NONE; 796 inst->_exception = EXCEPTION_DECOD_NONE; 797 // inst->_branch_condition = ; 798 // inst->_branch_stack_write = ; 799 // inst->_branch_direction = ; 800 // inst->_address_next = ; 801 inst->_no_execute = 0; 762 802 inst->_event_type = EVENT_TYPE_NONE; 763 803 } … … 767 807 log_printf(TRACE,Decod,"instruction_l_fl1"," * instruction : l.fl1"); 768 808 769 inst->_type = TYPE_FIND; 770 inst->_operation = OPERATION_FIND_L_FL1; 771 inst->_has_immediat = 0; 772 // inst->_immediat = ; 773 inst->_read_ra = 1; 774 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 775 inst->_read_rb = 0; 776 // inst->_num_reg_rb = ; 777 inst->_read_rc = 0; 778 // inst->_num_reg_rc = ; 779 inst->_write_rd = 1; 780 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 781 inst->_write_re = 0; 782 // inst->_num_reg_re = ; 783 inst->_exception_use = EXCEPTION_USE_NONE; 784 // inst->_branch_condition = ; 785 // inst->_branch_stack_write = ; 786 // inst->_branch_direction = ; 787 // inst->_address_next = ; 809 inst->_type = instruction_information(INSTRUCTION_L_FL1)._type ; //TYPE_FIND; 810 inst->_operation = instruction_information(INSTRUCTION_L_FL1)._operation; //OPERATION_FIND_L_FL1; 811 inst->_has_immediat = 0; 812 // inst->_immediat = ; 813 inst->_read_ra = 1; 814 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 815 inst->_read_rb = 0; 816 // inst->_num_reg_rb = ; 817 inst->_read_rc = 0; 818 // inst->_num_reg_rc = ; 819 inst->_write_rd = 1; 820 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 821 inst->_write_re = 0; 822 // inst->_num_reg_re = ; 823 inst->_exception_use = EXCEPTION_USE_NONE; 824 inst->_exception = EXCEPTION_DECOD_NONE; 825 // inst->_branch_condition = ; 826 // inst->_branch_stack_write = ; 827 // inst->_branch_direction = ; 828 // inst->_address_next = ; 829 inst->_no_execute = 0; 788 830 inst->_event_type = EVENT_TYPE_NONE; 789 831 } … … 793 835 log_printf(TRACE,Decod,"instruction_l_j"," * instruction : l.j"); 794 836 795 inst->_type = TYPE_BRANCH;796 inst->_operation = OPERATION_BRANCH_NONE;837 inst->_type = instruction_information(INSTRUCTION_L_J)._type ; //TYPE_BRANCH; 838 inst->_operation = instruction_information(INSTRUCTION_L_J)._operation; //OPERATION_BRANCH_NONE; 797 839 inst->_has_immediat = 0; 798 840 // inst->_immediat = ; … … 808 850 // inst->_num_reg_re = ; 809 851 inst->_exception_use = EXCEPTION_USE_NONE; 852 inst->_exception = EXCEPTION_DECOD_NONE; 810 853 inst->_branch_condition = BRANCH_CONDITION_NONE_WITHOUT_WRITE_STACK; 811 854 // inst->_branch_stack_write = 0; 812 855 inst->_branch_direction = 1; 813 inst->_address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); 856 inst->_address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 857 ); 858 inst->_no_execute = 1; 814 859 inst->_event_type = EVENT_TYPE_NONE; 815 860 } … … 819 864 log_printf(TRACE,Decod,"instruction_l_jal"," * instruction : l.jal"); 820 865 821 inst->_type = TYPE_BRANCH;822 inst->_operation = OPERATION_BRANCH_L_JALR;866 inst->_type = instruction_information(INSTRUCTION_L_JAL)._type ; //TYPE_BRANCH; 867 inst->_operation = instruction_information(INSTRUCTION_L_JAL)._operation; //OPERATION_BRANCH_L_JALR; 823 868 inst->_has_immediat = 1; 824 869 inst->_immediat = inst->_address_next+1; … … 834 879 // inst->_num_reg_re = ; 835 880 inst->_exception_use = EXCEPTION_USE_NONE; 881 inst->_exception = EXCEPTION_DECOD_NONE; 836 882 inst->_branch_condition = BRANCH_CONDITION_NONE_WITH_WRITE_STACK; // Always jump 837 883 // inst->_branch_stack_write = 1; 838 884 inst->_branch_direction = 1; 839 inst->_address_next = inst->_address+(EXTENDS(inst->_instruction,26)<<2); 885 inst->_address_next = signed(param->_size_data,inst->_address+EXTENDS(inst->_instruction,26)// <<2 886 ); 887 inst->_no_execute = 0; 840 888 inst->_event_type = EVENT_TYPE_NONE; 841 889 } … … 853 901 else 854 902 { 855 inst->_type = TYPE_BRANCH;856 inst->_operation = OPERATION_BRANCH_L_JALR;903 inst->_type = instruction_information(INSTRUCTION_L_JALR)._type ; //TYPE_BRANCH; 904 inst->_operation = instruction_information(INSTRUCTION_L_JALR)._operation; //OPERATION_BRANCH_L_JALR; 857 905 inst->_has_immediat = 0; 858 906 // inst->_immediat = ; … … 868 916 // inst->_num_reg_re = ; 869 917 inst->_exception_use = EXCEPTION_USE_NONE; 918 inst->_exception = EXCEPTION_DECOD_NONE; 870 919 // inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER; 871 920 inst->_branch_condition = BRANCH_CONDITION_READ_REGISTER_WITH_WRITE_STACK; … … 873 922 inst->_branch_direction = 1; 874 923 // inst->_address_next = ; 924 inst->_no_execute = 0; 875 925 inst->_event_type = EVENT_TYPE_NONE; 876 926 } … … 881 931 log_printf(TRACE,Decod,"instruction_l_jr"," * instruction : l.jr"); 882 932 883 inst->_type = TYPE_BRANCH;884 inst->_operation = OPERATION_BRANCH_L_JALR;933 inst->_type = instruction_information(INSTRUCTION_L_JR)._type ; //TYPE_BRANCH; 934 inst->_operation = instruction_information(INSTRUCTION_L_JR)._operation; //OPERATION_BRANCH_L_JALR; 885 935 inst->_has_immediat = 0; 886 936 // inst->_immediat = ; … … 896 946 // inst->_num_reg_re = ; 897 947 inst->_exception_use = EXCEPTION_USE_NONE; 948 inst->_exception = EXCEPTION_DECOD_NONE; 898 949 inst->_branch_condition = (inst->_num_reg_rb == 9)?BRANCH_CONDITION_READ_STACK:BRANCH_CONDITION_READ_REGISTER_WITHOUT_WRITE_STACK; 899 950 // inst->_branch_stack_write = 0; 900 951 inst->_branch_direction = 1; 901 952 // inst->_address_next = ; 953 inst->_no_execute = 0; 902 954 inst->_event_type = EVENT_TYPE_NONE; 903 955 } … … 907 959 log_printf(TRACE,Decod,"instruction_l_lbs"," * instruction : l.lbs"); 908 960 909 inst->_type = TYPE_MEMORY;910 inst->_operation = OPERATION_MEMORY_LOAD_8_S;961 inst->_type = instruction_information(INSTRUCTION_L_LBS)._type ; //TYPE_MEMORY; 962 inst->_operation = instruction_information(INSTRUCTION_L_LBS)._operation; //OPERATION_MEMORY_LOAD_8_S; 911 963 inst->_has_immediat = 1; 912 964 inst->_immediat = EXTENDS(inst->_instruction,16); … … 922 974 // inst->_num_reg_re = ; 923 975 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 924 // inst->_branch_condition = ; 925 // inst->_branch_stack_write = ; 926 // inst->_branch_direction = ; 927 // inst->_address_next = ; 976 inst->_exception = EXCEPTION_DECOD_NONE; 977 // inst->_branch_condition = ; 978 // inst->_branch_stack_write = ; 979 // inst->_branch_direction = ; 980 // inst->_address_next = ; 981 inst->_no_execute = 0; 928 982 inst->_event_type = EVENT_TYPE_NONE; 929 983 } … … 933 987 log_printf(TRACE,Decod,"instruction_l_lbz"," * instruction : l.lbz"); 934 988 935 inst->_type = TYPE_MEMORY;936 inst->_operation = OPERATION_MEMORY_LOAD_8_Z;989 inst->_type = instruction_information(INSTRUCTION_L_LBZ)._type ; //TYPE_MEMORY; 990 inst->_operation = instruction_information(INSTRUCTION_L_LBZ)._operation; //OPERATION_MEMORY_LOAD_8_Z; 937 991 inst->_has_immediat = 1; 938 992 inst->_immediat = EXTENDS(inst->_instruction,16); … … 948 1002 // inst->_num_reg_re = ; 949 1003 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 950 // inst->_branch_condition = ; 951 // inst->_branch_stack_write = ; 952 // inst->_branch_direction = ; 953 // inst->_address_next = ; 1004 inst->_exception = EXCEPTION_DECOD_NONE; 1005 // inst->_branch_condition = ; 1006 // inst->_branch_stack_write = ; 1007 // inst->_branch_direction = ; 1008 // inst->_address_next = ; 1009 inst->_no_execute = 0; 954 1010 inst->_event_type = EVENT_TYPE_NONE; 955 1011 } … … 959 1015 log_printf(TRACE,Decod,"instruction_l_ld"," * instruction : l.ld"); 960 1016 961 inst->_type = TYPE_MEMORY;962 inst->_operation = OPERATION_MEMORY_LOAD_64_S;1017 inst->_type = instruction_information(INSTRUCTION_L_LD)._type ; //TYPE_MEMORY; 1018 inst->_operation = instruction_information(INSTRUCTION_L_LD)._operation; //OPERATION_MEMORY_LOAD_64_S; 963 1019 inst->_has_immediat = 1; 964 1020 inst->_immediat = EXTENDS(inst->_instruction,16); … … 974 1030 // inst->_num_reg_re = ; 975 1031 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 976 // inst->_branch_condition = ; 977 // inst->_branch_stack_write = ; 978 // inst->_branch_direction = ; 979 // inst->_address_next = ; 1032 inst->_exception = EXCEPTION_DECOD_NONE; 1033 // inst->_branch_condition = ; 1034 // inst->_branch_stack_write = ; 1035 // inst->_branch_direction = ; 1036 // inst->_address_next = ; 1037 inst->_no_execute = 0; 980 1038 inst->_event_type = EVENT_TYPE_NONE; 981 1039 } … … 985 1043 log_printf(TRACE,Decod,"instruction_l_lhs"," * instruction : l.lhs"); 986 1044 987 inst->_type = TYPE_MEMORY;988 inst->_operation = OPERATION_MEMORY_LOAD_16_S;1045 inst->_type = instruction_information(INSTRUCTION_L_LHS)._type ; //TYPE_MEMORY; 1046 inst->_operation = instruction_information(INSTRUCTION_L_LHS)._operation; //OPERATION_MEMORY_LOAD_16_S; 989 1047 inst->_has_immediat = 1; 990 1048 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1000 1058 // inst->_num_reg_re = ; 1001 1059 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1002 // inst->_branch_condition = ; 1003 // inst->_branch_stack_write = ; 1004 // inst->_branch_direction = ; 1005 // inst->_address_next = ; 1060 inst->_exception = EXCEPTION_DECOD_NONE; 1061 // inst->_branch_condition = ; 1062 // inst->_branch_stack_write = ; 1063 // inst->_branch_direction = ; 1064 // inst->_address_next = ; 1065 inst->_no_execute = 0; 1006 1066 inst->_event_type = EVENT_TYPE_NONE; 1007 1067 } … … 1011 1071 log_printf(TRACE,Decod,"instruction_l_lhz"," * instruction : l.lhz"); 1012 1072 1013 inst->_type = TYPE_MEMORY;1014 inst->_operation = OPERATION_MEMORY_LOAD_16_Z;1073 inst->_type = instruction_information(INSTRUCTION_L_LHZ)._type ; //TYPE_MEMORY; 1074 inst->_operation = instruction_information(INSTRUCTION_L_LHZ)._operation; //OPERATION_MEMORY_LOAD_16_Z; 1015 1075 inst->_has_immediat = 1; 1016 1076 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1026 1086 // inst->_num_reg_re = ; 1027 1087 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1028 // inst->_branch_condition = ; 1029 // inst->_branch_stack_write = ; 1030 // inst->_branch_direction = ; 1031 // inst->_address_next = ; 1088 inst->_exception = EXCEPTION_DECOD_NONE; 1089 // inst->_branch_condition = ; 1090 // inst->_branch_stack_write = ; 1091 // inst->_branch_direction = ; 1092 // inst->_address_next = ; 1093 inst->_no_execute = 0; 1032 1094 inst->_event_type = EVENT_TYPE_NONE; 1033 1095 } … … 1037 1099 log_printf(TRACE,Decod,"instruction_l_lws"," * instruction : l.lws"); 1038 1100 1039 inst->_type = TYPE_MEMORY;1040 inst->_operation = OPERATION_MEMORY_LOAD_32_S;1101 inst->_type = instruction_information(INSTRUCTION_L_LWS)._type ; //TYPE_MEMORY; 1102 inst->_operation = instruction_information(INSTRUCTION_L_LWS)._operation; //OPERATION_MEMORY_LOAD_32_S; 1041 1103 inst->_has_immediat = 1; 1042 1104 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1052 1114 // inst->_num_reg_re = ; 1053 1115 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1054 // inst->_branch_condition = ; 1055 // inst->_branch_stack_write = ; 1056 // inst->_branch_direction = ; 1057 // inst->_address_next = ; 1116 inst->_exception = EXCEPTION_DECOD_NONE; 1117 // inst->_branch_condition = ; 1118 // inst->_branch_stack_write = ; 1119 // inst->_branch_direction = ; 1120 // inst->_address_next = ; 1121 inst->_no_execute = 0; 1058 1122 inst->_event_type = EVENT_TYPE_NONE; 1059 1123 } … … 1063 1127 log_printf(TRACE,Decod,"instruction_l_lwz"," * instruction : l.lwz"); 1064 1128 1065 inst->_type = TYPE_MEMORY;1066 inst->_operation = OPERATION_MEMORY_LOAD_32_Z;1129 inst->_type = instruction_information(INSTRUCTION_L_LWZ)._type ; //TYPE_MEMORY; 1130 inst->_operation = instruction_information(INSTRUCTION_L_LWZ)._operation; //OPERATION_MEMORY_LOAD_32_Z; 1067 1131 inst->_has_immediat = 1; 1068 1132 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1078 1142 // inst->_num_reg_re = ; 1079 1143 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1080 // inst->_branch_condition = ; 1081 // inst->_branch_stack_write = ; 1082 // inst->_branch_direction = ; 1083 // inst->_address_next = ; 1144 inst->_exception = EXCEPTION_DECOD_NONE; 1145 // inst->_branch_condition = ; 1146 // inst->_branch_stack_write = ; 1147 // inst->_branch_direction = ; 1148 // inst->_address_next = ; 1149 inst->_no_execute = 0; 1084 1150 inst->_event_type = EVENT_TYPE_NONE; 1085 1151 } … … 1089 1155 log_printf(TRACE,Decod,"instruction_l_mac"," * instruction : l.mac"); 1090 1156 1091 inst->_type = TYPE_SPECIAL; 1092 inst->_operation = OPERATION_SPECIAL_L_MAC; 1093 inst->_has_immediat = 0; 1094 // inst->_immediat = ; 1095 inst->_read_ra = 1; 1096 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1097 inst->_read_rb = 1; 1098 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1099 inst->_read_rc = 0; 1100 // inst->_num_reg_rc = ; 1101 inst->_write_rd = 0; 1102 // inst->_num_reg_rd = ; 1103 inst->_write_re = 0; 1104 // inst->_num_reg_re = ; 1105 inst->_exception_use = EXCEPTION_USE_NONE; 1157 inst->_type = instruction_information(INSTRUCTION_L_MAC)._type ; //TYPE_SPECIAL; 1158 inst->_operation = instruction_information(INSTRUCTION_L_MAC)._operation; //OPERATION_SPECIAL_L_MAC; 1159 inst->_has_immediat = 0; 1160 // inst->_immediat = ; 1161 inst->_read_ra = 1; 1162 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1163 inst->_read_rb = 1; 1164 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1165 inst->_read_rc = 0; 1166 // inst->_num_reg_rc = ; 1167 inst->_write_rd = 0; 1168 // inst->_num_reg_rd = ; 1169 inst->_write_re = 0; 1170 // inst->_num_reg_re = ; 1171 inst->_exception_use = EXCEPTION_USE_NONE; 1172 inst->_exception = EXCEPTION_DECOD_NONE; 1106 1173 // inst->_branch_condition = ; 1107 1174 // inst->_branch_stack_write = ; 1108 1175 // inst->_branch_direction = ; 1109 1176 // inst->_address_next = ; // don't change 1177 inst->_no_execute = 0; 1110 1178 inst->_event_type = EVENT_TYPE_SPR_ACCESS; 1111 1179 } … … 1115 1183 log_printf(TRACE,Decod,"instruction_l_maci"," * instruction : l.maci"); 1116 1184 1117 inst->_type = TYPE_SPECIAL;1118 inst->_operation = OPERATION_SPECIAL_L_MAC;1185 inst->_type = instruction_information(INSTRUCTION_L_MACI)._type ; //TYPE_SPECIAL; 1186 inst->_operation = instruction_information(INSTRUCTION_L_MACI)._operation; //OPERATION_SPECIAL_L_MAC; 1119 1187 inst->_has_immediat = 1; 1120 1188 inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| … … 1131 1199 // inst->_num_reg_re = ; 1132 1200 inst->_exception_use = EXCEPTION_USE_NONE; 1201 inst->_exception = EXCEPTION_DECOD_NONE; 1133 1202 // inst->_branch_condition = ; 1134 1203 // inst->_branch_stack_write = ; 1135 1204 // inst->_branch_direction = ; 1136 1205 // inst->_address_next = ; // don't change 1206 inst->_no_execute = 0; 1137 1207 inst->_event_type = EVENT_TYPE_SPR_ACCESS; 1138 1208 } … … 1148 1218 else 1149 1219 { 1150 inst->_type = TYPE_SPECIAL;1151 inst->_operation = OPERATION_SPECIAL_L_MACRC;1220 inst->_type = instruction_information(INSTRUCTION_L_MACRC)._type ; //TYPE_SPECIAL; 1221 inst->_operation = instruction_information(INSTRUCTION_L_MACRC)._operation; //OPERATION_SPECIAL_L_MACRC; 1152 1222 inst->_has_immediat = 0; 1153 1223 // inst->_immediat = ; … … 1163 1233 // inst->_num_reg_re = ; 1164 1234 inst->_exception_use = EXCEPTION_USE_NONE; 1235 inst->_exception = EXCEPTION_DECOD_NONE; 1165 1236 // inst->_branch_condition = ; 1166 1237 // inst->_branch_stack_write = ; 1167 1238 // inst->_branch_direction = ; 1168 1239 // inst->_address_next = ; // don't change 1240 inst->_no_execute = 0; 1169 1241 inst->_event_type = EVENT_TYPE_SPR_ACCESS; 1170 1242 } … … 1175 1247 log_printf(TRACE,Decod,"instruction_l_mfspr"," * instruction : l.mfspr"); 1176 1248 1177 inst->_type = TYPE_SPECIAL;1178 inst->_operation = OPERATION_SPECIAL_L_MFSPR;1249 inst->_type = instruction_information(INSTRUCTION_L_MFSPR)._type ; //TYPE_SPECIAL; 1250 inst->_operation = instruction_information(INSTRUCTION_L_MFSPR)._operation; //OPERATION_SPECIAL_L_MFSPR; 1179 1251 inst->_has_immediat = 1; 1180 1252 inst->_immediat = EXTENDZ(inst->_instruction,16); … … 1190 1262 // inst->_num_reg_re = ; 1191 1263 inst->_exception_use = EXCEPTION_USE_NONE; 1264 inst->_exception = EXCEPTION_DECOD_NONE; 1192 1265 // inst->_branch_condition = ; 1193 1266 // inst->_branch_stack_write = ; 1194 1267 // inst->_branch_direction = ; 1195 1268 // inst->_address_next = ; // don't change 1269 inst->_no_execute = 0; 1196 1270 inst->_event_type = EVENT_TYPE_SPR_ACCESS; 1197 1271 } … … 1201 1275 log_printf(TRACE,Decod,"instruction_l_movhi"," * instruction : l.movhi"); 1202 1276 1203 inst->_type = TYPE_MOVE;1204 inst->_operation = OPERATION_MOVE_L_MOVHI;1277 inst->_type = instruction_information(INSTRUCTION_L_MOVHI)._type ; //TYPE_MOVE; 1278 inst->_operation = instruction_information(INSTRUCTION_L_MOVHI)._operation; //OPERATION_MOVE_L_MOVHI; 1205 1279 inst->_has_immediat = 1; 1206 1280 inst->_immediat = EXTENDZ(inst->_instruction,16); … … 1216 1290 // inst->_num_reg_re = ; 1217 1291 inst->_exception_use = EXCEPTION_USE_NONE; 1218 // inst->_branch_condition = ; 1219 // inst->_branch_stack_write = ; 1220 // inst->_branch_direction = ; 1221 // inst->_address_next = ; 1292 inst->_exception = EXCEPTION_DECOD_NONE; 1293 // inst->_branch_condition = ; 1294 // inst->_branch_stack_write = ; 1295 // inst->_branch_direction = ; 1296 // inst->_address_next = ; 1297 inst->_no_execute = 0; 1222 1298 inst->_event_type = EVENT_TYPE_NONE; 1223 1299 } … … 1227 1303 log_printf(TRACE,Decod,"instruction_l_msb"," * instruction : l.msb"); 1228 1304 1229 inst->_type = TYPE_SPECIAL; 1230 inst->_operation = OPERATION_SPECIAL_L_MSB; 1231 inst->_has_immediat = 0; 1232 // inst->_immediat = ; 1233 inst->_read_ra = 1; 1234 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1235 inst->_read_rb = 1; 1236 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1237 inst->_read_rc = 0; 1238 // inst->_num_reg_rc = ; 1239 inst->_write_rd = 0; 1240 // inst->_num_reg_rd = ; 1241 inst->_write_re = 0; 1242 // inst->_num_reg_re = ; 1243 inst->_exception_use = EXCEPTION_USE_NONE; 1305 inst->_type = instruction_information(INSTRUCTION_L_MSB)._type ; //TYPE_SPECIAL; 1306 inst->_operation = instruction_information(INSTRUCTION_L_MSB)._operation; //OPERATION_SPECIAL_L_MSB; 1307 inst->_has_immediat = 0; 1308 // inst->_immediat = ; 1309 inst->_read_ra = 1; 1310 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1311 inst->_read_rb = 1; 1312 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1313 inst->_read_rc = 0; 1314 // inst->_num_reg_rc = ; 1315 inst->_write_rd = 0; 1316 // inst->_num_reg_rd = ; 1317 inst->_write_re = 0; 1318 // inst->_num_reg_re = ; 1319 inst->_exception_use = EXCEPTION_USE_NONE; 1320 inst->_exception = EXCEPTION_DECOD_NONE; 1244 1321 // inst->_branch_condition = ; 1245 1322 // inst->_branch_stack_write = ; 1246 1323 // inst->_branch_direction = ; 1247 1324 // inst->_address_next = ; // don't change 1325 inst->_no_execute = 0; 1248 1326 inst->_event_type = EVENT_TYPE_SPR_ACCESS; 1249 1327 } … … 1259 1337 else 1260 1338 { 1261 inst->_type = TYPE_SPECIAL;1262 inst->_operation = OPERATION_SPECIAL_L_MSYNC;1339 inst->_type = instruction_information(INSTRUCTION_L_MSYNC)._type ; //TYPE_SPECIAL; 1340 inst->_operation = instruction_information(INSTRUCTION_L_MSYNC)._operation; //OPERATION_SPECIAL_L_MSYNC; 1263 1341 inst->_has_immediat = 0; 1264 1342 // inst->_immediat = ; … … 1274 1352 // inst->_num_reg_re = ; 1275 1353 inst->_exception_use = EXCEPTION_USE_NONE; 1354 inst->_exception = EXCEPTION_DECOD_NONE; 1276 1355 // inst->_branch_condition = ; 1277 1356 // inst->_branch_stack_write = ; 1278 1357 // inst->_branch_direction = ; 1279 1358 // inst->_address_next = ; // don't change 1359 inst->_no_execute = 0; 1280 1360 inst->_event_type = EVENT_TYPE_MSYNC; 1281 1361 } … … 1286 1366 log_printf(TRACE,Decod,"instruction_l_mtspr"," * instruction : l.mtspr"); 1287 1367 1288 inst->_type = TYPE_SPECIAL;1289 inst->_operation = OPERATION_SPECIAL_L_MTSPR;1368 inst->_type = instruction_information(INSTRUCTION_L_MTSPR)._type ; //TYPE_SPECIAL; 1369 inst->_operation = instruction_information(INSTRUCTION_L_MTSPR)._operation; //OPERATION_SPECIAL_L_MTSPR; 1290 1370 inst->_has_immediat = 1; 1291 1371 inst->_immediat = EXTENDZ(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| … … 1302 1382 // inst->_num_reg_re = ; 1303 1383 inst->_exception_use = EXCEPTION_USE_NONE; 1384 inst->_exception = EXCEPTION_DECOD_NONE; 1304 1385 // inst->_branch_condition = ; 1305 1386 // inst->_branch_stack_write = ; 1306 1387 // inst->_branch_direction = ; 1307 1388 // inst->_address_next = ; // don't change 1389 inst->_no_execute = 0; 1308 1390 inst->_event_type = EVENT_TYPE_SPR_ACCESS; 1309 1391 } … … 1313 1395 log_printf(TRACE,Decod,"instruction_l_mul"," * instruction : l.mul"); 1314 1396 1315 inst->_type = TYPE_MUL_DIV;1316 inst->_operation = OPERATION_MUL_DIV_L_MUL;1397 inst->_type = instruction_information(INSTRUCTION_L_MUL)._type ; //TYPE_MUL; 1398 inst->_operation = instruction_information(INSTRUCTION_L_MUL)._operation; //OPERATION_MUL_L_MUL; 1317 1399 inst->_has_immediat = 0; 1318 1400 // inst->_immediat = ; … … 1328 1410 inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; 1329 1411 inst->_exception_use = EXCEPTION_USE_RANGE; 1330 // inst->_branch_condition = ; 1331 // inst->_branch_stack_write = ; 1332 // inst->_branch_direction = ; 1333 // inst->_address_next = ; 1412 inst->_exception = EXCEPTION_DECOD_NONE; 1413 // inst->_branch_condition = ; 1414 // inst->_branch_stack_write = ; 1415 // inst->_branch_direction = ; 1416 // inst->_address_next = ; 1417 inst->_no_execute = 0; 1334 1418 inst->_event_type = EVENT_TYPE_NONE; 1335 1419 } … … 1339 1423 log_printf(TRACE,Decod,"instruction_l_muli"," * instruction : l.muli"); 1340 1424 1341 inst->_type = TYPE_MUL_DIV;1342 inst->_operation = OPERATION_MUL_DIV_L_MUL;1425 inst->_type = instruction_information(INSTRUCTION_L_MULI)._type ; //TYPE_MUL; 1426 inst->_operation = instruction_information(INSTRUCTION_L_MULI)._operation; //OPERATION_MUL_L_MUL; 1343 1427 inst->_has_immediat = 1; 1344 1428 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1354 1438 inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; 1355 1439 inst->_exception_use = EXCEPTION_USE_RANGE; 1356 // inst->_branch_condition = ; 1357 // inst->_branch_stack_write = ; 1358 // inst->_branch_direction = ; 1359 // inst->_address_next = ; 1440 inst->_exception = EXCEPTION_DECOD_NONE; 1441 // inst->_branch_condition = ; 1442 // inst->_branch_stack_write = ; 1443 // inst->_branch_direction = ; 1444 // inst->_address_next = ; 1445 inst->_no_execute = 0; 1360 1446 inst->_event_type = EVENT_TYPE_NONE; 1361 1447 } … … 1365 1451 log_printf(TRACE,Decod,"instruction_l_mulu"," * instruction : l.mulu"); 1366 1452 1367 inst->_type = TYPE_MUL_DIV;1368 inst->_operation = OPERATION_MUL_DIV_L_MULU;1453 inst->_type = instruction_information(INSTRUCTION_L_MULU)._type ; //TYPE_MUL; 1454 inst->_operation = instruction_information(INSTRUCTION_L_MULU)._operation; //OPERATION_MUL_L_MULU; 1369 1455 inst->_has_immediat = 0; 1370 1456 // inst->_immediat = ; … … 1380 1466 inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; 1381 1467 inst->_exception_use = EXCEPTION_USE_RANGE; 1382 // inst->_branch_condition = ; 1383 // inst->_branch_stack_write = ; 1384 // inst->_branch_direction = ; 1385 // inst->_address_next = ; 1468 inst->_exception = EXCEPTION_DECOD_NONE; 1469 // inst->_branch_condition = ; 1470 // inst->_branch_stack_write = ; 1471 // inst->_branch_direction = ; 1472 // inst->_address_next = ; 1473 inst->_no_execute = 0; 1386 1474 inst->_event_type = EVENT_TYPE_NONE; 1387 1475 } … … 1391 1479 log_printf(TRACE,Decod,"instruction_l_nop"," * instruction : l.nop"); 1392 1480 1393 inst->_type = TYPE_SPECIAL;1394 inst->_operation = OPERATION_SPECIAL_L_NOP;1481 inst->_type = instruction_information(INSTRUCTION_L_NOP)._type ; //TYPE_SPECIAL; 1482 inst->_operation = instruction_information(INSTRUCTION_L_NOP)._operation; //OPERATION_SPECIAL_L_NOP; 1395 1483 // inst->_has_immediat = 1; 1396 1484 // inst->_immediat = EXTENDZ(inst->_instruction,16); … … 1408 1496 // inst->_num_reg_re = ; 1409 1497 inst->_exception_use = EXCEPTION_USE_NONE; 1410 // inst->_branch_condition = ; 1411 // inst->_branch_stack_write = ; 1412 // inst->_branch_direction = ; 1413 // inst->_address_next = ; 1498 inst->_exception = EXCEPTION_DECOD_NONE; 1499 // inst->_branch_condition = ; 1500 // inst->_branch_stack_write = ; 1501 // inst->_branch_direction = ; 1502 // inst->_address_next = ; 1503 inst->_no_execute = 1; 1414 1504 inst->_event_type = EVENT_TYPE_NONE; 1415 1505 } … … 1419 1509 log_printf(TRACE,Decod,"instruction_l_or"," * instruction : l.or"); 1420 1510 1421 inst->_type = TYPE_ALU; 1422 inst->_operation = OPERATION_ALU_L_OR; 1423 inst->_has_immediat = 0; 1424 // inst->_immediat = ; 1425 inst->_read_ra = 1; 1426 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1427 inst->_read_rb = 1; 1428 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1429 inst->_read_rc = 0; 1430 // inst->_num_reg_rc = ; 1431 inst->_write_rd = 1; 1432 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1433 inst->_write_re = 0; 1434 // inst->_num_reg_re = ; 1435 inst->_exception_use = EXCEPTION_USE_NONE; 1436 // inst->_branch_condition = ; 1437 // inst->_branch_stack_write = ; 1438 // inst->_branch_direction = ; 1439 // inst->_address_next = ; 1511 inst->_type = instruction_information(INSTRUCTION_L_OR)._type ; //TYPE_ALU; 1512 inst->_operation = instruction_information(INSTRUCTION_L_OR)._operation; //OPERATION_ALU_L_OR; 1513 inst->_has_immediat = 0; 1514 // inst->_immediat = ; 1515 inst->_read_ra = 1; 1516 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1517 inst->_read_rb = 1; 1518 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1519 inst->_read_rc = 0; 1520 // inst->_num_reg_rc = ; 1521 inst->_write_rd = 1; 1522 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1523 inst->_write_re = 0; 1524 // inst->_num_reg_re = ; 1525 inst->_exception_use = EXCEPTION_USE_NONE; 1526 inst->_exception = EXCEPTION_DECOD_NONE; 1527 // inst->_branch_condition = ; 1528 // inst->_branch_stack_write = ; 1529 // inst->_branch_direction = ; 1530 // inst->_address_next = ; 1531 inst->_no_execute = 0; 1440 1532 inst->_event_type = EVENT_TYPE_NONE; 1441 1533 } … … 1445 1537 log_printf(TRACE,Decod,"instruction_l_ori"," * instruction : l.ori"); 1446 1538 1447 inst->_type = TYPE_ALU;1448 inst->_operation = OPERATION_ALU_L_OR;1539 inst->_type = instruction_information(INSTRUCTION_L_ORI)._type ; //TYPE_ALU; 1540 inst->_operation = instruction_information(INSTRUCTION_L_ORI)._operation; //OPERATION_ALU_L_OR; 1449 1541 inst->_has_immediat = 1; 1450 1542 inst->_immediat = EXTENDZ(inst->_instruction,16); … … 1460 1552 // inst->_num_reg_re = ; 1461 1553 inst->_exception_use = EXCEPTION_USE_NONE; 1462 // inst->_branch_condition = ; 1463 // inst->_branch_stack_write = ; 1464 // inst->_branch_direction = ; 1465 // inst->_address_next = ; 1554 inst->_exception = EXCEPTION_DECOD_NONE; 1555 // inst->_branch_condition = ; 1556 // inst->_branch_stack_write = ; 1557 // inst->_branch_direction = ; 1558 // inst->_address_next = ; 1559 inst->_no_execute = 0; 1466 1560 inst->_event_type = EVENT_TYPE_NONE; 1467 1561 } … … 1477 1571 else 1478 1572 { 1479 inst->_type = TYPE_SPECIAL;1480 inst->_operation = OPERATION_SPECIAL_L_PSYNC;1573 inst->_type = instruction_information(INSTRUCTION_L_PSYNC)._type ; //TYPE_SPECIAL; 1574 inst->_operation = instruction_information(INSTRUCTION_L_PSYNC)._operation; //OPERATION_SPECIAL_L_PSYNC; 1481 1575 inst->_has_immediat = 0; 1482 1576 // inst->_immediat = ; … … 1492 1586 // inst->_num_reg_re = ; 1493 1587 inst->_exception_use = EXCEPTION_USE_NONE; 1588 inst->_exception = EXCEPTION_DECOD_NONE; 1494 1589 // inst->_branch_condition = ; 1495 1590 // inst->_branch_stack_write = ; 1496 1591 // inst->_branch_direction = ; 1497 1592 // inst->_address_next = ; // don't change 1593 inst->_no_execute = 0; 1498 1594 inst->_event_type = EVENT_TYPE_PSYNC; 1499 1595 } … … 1504 1600 log_printf(TRACE,Decod,"instruction_l_rfe"," * instruction : l.rfe"); 1505 1601 1506 inst->_type = TYPE_SPECIAL;1507 inst->_operation = OPERATION_SPECIAL_L_RFE;1602 inst->_type = instruction_information(INSTRUCTION_L_RFE)._type ; //TYPE_SPECIAL; 1603 inst->_operation = instruction_information(INSTRUCTION_L_RFE)._operation; //OPERATION_SPECIAL_L_RFE; 1508 1604 inst->_has_immediat = 0; 1509 1605 // inst->_immediat = ; … … 1519 1615 // inst->_num_reg_re = ; 1520 1616 inst->_exception_use = EXCEPTION_USE_NONE; 1617 inst->_exception = EXCEPTION_DECOD_NONE; 1521 1618 // inst->_branch_condition = ; 1522 1619 // inst->_branch_stack_write = ; 1523 1620 // inst->_branch_direction = ; 1524 1621 // inst->_address_next = ; // don't change 1622 inst->_no_execute = 1; 1525 1623 inst->_event_type = EVENT_TYPE_NONE; // can't anticip this instruction : must read EPCR in rename stage 1526 1624 } … … 1530 1628 log_printf(TRACE,Decod,"instruction_l_ror"," * instruction : l.ror"); 1531 1629 1532 inst->_type = TYPE_SHIFT; 1533 inst->_operation = OPERATION_SHIFT_L_ROR; 1534 inst->_has_immediat = 0; 1535 // inst->_immediat = ; 1536 inst->_read_ra = 1; 1537 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1538 inst->_read_rb = 1; 1539 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1540 inst->_read_rc = 0; 1541 // inst->_num_reg_rc = ; 1542 inst->_write_rd = 1; 1543 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1544 inst->_write_re = 0; 1545 // inst->_num_reg_re = ; 1546 inst->_exception_use = EXCEPTION_USE_NONE; 1547 // inst->_branch_condition = ; 1548 // inst->_branch_stack_write = ; 1549 // inst->_branch_direction = ; 1550 // inst->_address_next = ; 1630 inst->_type = instruction_information(INSTRUCTION_L_ROR)._type ; //TYPE_SHIFT; 1631 inst->_operation = instruction_information(INSTRUCTION_L_ROR)._operation; //OPERATION_SHIFT_L_ROR; 1632 inst->_has_immediat = 0; 1633 // inst->_immediat = ; 1634 inst->_read_ra = 1; 1635 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 1636 inst->_read_rb = 1; 1637 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 1638 inst->_read_rc = 0; 1639 // inst->_num_reg_rc = ; 1640 inst->_write_rd = 1; 1641 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 1642 inst->_write_re = 0; 1643 // inst->_num_reg_re = ; 1644 inst->_exception_use = EXCEPTION_USE_NONE; 1645 inst->_exception = EXCEPTION_DECOD_NONE; 1646 // inst->_branch_condition = ; 1647 // inst->_branch_stack_write = ; 1648 // inst->_branch_direction = ; 1649 // inst->_address_next = ; 1650 inst->_no_execute = 0; 1551 1651 inst->_event_type = EVENT_TYPE_NONE; 1552 1652 } … … 1556 1656 log_printf(TRACE,Decod,"instruction_l_rori"," * instruction : l.rori"); 1557 1657 1558 inst->_type = TYPE_SHIFT;1559 inst->_operation = OPERATION_SHIFT_L_ROR;1658 inst->_type = instruction_information(INSTRUCTION_L_RORI)._type ; //TYPE_SHIFT; 1659 inst->_operation = instruction_information(INSTRUCTION_L_RORI)._operation; //OPERATION_SHIFT_L_ROR; 1560 1660 inst->_has_immediat = 1; 1561 1661 inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); … … 1571 1671 // inst->_num_reg_re = ; 1572 1672 inst->_exception_use = EXCEPTION_USE_NONE; 1573 // inst->_branch_condition = ; 1574 // inst->_branch_stack_write = ; 1575 // inst->_branch_direction = ; 1576 // inst->_address_next = ; 1673 inst->_exception = EXCEPTION_DECOD_NONE; 1674 // inst->_branch_condition = ; 1675 // inst->_branch_stack_write = ; 1676 // inst->_branch_direction = ; 1677 // inst->_address_next = ; 1678 inst->_no_execute = 0; 1577 1679 inst->_event_type = EVENT_TYPE_NONE; 1578 1680 } … … 1582 1684 log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb"); 1583 1685 1584 inst->_type = TYPE_MEMORY;1585 inst->_operation = OPERATION_MEMORY_STORE_8;1686 inst->_type = instruction_information(INSTRUCTION_L_SB)._type ; //TYPE_MEMORY; 1687 inst->_operation = instruction_information(INSTRUCTION_L_SB)._operation; //OPERATION_MEMORY_STORE_8; 1586 1688 inst->_has_immediat = 1; 1587 1689 inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| … … 1598 1700 // inst->_num_reg_re = ; 1599 1701 inst->_exception_use = EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT; 1600 // inst->_branch_condition = ; 1601 // inst->_branch_stack_write = ; 1602 // inst->_branch_direction = ; 1603 // inst->_address_next = ; 1702 inst->_exception = EXCEPTION_DECOD_NONE; 1703 // inst->_branch_condition = ; 1704 // inst->_branch_stack_write = ; 1705 // inst->_branch_direction = ; 1706 // inst->_address_next = ; 1707 inst->_no_execute = 0; 1604 1708 inst->_event_type = EVENT_TYPE_NONE; 1605 1709 } … … 1609 1713 log_printf(TRACE,Decod,"instruction_l_sb"," * instruction : l.sb"); 1610 1714 1611 inst->_type = TYPE_MEMORY;1612 inst->_operation = OPERATION_MEMORY_STORE_64;1715 inst->_type = instruction_information(INSTRUCTION_L_SD)._type ; //TYPE_MEMORY; 1716 inst->_operation = instruction_information(INSTRUCTION_L_SD)._operation; //OPERATION_MEMORY_STORE_64; 1613 1717 inst->_has_immediat = 1; 1614 1718 inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| … … 1625 1729 // inst->_num_reg_re = ; 1626 1730 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 1627 // inst->_branch_condition = ; 1628 // inst->_branch_stack_write = ; 1629 // inst->_branch_direction = ; 1630 // inst->_address_next = ; 1731 inst->_exception = EXCEPTION_DECOD_NONE; 1732 // inst->_branch_condition = ; 1733 // inst->_branch_stack_write = ; 1734 // inst->_branch_direction = ; 1735 // inst->_address_next = ; 1736 inst->_no_execute = 0; 1631 1737 inst->_event_type = EVENT_TYPE_NONE; 1632 1738 } … … 1636 1742 log_printf(TRACE,Decod,"instruction_l_sfeq"," * instruction : l.sfeq"); 1637 1743 1638 inst->_type = TYPE_TEST;1639 inst->_operation = OPERATION_TEST_L_SFEQ;1744 inst->_type = instruction_information(INSTRUCTION_L_SFEQ)._type ; //TYPE_TEST; 1745 inst->_operation = instruction_information(INSTRUCTION_L_SFEQ)._operation; //OPERATION_TEST_L_SFEQ; 1640 1746 inst->_has_immediat = 0; 1641 1747 // inst->_immediat = ; … … 1651 1757 inst->_num_reg_re = SPR_LOGIC_SR_F; 1652 1758 inst->_exception_use = EXCEPTION_USE_NONE; 1653 // inst->_branch_condition = ; 1654 // inst->_branch_stack_write = ; 1655 // inst->_branch_direction = ; 1656 // inst->_address_next = ; 1759 inst->_exception = EXCEPTION_DECOD_NONE; 1760 // inst->_branch_condition = ; 1761 // inst->_branch_stack_write = ; 1762 // inst->_branch_direction = ; 1763 // inst->_address_next = ; 1764 inst->_no_execute = 0; 1657 1765 inst->_event_type = EVENT_TYPE_NONE; 1658 1766 } … … 1662 1770 log_printf(TRACE,Decod,"instruction_l_sfeqi"," * instruction : l.sfeqi"); 1663 1771 1664 inst->_type = TYPE_TEST;1665 inst->_operation = OPERATION_TEST_L_SFEQ;1772 inst->_type = instruction_information(INSTRUCTION_L_SFEQI)._type ; //TYPE_TEST; 1773 inst->_operation = instruction_information(INSTRUCTION_L_SFEQI)._operation; //OPERATION_TEST_L_SFEQ; 1666 1774 inst->_has_immediat = 1; 1667 1775 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1677 1785 inst->_num_reg_re = SPR_LOGIC_SR_F; 1678 1786 inst->_exception_use = EXCEPTION_USE_NONE; 1679 // inst->_branch_condition = ; 1680 // inst->_branch_stack_write = ; 1681 // inst->_branch_direction = ; 1682 // inst->_address_next = ; 1787 inst->_exception = EXCEPTION_DECOD_NONE; 1788 // inst->_branch_condition = ; 1789 // inst->_branch_stack_write = ; 1790 // inst->_branch_direction = ; 1791 // inst->_address_next = ; 1792 inst->_no_execute = 0; 1683 1793 inst->_event_type = EVENT_TYPE_NONE; 1684 1794 } … … 1688 1798 log_printf(TRACE,Decod,"instruction_l_sfges"," * instruction : l.sfges"); 1689 1799 1690 inst->_type = TYPE_TEST;1691 inst->_operation = OPERATION_TEST_L_SFGES;1800 inst->_type = instruction_information(INSTRUCTION_L_SFGES)._type ; //TYPE_TEST; 1801 inst->_operation = instruction_information(INSTRUCTION_L_SFGES)._operation; //OPERATION_TEST_L_SFGES; 1692 1802 inst->_has_immediat = 0; 1693 1803 // inst->_immediat = ; … … 1703 1813 inst->_num_reg_re = SPR_LOGIC_SR_F; 1704 1814 inst->_exception_use = EXCEPTION_USE_NONE; 1705 // inst->_branch_condition = ; 1706 // inst->_branch_stack_write = ; 1707 // inst->_branch_direction = ; 1708 // inst->_address_next = ; 1815 inst->_exception = EXCEPTION_DECOD_NONE; 1816 // inst->_branch_condition = ; 1817 // inst->_branch_stack_write = ; 1818 // inst->_branch_direction = ; 1819 // inst->_address_next = ; 1820 inst->_no_execute = 0; 1709 1821 inst->_event_type = EVENT_TYPE_NONE; 1710 1822 } … … 1714 1826 log_printf(TRACE,Decod,"instruction_l_sfgesi"," * instruction : l.sfgesi"); 1715 1827 1716 inst->_type = TYPE_TEST;1717 inst->_operation = OPERATION_TEST_L_SFGES;1828 inst->_type = instruction_information(INSTRUCTION_L_SFGESI)._type ; //TYPE_TEST; 1829 inst->_operation = instruction_information(INSTRUCTION_L_SFGESI)._operation; //OPERATION_TEST_L_SFGES; 1718 1830 inst->_has_immediat = 1; 1719 1831 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1729 1841 inst->_num_reg_re = SPR_LOGIC_SR_F; 1730 1842 inst->_exception_use = EXCEPTION_USE_NONE; 1731 // inst->_branch_condition = ; 1732 // inst->_branch_stack_write = ; 1733 // inst->_branch_direction = ; 1734 // inst->_address_next = ; 1843 inst->_exception = EXCEPTION_DECOD_NONE; 1844 // inst->_branch_condition = ; 1845 // inst->_branch_stack_write = ; 1846 // inst->_branch_direction = ; 1847 // inst->_address_next = ; 1848 inst->_no_execute = 0; 1735 1849 inst->_event_type = EVENT_TYPE_NONE; 1736 1850 } … … 1740 1854 log_printf(TRACE,Decod,"instruction_l_sfgeu"," * instruction : l.sfgeu"); 1741 1855 1742 inst->_type = TYPE_TEST;1743 inst->_operation = OPERATION_TEST_L_SFGEU;1856 inst->_type = instruction_information(INSTRUCTION_L_SFGEU)._type ; //TYPE_TEST; 1857 inst->_operation = instruction_information(INSTRUCTION_L_SFGEU)._operation; //OPERATION_TEST_L_SFGEU; 1744 1858 inst->_has_immediat = 0; 1745 1859 // inst->_immediat = ; … … 1755 1869 inst->_num_reg_re = SPR_LOGIC_SR_F; 1756 1870 inst->_exception_use = EXCEPTION_USE_NONE; 1757 // inst->_branch_condition = ; 1758 // inst->_branch_stack_write = ; 1759 // inst->_branch_direction = ; 1760 // inst->_address_next = ; 1871 inst->_exception = EXCEPTION_DECOD_NONE; 1872 // inst->_branch_condition = ; 1873 // inst->_branch_stack_write = ; 1874 // inst->_branch_direction = ; 1875 // inst->_address_next = ; 1876 inst->_no_execute = 0; 1761 1877 inst->_event_type = EVENT_TYPE_NONE; 1762 1878 } … … 1766 1882 log_printf(TRACE,Decod,"instruction_l_sfgeui"," * instruction : l.sfgeui"); 1767 1883 1768 inst->_type = TYPE_TEST;1769 inst->_operation = OPERATION_TEST_L_SFGEU;1884 inst->_type = instruction_information(INSTRUCTION_L_SFGEUI)._type ; //TYPE_TEST; 1885 inst->_operation = instruction_information(INSTRUCTION_L_SFGEUI)._operation; //OPERATION_TEST_L_SFGEU; 1770 1886 inst->_has_immediat = 1; 1771 1887 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1781 1897 inst->_num_reg_re = SPR_LOGIC_SR_F; 1782 1898 inst->_exception_use = EXCEPTION_USE_NONE; 1783 // inst->_branch_condition = ; 1784 // inst->_branch_stack_write = ; 1785 // inst->_branch_direction = ; 1786 // inst->_address_next = ; 1899 inst->_exception = EXCEPTION_DECOD_NONE; 1900 // inst->_branch_condition = ; 1901 // inst->_branch_stack_write = ; 1902 // inst->_branch_direction = ; 1903 // inst->_address_next = ; 1904 inst->_no_execute = 0; 1787 1905 inst->_event_type = EVENT_TYPE_NONE; 1788 1906 } … … 1792 1910 log_printf(TRACE,Decod,"instruction_l_sfgts"," * instruction : l.sfgts"); 1793 1911 1794 inst->_type = TYPE_TEST;1795 inst->_operation = OPERATION_TEST_L_SFGTS;1912 inst->_type = instruction_information(INSTRUCTION_L_SFGTS)._type ; //TYPE_TEST; 1913 inst->_operation = instruction_information(INSTRUCTION_L_SFGTS)._operation; //OPERATION_TEST_L_SFGTS; 1796 1914 inst->_has_immediat = 0; 1797 1915 // inst->_immediat = ; … … 1807 1925 inst->_num_reg_re = SPR_LOGIC_SR_F; 1808 1926 inst->_exception_use = EXCEPTION_USE_NONE; 1809 // inst->_branch_condition = ; 1810 // inst->_branch_stack_write = ; 1811 // inst->_branch_direction = ; 1812 // inst->_address_next = ; 1927 inst->_exception = EXCEPTION_DECOD_NONE; 1928 // inst->_branch_condition = ; 1929 // inst->_branch_stack_write = ; 1930 // inst->_branch_direction = ; 1931 // inst->_address_next = ; 1932 inst->_no_execute = 0; 1813 1933 inst->_event_type = EVENT_TYPE_NONE; 1814 1934 } … … 1818 1938 log_printf(TRACE,Decod,"instruction_l_sfgtsi"," * instruction : l.sfgtsi"); 1819 1939 1820 inst->_type = TYPE_TEST;1821 inst->_operation = OPERATION_TEST_L_SFGTS;1940 inst->_type = instruction_information(INSTRUCTION_L_SFGTSI)._type ; //TYPE_TEST; 1941 inst->_operation = instruction_information(INSTRUCTION_L_SFGTSI)._operation; //OPERATION_TEST_L_SFGTS; 1822 1942 inst->_has_immediat = 1; 1823 1943 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1833 1953 inst->_num_reg_re = SPR_LOGIC_SR_F; 1834 1954 inst->_exception_use = EXCEPTION_USE_NONE; 1835 // inst->_branch_condition = ; 1836 // inst->_branch_stack_write = ; 1837 // inst->_branch_direction = ; 1838 // inst->_address_next = ; 1955 inst->_exception = EXCEPTION_DECOD_NONE; 1956 // inst->_branch_condition = ; 1957 // inst->_branch_stack_write = ; 1958 // inst->_branch_direction = ; 1959 // inst->_address_next = ; 1960 inst->_no_execute = 0; 1839 1961 inst->_event_type = EVENT_TYPE_NONE; 1840 1962 } … … 1844 1966 log_printf(TRACE,Decod,"instruction_l_sfgtu"," * instruction : l.sfgtu"); 1845 1967 1846 inst->_type = TYPE_TEST;1847 inst->_operation = OPERATION_TEST_L_SFGTU;1968 inst->_type = instruction_information(INSTRUCTION_L_SFGTU)._type ; //TYPE_TEST; 1969 inst->_operation = instruction_information(INSTRUCTION_L_SFGTU)._operation; //OPERATION_TEST_L_SFGTU; 1848 1970 inst->_has_immediat = 0; 1849 1971 // inst->_immediat = ; … … 1859 1981 inst->_num_reg_re = SPR_LOGIC_SR_F; 1860 1982 inst->_exception_use = EXCEPTION_USE_NONE; 1861 // inst->_branch_condition = ; 1862 // inst->_branch_stack_write = ; 1863 // inst->_branch_direction = ; 1864 // inst->_address_next = ; 1983 inst->_exception = EXCEPTION_DECOD_NONE; 1984 // inst->_branch_condition = ; 1985 // inst->_branch_stack_write = ; 1986 // inst->_branch_direction = ; 1987 // inst->_address_next = ; 1988 inst->_no_execute = 0; 1865 1989 inst->_event_type = EVENT_TYPE_NONE; 1866 1990 } … … 1870 1994 log_printf(TRACE,Decod,"instruction_l_sfgtui"," * instruction : l.sfgtui"); 1871 1995 1872 inst->_type = TYPE_TEST;1873 inst->_operation = OPERATION_TEST_L_SFGTU;1996 inst->_type = instruction_information(INSTRUCTION_L_SFGTUI)._type ; //TYPE_TEST; 1997 inst->_operation = instruction_information(INSTRUCTION_L_SFGTUI)._operation; //OPERATION_TEST_L_SFGTU; 1874 1998 inst->_has_immediat = 1; 1875 1999 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1885 2009 inst->_num_reg_re = SPR_LOGIC_SR_F; 1886 2010 inst->_exception_use = EXCEPTION_USE_NONE; 1887 // inst->_branch_condition = ; 1888 // inst->_branch_stack_write = ; 1889 // inst->_branch_direction = ; 1890 // inst->_address_next = ; 2011 inst->_exception = EXCEPTION_DECOD_NONE; 2012 // inst->_branch_condition = ; 2013 // inst->_branch_stack_write = ; 2014 // inst->_branch_direction = ; 2015 // inst->_address_next = ; 2016 inst->_no_execute = 0; 1891 2017 inst->_event_type = EVENT_TYPE_NONE; 1892 2018 } … … 1896 2022 log_printf(TRACE,Decod,"instruction_l_sfles"," * instruction : l.sfles"); 1897 2023 1898 inst->_type = TYPE_TEST;1899 inst->_operation = OPERATION_TEST_L_SFLES;2024 inst->_type = instruction_information(INSTRUCTION_L_SFLES)._type ; //TYPE_TEST; 2025 inst->_operation = instruction_information(INSTRUCTION_L_SFLES)._operation; //OPERATION_TEST_L_SFLES; 1900 2026 inst->_has_immediat = 0; 1901 2027 // inst->_immediat = ; … … 1911 2037 inst->_num_reg_re = SPR_LOGIC_SR_F; 1912 2038 inst->_exception_use = EXCEPTION_USE_NONE; 1913 // inst->_branch_condition = ; 1914 // inst->_branch_stack_write = ; 1915 // inst->_branch_direction = ; 1916 // inst->_address_next = ; 2039 inst->_exception = EXCEPTION_DECOD_NONE; 2040 // inst->_branch_condition = ; 2041 // inst->_branch_stack_write = ; 2042 // inst->_branch_direction = ; 2043 // inst->_address_next = ; 2044 inst->_no_execute = 0; 1917 2045 inst->_event_type = EVENT_TYPE_NONE; 1918 2046 } … … 1922 2050 log_printf(TRACE,Decod,"instruction_l_sflesi"," * instruction : l.sflesi"); 1923 2051 1924 inst->_type = TYPE_TEST;1925 inst->_operation = OPERATION_TEST_L_SFLES;2052 inst->_type = instruction_information(INSTRUCTION_L_SFLESI)._type ; //TYPE_TEST; 2053 inst->_operation = instruction_information(INSTRUCTION_L_SFLESI)._operation; //OPERATION_TEST_L_SFLES; 1926 2054 inst->_has_immediat = 1; 1927 2055 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1937 2065 inst->_num_reg_re = SPR_LOGIC_SR_F; 1938 2066 inst->_exception_use = EXCEPTION_USE_NONE; 1939 // inst->_branch_condition = ; 1940 // inst->_branch_stack_write = ; 1941 // inst->_branch_direction = ; 1942 // inst->_address_next = ; 2067 inst->_exception = EXCEPTION_DECOD_NONE; 2068 // inst->_branch_condition = ; 2069 // inst->_branch_stack_write = ; 2070 // inst->_branch_direction = ; 2071 // inst->_address_next = ; 2072 inst->_no_execute = 0; 1943 2073 inst->_event_type = EVENT_TYPE_NONE; 1944 2074 } … … 1948 2078 log_printf(TRACE,Decod,"instruction_l_sfleu"," * instruction : l.sfleu"); 1949 2079 1950 inst->_type = TYPE_TEST;1951 inst->_operation = OPERATION_TEST_L_SFLEU;2080 inst->_type = instruction_information(INSTRUCTION_L_SFLEU)._type ; //TYPE_TEST; 2081 inst->_operation = instruction_information(INSTRUCTION_L_SFLEU)._operation; //OPERATION_TEST_L_SFLEU; 1952 2082 inst->_has_immediat = 0; 1953 2083 // inst->_immediat = ; … … 1963 2093 inst->_num_reg_re = SPR_LOGIC_SR_F; 1964 2094 inst->_exception_use = EXCEPTION_USE_NONE; 1965 // inst->_branch_condition = ; 1966 // inst->_branch_stack_write = ; 1967 // inst->_branch_direction = ; 1968 // inst->_address_next = ; 2095 inst->_exception = EXCEPTION_DECOD_NONE; 2096 // inst->_branch_condition = ; 2097 // inst->_branch_stack_write = ; 2098 // inst->_branch_direction = ; 2099 // inst->_address_next = ; 2100 inst->_no_execute = 0; 1969 2101 inst->_event_type = EVENT_TYPE_NONE; 1970 2102 } … … 1974 2106 log_printf(TRACE,Decod,"instruction_l_sfleui"," * instruction : l.sfleui"); 1975 2107 1976 inst->_type = TYPE_TEST;1977 inst->_operation = OPERATION_TEST_L_SFLEU;2108 inst->_type = instruction_information(INSTRUCTION_L_SFLEUI)._type ; //TYPE_TEST; 2109 inst->_operation = instruction_information(INSTRUCTION_L_SFLEUI)._operation; //OPERATION_TEST_L_SFLEU; 1978 2110 inst->_has_immediat = 1; 1979 2111 inst->_immediat = EXTENDS(inst->_instruction,16); … … 1989 2121 inst->_num_reg_re = SPR_LOGIC_SR_F; 1990 2122 inst->_exception_use = EXCEPTION_USE_NONE; 1991 // inst->_branch_condition = ; 1992 // inst->_branch_stack_write = ; 1993 // inst->_branch_direction = ; 1994 // inst->_address_next = ; 2123 inst->_exception = EXCEPTION_DECOD_NONE; 2124 // inst->_branch_condition = ; 2125 // inst->_branch_stack_write = ; 2126 // inst->_branch_direction = ; 2127 // inst->_address_next = ; 2128 inst->_no_execute = 0; 1995 2129 inst->_event_type = EVENT_TYPE_NONE; 1996 2130 } … … 2000 2134 log_printf(TRACE,Decod,"instruction_l_sflts"," * instruction : l.sflts"); 2001 2135 2002 inst->_type = TYPE_TEST;2003 inst->_operation = OPERATION_TEST_L_SFLTS;2136 inst->_type = instruction_information(INSTRUCTION_L_SFLTS)._type ; //TYPE_TEST; 2137 inst->_operation = instruction_information(INSTRUCTION_L_SFLTS)._operation; //OPERATION_TEST_L_SFLTS; 2004 2138 inst->_has_immediat = 0; 2005 2139 // inst->_immediat = ; … … 2015 2149 inst->_num_reg_re = SPR_LOGIC_SR_F; 2016 2150 inst->_exception_use = EXCEPTION_USE_NONE; 2017 // inst->_branch_condition = ; 2018 // inst->_branch_stack_write = ; 2019 // inst->_branch_direction = ; 2020 // inst->_address_next = ; 2151 inst->_exception = EXCEPTION_DECOD_NONE; 2152 // inst->_branch_condition = ; 2153 // inst->_branch_stack_write = ; 2154 // inst->_branch_direction = ; 2155 // inst->_address_next = ; 2156 inst->_no_execute = 0; 2021 2157 inst->_event_type = EVENT_TYPE_NONE; 2022 2158 } … … 2026 2162 log_printf(TRACE,Decod,"instruction_l_sfltsi"," * instruction : l.sfltsi"); 2027 2163 2028 inst->_type = TYPE_TEST;2029 inst->_operation = OPERATION_TEST_L_SFLTS;2164 inst->_type = instruction_information(INSTRUCTION_L_SFLTSI)._type ; //TYPE_TEST; 2165 inst->_operation = instruction_information(INSTRUCTION_L_SFLTSI)._operation; //OPERATION_TEST_L_SFLTS; 2030 2166 inst->_has_immediat = 1; 2031 2167 inst->_immediat = EXTENDS(inst->_instruction,16); … … 2041 2177 inst->_num_reg_re = SPR_LOGIC_SR_F; 2042 2178 inst->_exception_use = EXCEPTION_USE_NONE; 2043 // inst->_branch_condition = ; 2044 // inst->_branch_stack_write = ; 2045 // inst->_branch_direction = ; 2046 // inst->_address_next = ; 2179 inst->_exception = EXCEPTION_DECOD_NONE; 2180 // inst->_branch_condition = ; 2181 // inst->_branch_stack_write = ; 2182 // inst->_branch_direction = ; 2183 // inst->_address_next = ; 2184 inst->_no_execute = 0; 2047 2185 inst->_event_type = EVENT_TYPE_NONE; 2048 2186 } … … 2052 2190 log_printf(TRACE,Decod,"instruction_l_sfltu"," * instruction : l.sfltu"); 2053 2191 2054 inst->_type = TYPE_TEST;2055 inst->_operation = OPERATION_TEST_L_SFLTU;2192 inst->_type = instruction_information(INSTRUCTION_L_SFLTU)._type ; //TYPE_TEST; 2193 inst->_operation = instruction_information(INSTRUCTION_L_SFLTU)._operation; //OPERATION_TEST_L_SFLTU; 2056 2194 inst->_has_immediat = 0; 2057 2195 // inst->_immediat = ; … … 2067 2205 inst->_num_reg_re = SPR_LOGIC_SR_F; 2068 2206 inst->_exception_use = EXCEPTION_USE_NONE; 2069 // inst->_branch_condition = ; 2070 // inst->_branch_stack_write = ; 2071 // inst->_branch_direction = ; 2072 // inst->_address_next = ; 2207 inst->_exception = EXCEPTION_DECOD_NONE; 2208 // inst->_branch_condition = ; 2209 // inst->_branch_stack_write = ; 2210 // inst->_branch_direction = ; 2211 // inst->_address_next = ; 2212 inst->_no_execute = 0; 2073 2213 inst->_event_type = EVENT_TYPE_NONE; 2074 2214 } … … 2078 2218 log_printf(TRACE,Decod,"instruction_l_sfltui"," * instruction : l.sfltui"); 2079 2219 2080 inst->_type = TYPE_TEST;2081 inst->_operation = OPERATION_TEST_L_SFLTU;2220 inst->_type = instruction_information(INSTRUCTION_L_SFLTUI)._type ; //TYPE_TEST; 2221 inst->_operation = instruction_information(INSTRUCTION_L_SFLTUI)._operation; //OPERATION_TEST_L_SFLTU; 2082 2222 inst->_has_immediat = 1; 2083 2223 inst->_immediat = EXTENDS(inst->_instruction,16); … … 2093 2233 inst->_num_reg_re = SPR_LOGIC_SR_F; 2094 2234 inst->_exception_use = EXCEPTION_USE_NONE; 2095 // inst->_branch_condition = ; 2096 // inst->_branch_stack_write = ; 2097 // inst->_branch_direction = ; 2098 // inst->_address_next = ; 2235 inst->_exception = EXCEPTION_DECOD_NONE; 2236 // inst->_branch_condition = ; 2237 // inst->_branch_stack_write = ; 2238 // inst->_branch_direction = ; 2239 // inst->_address_next = ; 2240 inst->_no_execute = 0; 2099 2241 inst->_event_type = EVENT_TYPE_NONE; 2100 2242 } … … 2104 2246 log_printf(TRACE,Decod,"instruction_l_sfne"," * instruction : l.sfne"); 2105 2247 2106 inst->_type = TYPE_TEST;2107 inst->_operation = OPERATION_TEST_L_SFNE;2248 inst->_type = instruction_information(INSTRUCTION_L_SFNE)._type ; //TYPE_TEST; 2249 inst->_operation = instruction_information(INSTRUCTION_L_SFNE)._operation; //OPERATION_TEST_L_SFNE; 2108 2250 inst->_has_immediat = 0; 2109 2251 // inst->_immediat = ; … … 2119 2261 inst->_num_reg_re = SPR_LOGIC_SR_F; 2120 2262 inst->_exception_use = EXCEPTION_USE_NONE; 2121 // inst->_branch_condition = ; 2122 // inst->_branch_stack_write = ; 2123 // inst->_branch_direction = ; 2124 // inst->_address_next = ; 2263 inst->_exception = EXCEPTION_DECOD_NONE; 2264 // inst->_branch_condition = ; 2265 // inst->_branch_stack_write = ; 2266 // inst->_branch_direction = ; 2267 // inst->_address_next = ; 2268 inst->_no_execute = 0; 2125 2269 inst->_event_type = EVENT_TYPE_NONE; 2126 2270 } … … 2130 2274 log_printf(TRACE,Decod,"instruction_l_sfnei"," * instruction : l.sfnei"); 2131 2275 2132 inst->_type = TYPE_TEST;2133 inst->_operation = OPERATION_TEST_L_SFNE;2276 inst->_type = instruction_information(INSTRUCTION_L_SFNEI)._type ; //TYPE_TEST; 2277 inst->_operation = instruction_information(INSTRUCTION_L_SFNEI)._operation; //OPERATION_TEST_L_SFNE; 2134 2278 inst->_has_immediat = 1; 2135 2279 inst->_immediat = EXTENDS(inst->_instruction,16); … … 2145 2289 inst->_num_reg_re = SPR_LOGIC_SR_F; 2146 2290 inst->_exception_use = EXCEPTION_USE_NONE; 2147 // inst->_branch_condition = ; 2148 // inst->_branch_stack_write = ; 2149 // inst->_branch_direction = ; 2150 // inst->_address_next = ; 2291 inst->_exception = EXCEPTION_DECOD_NONE; 2292 // inst->_branch_condition = ; 2293 // inst->_branch_stack_write = ; 2294 // inst->_branch_direction = ; 2295 // inst->_address_next = ; 2296 inst->_no_execute = 0; 2151 2297 inst->_event_type = EVENT_TYPE_NONE; 2152 2298 } … … 2156 2302 log_printf(TRACE,Decod,"instruction_l_sh"," * instruction : l.sh"); 2157 2303 2158 inst->_type = TYPE_MEMORY;2159 inst->_operation = OPERATION_MEMORY_STORE_16;2304 inst->_type = instruction_information(INSTRUCTION_L_SH)._type ; //TYPE_MEMORY; 2305 inst->_operation = instruction_information(INSTRUCTION_L_SH)._operation; //OPERATION_MEMORY_STORE_16; 2160 2306 inst->_has_immediat = 1; 2161 2307 inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| … … 2172 2318 // inst->_num_reg_re = ; 2173 2319 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 2174 // inst->_branch_condition = ; 2175 // inst->_branch_stack_write = ; 2176 // inst->_branch_direction = ; 2177 // inst->_address_next = ; 2320 inst->_exception = EXCEPTION_DECOD_NONE; 2321 // inst->_branch_condition = ; 2322 // inst->_branch_stack_write = ; 2323 // inst->_branch_direction = ; 2324 // inst->_address_next = ; 2325 inst->_no_execute = 0; 2178 2326 inst->_event_type = EVENT_TYPE_NONE; 2179 2327 } … … 2183 2331 log_printf(TRACE,Decod,"instruction_l_sll"," * instruction : l.sll"); 2184 2332 2185 inst->_type = TYPE_SHIFT; 2186 inst->_operation = OPERATION_SHIFT_L_SLL; 2187 inst->_has_immediat = 0; 2188 // inst->_immediat = ; 2189 inst->_read_ra = 1; 2190 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2191 inst->_read_rb = 1; 2192 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2193 inst->_read_rc = 0; 2194 // inst->_num_reg_rc = ; 2195 inst->_write_rd = 1; 2196 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2197 inst->_write_re = 0; 2198 // inst->_num_reg_re = ; 2199 inst->_exception_use = EXCEPTION_USE_NONE; 2200 // inst->_branch_condition = ; 2201 // inst->_branch_stack_write = ; 2202 // inst->_branch_direction = ; 2203 // inst->_address_next = ; 2333 inst->_type = instruction_information(INSTRUCTION_L_SLL)._type ; //TYPE_SHIFT; 2334 inst->_operation = instruction_information(INSTRUCTION_L_SLL)._operation; //OPERATION_SHIFT_L_SLL; 2335 inst->_has_immediat = 0; 2336 // inst->_immediat = ; 2337 inst->_read_ra = 1; 2338 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2339 inst->_read_rb = 1; 2340 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2341 inst->_read_rc = 0; 2342 // inst->_num_reg_rc = ; 2343 inst->_write_rd = 1; 2344 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2345 inst->_write_re = 0; 2346 // inst->_num_reg_re = ; 2347 inst->_exception_use = EXCEPTION_USE_NONE; 2348 inst->_exception = EXCEPTION_DECOD_NONE; 2349 // inst->_branch_condition = ; 2350 // inst->_branch_stack_write = ; 2351 // inst->_branch_direction = ; 2352 // inst->_address_next = ; 2353 inst->_no_execute = 0; 2204 2354 inst->_event_type = EVENT_TYPE_NONE; 2205 2355 } … … 2209 2359 log_printf(TRACE,Decod,"instruction_l_slli"," * instruction : l.slli"); 2210 2360 2211 inst->_type = TYPE_SHIFT;2212 inst->_operation = OPERATION_SHIFT_L_SLL;2361 inst->_type = instruction_information(INSTRUCTION_L_SLLI)._type ; //TYPE_SHIFT; 2362 inst->_operation = instruction_information(INSTRUCTION_L_SLLI)._operation; //OPERATION_SHIFT_L_SLL; 2213 2363 inst->_has_immediat = 1; 2214 2364 inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); … … 2224 2374 // inst->_num_reg_re = ; 2225 2375 inst->_exception_use = EXCEPTION_USE_NONE; 2226 // inst->_branch_condition = ; 2227 // inst->_branch_stack_write = ; 2228 // inst->_branch_direction = ; 2229 // inst->_address_next = ; 2376 inst->_exception = EXCEPTION_DECOD_NONE; 2377 // inst->_branch_condition = ; 2378 // inst->_branch_stack_write = ; 2379 // inst->_branch_direction = ; 2380 // inst->_address_next = ; 2381 inst->_no_execute = 0; 2230 2382 inst->_event_type = EVENT_TYPE_NONE; 2231 2383 } … … 2235 2387 log_printf(TRACE,Decod,"instruction_l_sra"," * instruction : l.sra"); 2236 2388 2237 inst->_type = TYPE_SHIFT; 2238 inst->_operation = OPERATION_SHIFT_L_SRA; 2239 inst->_has_immediat = 0; 2240 // inst->_immediat = ; 2241 inst->_read_ra = 1; 2242 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2243 inst->_read_rb = 1; 2244 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2245 inst->_read_rc = 0; 2246 // inst->_num_reg_rc = ; 2247 inst->_write_rd = 1; 2248 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2249 inst->_write_re = 0; 2250 // inst->_num_reg_re = ; 2251 inst->_exception_use = EXCEPTION_USE_NONE; 2252 // inst->_branch_condition = ; 2253 // inst->_branch_stack_write = ; 2254 // inst->_branch_direction = ; 2255 // inst->_address_next = ; 2389 inst->_type = instruction_information(INSTRUCTION_L_SRA)._type ; //TYPE_SHIFT; 2390 inst->_operation = instruction_information(INSTRUCTION_L_SRA)._operation; //OPERATION_SHIFT_L_SRA; 2391 inst->_has_immediat = 0; 2392 // inst->_immediat = ; 2393 inst->_read_ra = 1; 2394 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2395 inst->_read_rb = 1; 2396 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2397 inst->_read_rc = 0; 2398 // inst->_num_reg_rc = ; 2399 inst->_write_rd = 1; 2400 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2401 inst->_write_re = 0; 2402 // inst->_num_reg_re = ; 2403 inst->_exception_use = EXCEPTION_USE_NONE; 2404 inst->_exception = EXCEPTION_DECOD_NONE; 2405 // inst->_branch_condition = ; 2406 // inst->_branch_stack_write = ; 2407 // inst->_branch_direction = ; 2408 // inst->_address_next = ; 2409 inst->_no_execute = 0; 2256 2410 inst->_event_type = EVENT_TYPE_NONE; 2257 2411 } … … 2261 2415 log_printf(TRACE,Decod,"instruction_l_srai"," * instruction : l.srai"); 2262 2416 2263 inst->_type = TYPE_SHIFT;2264 inst->_operation = OPERATION_SHIFT_L_SRA;2417 inst->_type = instruction_information(INSTRUCTION_L_SRAI)._type ; //TYPE_SHIFT; 2418 inst->_operation = instruction_information(INSTRUCTION_L_SRAI)._operation; //OPERATION_SHIFT_L_SRA; 2265 2419 inst->_has_immediat = 1; 2266 2420 inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); … … 2276 2430 // inst->_num_reg_re = ; 2277 2431 inst->_exception_use = EXCEPTION_USE_NONE; 2278 // inst->_branch_condition = ; 2279 // inst->_branch_stack_write = ; 2280 // inst->_branch_direction = ; 2281 // inst->_address_next = ; 2432 inst->_exception = EXCEPTION_DECOD_NONE; 2433 // inst->_branch_condition = ; 2434 // inst->_branch_stack_write = ; 2435 // inst->_branch_direction = ; 2436 // inst->_address_next = ; 2437 inst->_no_execute = 0; 2282 2438 inst->_event_type = EVENT_TYPE_NONE; 2283 2439 } … … 2287 2443 log_printf(TRACE,Decod,"instruction_l_srl"," * instruction : l.srl"); 2288 2444 2289 inst->_type = TYPE_SHIFT; 2290 inst->_operation = OPERATION_SHIFT_L_SRL; 2291 inst->_has_immediat = 0; 2292 // inst->_immediat = ; 2293 inst->_read_ra = 1; 2294 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2295 inst->_read_rb = 1; 2296 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2297 inst->_read_rc = 0; 2298 // inst->_num_reg_rc = ; 2299 inst->_write_rd = 1; 2300 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2301 inst->_write_re = 0; 2302 // inst->_num_reg_re = ; 2303 inst->_exception_use = EXCEPTION_USE_NONE; 2304 // inst->_branch_condition = ; 2305 // inst->_branch_stack_write = ; 2306 // inst->_branch_direction = ; 2307 // inst->_address_next = ; 2445 inst->_type = instruction_information(INSTRUCTION_L_SRL)._type ; //TYPE_SHIFT; 2446 inst->_operation = instruction_information(INSTRUCTION_L_SRL)._operation; //OPERATION_SHIFT_L_SRL; 2447 inst->_has_immediat = 0; 2448 // inst->_immediat = ; 2449 inst->_read_ra = 1; 2450 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2451 inst->_read_rb = 1; 2452 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2453 inst->_read_rc = 0; 2454 // inst->_num_reg_rc = ; 2455 inst->_write_rd = 1; 2456 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2457 inst->_write_re = 0; 2458 // inst->_num_reg_re = ; 2459 inst->_exception_use = EXCEPTION_USE_NONE; 2460 inst->_exception = EXCEPTION_DECOD_NONE; 2461 // inst->_branch_condition = ; 2462 // inst->_branch_stack_write = ; 2463 // inst->_branch_direction = ; 2464 // inst->_address_next = ; 2465 inst->_no_execute = 0; 2308 2466 inst->_event_type = EVENT_TYPE_NONE; 2309 2467 } … … 2313 2471 log_printf(TRACE,Decod,"instruction_l_srli"," * instruction : l.srli"); 2314 2472 2315 inst->_type = TYPE_SHIFT;2316 inst->_operation = OPERATION_SHIFT_L_SRL;2473 inst->_type = instruction_information(INSTRUCTION_L_SRLI)._type ; //TYPE_SHIFT; 2474 inst->_operation = instruction_information(INSTRUCTION_L_SRLI)._operation; //OPERATION_SHIFT_L_SRL; 2317 2475 inst->_has_immediat = 1; 2318 2476 inst->_immediat = range<Tgeneral_data_t >(inst->_instruction, 5, 0); … … 2328 2486 // inst->_num_reg_re = ; 2329 2487 inst->_exception_use = EXCEPTION_USE_NONE; 2330 // inst->_branch_condition = ; 2331 // inst->_branch_stack_write = ; 2332 // inst->_branch_direction = ; 2333 // inst->_address_next = ; 2488 inst->_exception = EXCEPTION_DECOD_NONE; 2489 // inst->_branch_condition = ; 2490 // inst->_branch_stack_write = ; 2491 // inst->_branch_direction = ; 2492 // inst->_address_next = ; 2493 inst->_no_execute = 0; 2334 2494 inst->_event_type = EVENT_TYPE_NONE; 2335 2495 } … … 2339 2499 log_printf(TRACE,Decod,"instruction_l_sub"," * instruction : l.sub"); 2340 2500 2341 inst->_type = TYPE_ALU;2342 inst->_operation = OPERATION_ALU_L_SUB;2501 inst->_type = instruction_information(INSTRUCTION_L_SUB)._type ; //TYPE_ALU; 2502 inst->_operation = instruction_information(INSTRUCTION_L_SUB)._operation; //OPERATION_ALU_L_SUB; 2343 2503 inst->_has_immediat = 0; 2344 2504 // inst->_immediat = ; … … 2354 2514 inst->_num_reg_re = SPR_LOGIC_SR_CY_OV; 2355 2515 inst->_exception_use = EXCEPTION_USE_RANGE; 2356 // inst->_branch_condition = ; 2357 // inst->_branch_stack_write = ; 2358 // inst->_branch_direction = ; 2359 // inst->_address_next = ; 2516 inst->_exception = EXCEPTION_DECOD_NONE; 2517 // inst->_branch_condition = ; 2518 // inst->_branch_stack_write = ; 2519 // inst->_branch_direction = ; 2520 // inst->_address_next = ; 2521 inst->_no_execute = 0; 2360 2522 inst->_event_type = EVENT_TYPE_NONE; 2361 2523 } … … 2365 2527 log_printf(TRACE,Decod,"instruction_l_sw"," * instruction : l.sw"); 2366 2528 2367 inst->_type = TYPE_MEMORY;2368 inst->_operation = OPERATION_MEMORY_STORE_32;2529 inst->_type = instruction_information(INSTRUCTION_L_SW)._type ; //TYPE_MEMORY; 2530 inst->_operation = instruction_information(INSTRUCTION_L_SW)._operation; //OPERATION_MEMORY_STORE_32; 2369 2531 inst->_has_immediat = 1; 2370 2532 inst->_immediat = EXTENDS(((range<Tgeneral_data_t >(inst->_instruction,25,21)<<11)| … … 2381 2543 // inst->_num_reg_re = ; 2382 2544 inst->_exception_use = EXCEPTION_USE_MEMORY_WITH_ALIGNMENT; 2383 // inst->_branch_condition = ; 2384 // inst->_branch_stack_write = ; 2385 // inst->_branch_direction = ; 2386 // inst->_address_next = ; 2545 inst->_exception = EXCEPTION_DECOD_NONE; 2546 // inst->_branch_condition = ; 2547 // inst->_branch_stack_write = ; 2548 // inst->_branch_direction = ; 2549 // inst->_address_next = ; 2550 inst->_no_execute = 0; 2387 2551 inst->_event_type = EVENT_TYPE_NONE; 2388 2552 } … … 2398 2562 else 2399 2563 { 2400 inst->_type = TYPE_SPECIAL;2401 inst->_operation = OPERATION_SPECIAL_L_SYS;2564 inst->_type = instruction_information(INSTRUCTION_L_SYS)._type ; //TYPE_SPECIAL; 2565 inst->_operation = instruction_information(INSTRUCTION_L_SYS)._operation; //OPERATION_SPECIAL_L_SYS; 2402 2566 // inst->_has_immediat = 1; 2403 2567 // inst->_immediat = EXTENDZ(inst->_instruction,16); … … 2415 2579 // inst->_num_reg_re = ; 2416 2580 inst->_exception_use = EXCEPTION_USE_SYSCALL; 2581 inst->_exception = EXCEPTION_SYSCALL; 2417 2582 // inst->_branch_condition = ; 2418 2583 // inst->_branch_stack_write = ; … … 2426 2591 2427 2592 // inst->_address_next = ; // don't change 2593 inst->_no_execute = 1; 2428 2594 inst->_event_type = EVENT_TYPE_EXCEPTION; 2429 2595 } … … 2440 2606 else 2441 2607 { 2442 inst->_type = TYPE_SPECIAL;2443 inst->_operation = OPERATION_SPECIAL_L_TRAP;2608 inst->_type = instruction_information(INSTRUCTION_L_TRAP)._type ; //TYPE_SPECIAL; 2609 inst->_operation = instruction_information(INSTRUCTION_L_TRAP)._operation; //OPERATION_SPECIAL_L_TRAP; 2444 2610 inst->_has_immediat = 1; 2445 2611 inst->_immediat = EXTENDZ(inst->_instruction,16); … … 2455 2621 // inst->_num_reg_re = ; 2456 2622 inst->_exception_use = EXCEPTION_USE_TRAP; 2457 // inst->_branch_condition = ; 2458 // inst->_branch_stack_write = ; 2459 // inst->_branch_direction = ; 2460 // inst->_address_next = ; 2623 inst->_exception = EXCEPTION_DECOD_NONE; 2624 // inst->_branch_condition = ; 2625 // inst->_branch_stack_write = ; 2626 // inst->_branch_direction = ; 2627 // inst->_address_next = ; 2628 inst->_no_execute = 1; 2461 2629 inst->_event_type = EVENT_TYPE_NONE; 2462 2630 } … … 2467 2635 log_printf(TRACE,Decod,"instruction_l_xor"," * instruction : l.xor"); 2468 2636 2469 inst->_type = TYPE_ALU; 2470 inst->_operation = OPERATION_ALU_L_XOR; 2471 inst->_has_immediat = 0; 2472 // inst->_immediat = ; 2473 inst->_read_ra = 1; 2474 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2475 inst->_read_rb = 1; 2476 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2477 inst->_read_rc = 0; 2478 // inst->_num_reg_rc = ; 2479 inst->_write_rd = 1; 2480 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2481 inst->_write_re = 0; 2482 // inst->_num_reg_re = ; 2483 inst->_exception_use = EXCEPTION_USE_NONE; 2484 // inst->_branch_condition = ; 2485 // inst->_branch_stack_write = ; 2486 // inst->_branch_direction = ; 2487 // inst->_address_next = ; 2637 inst->_type = instruction_information(INSTRUCTION_L_XOR)._type ; //TYPE_ALU; 2638 inst->_operation = instruction_information(INSTRUCTION_L_XOR)._operation; //OPERATION_ALU_L_XOR; 2639 inst->_has_immediat = 0; 2640 // inst->_immediat = ; 2641 inst->_read_ra = 1; 2642 inst->_num_reg_ra = range<Tgeneral_address_t>(inst->_instruction,20,16); 2643 inst->_read_rb = 1; 2644 inst->_num_reg_rb = range<Tgeneral_address_t>(inst->_instruction,15,11); 2645 inst->_read_rc = 0; 2646 // inst->_num_reg_rc = ; 2647 inst->_write_rd = 1; 2648 inst->_num_reg_rd = range<Tgeneral_address_t>(inst->_instruction,25,21); 2649 inst->_write_re = 0; 2650 // inst->_num_reg_re = ; 2651 inst->_exception_use = EXCEPTION_USE_NONE; 2652 inst->_exception = EXCEPTION_DECOD_NONE; 2653 // inst->_branch_condition = ; 2654 // inst->_branch_stack_write = ; 2655 // inst->_branch_direction = ; 2656 // inst->_address_next = ; 2657 inst->_no_execute = 0; 2488 2658 inst->_event_type = EVENT_TYPE_NONE; 2489 2659 } … … 2493 2663 log_printf(TRACE,Decod,"instruction_l_xori"," * instruction : l.xori"); 2494 2664 2495 inst->_type = TYPE_ALU;2496 inst->_operation = OPERATION_ALU_L_XOR;2665 inst->_type = instruction_information(INSTRUCTION_L_XORI)._type ; //TYPE_ALU; 2666 inst->_operation = instruction_information(INSTRUCTION_L_XORI)._operation; //OPERATION_ALU_L_XOR; 2497 2667 inst->_has_immediat = 1; 2498 2668 inst->_immediat = EXTENDS(inst->_instruction,16); … … 2508 2678 // inst->_num_reg_re = ; 2509 2679 inst->_exception_use = EXCEPTION_USE_NONE; 2510 // inst->_branch_condition = ; 2511 // inst->_branch_stack_write = ; 2512 // inst->_branch_direction = ; 2513 // inst->_address_next = ; 2680 inst->_exception = EXCEPTION_DECOD_NONE; 2681 // inst->_branch_condition = ; 2682 // inst->_branch_stack_write = ; 2683 // inst->_branch_direction = ; 2684 // inst->_address_next = ; 2685 inst->_no_execute = 0; 2514 2686 inst->_event_type = EVENT_TYPE_NONE; 2515 2687 }
Note: See TracChangeset
for help on using the changeset viewer.