Ignore:
Timestamp:
Dec 10, 2008, 7:31:39 PM (15 years ago)
Author:
rosiere
Message:

Almost complete design
with Test and test platform

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Ifetch_unit/Address_management/src/Address_management_transition.cpp

    r84 r88  
    2222  void Address_management::transition (void)
    2323  {
    24     log_printf(FUNC,Address_management,FUNCTION,"Begin");
     24    log_begin(Address_management,FUNCTION);
     25    log_function(Address_management,FUNCTION,_name.c_str());
    2526
    2627    if (PORT_READ(in_NRESET) == 0)
     
    2829        // nothing is valid
    2930        reg_PC_CURRENT_VAL   = 0;
    30         reg_PC_NEXT_VAL      = 0;
     31
     32        reg_PC_NEXT_VAL      = 1;
     33        reg_PC_NEXT          = 0x100>>2;
     34
    3135        reg_PC_NEXT_NEXT_VAL = 0;
    3236      }
     
    4044            for (uint32_t i=0; i<_param->_nb_instruction; i++)
    4145            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = PORT_READ(in_PREDICT_INSTRUCTION_ENABLE [i]);
    42             if (_param->_have_port_instruction_ptr)
     46            if (_param->_have_port_inst_ifetch_ptr)
    4347            reg_PC_NEXT_INST_IFETCH_PTR             = PORT_READ(in_PREDICT_INST_IFETCH_PTR            );
    4448            reg_PC_NEXT_BRANCH_STATE                = PORT_READ(in_PREDICT_BRANCH_STATE               );
    45             if (_param->_have_port_branch_update_prediction_id)
     49            if (_param->_have_port_depth)
    4650            reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = PORT_READ(in_PREDICT_BRANCH_UPDATE_PREDICTION_ID);
    4751           
     
    5155
    5256#ifdef STATISTICS
    53             (*_stat_nb_transaction_predict) ++;
     57            if (usage_is_set(_usage,USE_STATISTICS))
     58              (*_stat_nb_transaction_predict) ++;
    5459#endif
    5560          }
     
    6267          {
    6368#ifdef STATISTICS
    64             if (reg_PC_CURRENT_VAL)
    65               {
    66                 (*_stat_nb_transaction_address) ++;
    67 
    68                 for (uint32_t i=0; i<_param->_nb_instruction; i++)
    69                   if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
    70                     (*_stat_sum_packet_size) ++;
    71               }
     69            if (usage_is_set(_usage,USE_STATISTICS))
     70              if (reg_PC_CURRENT_VAL)
     71                {
     72                  (*_stat_nb_transaction_address) ++;
     73                 
     74                  for (uint32_t i=0; i<_param->_nb_instruction; i++)
     75                    if (reg_PC_CURRENT_INSTRUCTION_ENABLE [i] == true)
     76                      (*_stat_sum_packet_size) ++;
     77                }
    7278#endif
    7379
     
    110116        if (PORT_READ(in_EVENT_VAL) and internal_EVENT_ACK)
    111117          {
    112             log_printf(TRACE,Address_management,FUNCTION,"EVENT : Transaction");
     118            log_printf(TRACE,Address_management,FUNCTION,"  * EVENT : Transaction");
     119            log_printf(TRACE,Address_management,FUNCTION,"    * IS_DS_TAKE       : %d"  ,PORT_READ(in_EVENT_IS_DS_TAKE      ));
     120            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS          : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS         ),PORT_READ(in_EVENT_ADDRESS         )<<2);
     121            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT     : %.8x (%.8x)",PORT_READ(in_EVENT_ADDRESS_NEXT    ),PORT_READ(in_EVENT_ADDRESS_NEXT    )<<2);
     122            log_printf(TRACE,Address_management,FUNCTION,"    * ADDRESS_NEXT_VAL : %d"  ,PORT_READ(in_EVENT_ADDRESS_NEXT_VAL));
    113123            reg_PC_CURRENT_VAL                      = 0;
    114124            reg_PC_NEXT_VAL                         = 1;
     
    118128            //  * load   miss speculation : the load is execute, the event_address is the next address (also the destination of branch)
    119129            //  * exception               : goto the first instruction of exception handler (also is not in delay slot).
    120             reg_PC_NEXT_IS_DS_TAKE                  = 0;
     130
     131            reg_PC_NEXT_IS_DS_TAKE                  = PORT_READ(in_EVENT_IS_DS_TAKE);
    121132//          reg_PC_NEXT_INST_IFETCH_PTR             = 0;
    122133//          reg_PC_NEXT_BRANCH_STATE                = BRANCH_STATE_NONE;
    123134//          reg_PC_NEXT_BRANCH_UPDATE_PREDICTION_ID = 0;
    124135           
    125 //          reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
    126 //          for (uint32_t i=1; i<_param->_nb_instruction; i++)
    127 //            reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0;
     136            reg_PC_NEXT_INSTRUCTION_ENABLE [0]      = 1; // only the instruction at the event address is valid, because we have no information on the branch presence in the instruction bundle.
     137            for (uint32_t i=1; i<_param->_nb_instruction; i++)
     138              reg_PC_NEXT_INSTRUCTION_ENABLE [i] = 0;
    128139
    129             reg_PC_NEXT_NEXT_VAL                    = 0; // cancel all prediction (event is send at the predict unit)
     140            reg_PC_NEXT_NEXT_VAL                    = PORT_READ(in_EVENT_ADDRESS_NEXT_VAL);
     141            reg_PC_NEXT_NEXT                        = PORT_READ(in_EVENT_ADDRESS_NEXT);
     142            reg_PC_NEXT_NEXT_IS_DS_TAKE             = 0;//??
     143
     144            // Note : is_ds_take = address_next_val
     145            // Because, is not ds take, can continue in sequence
     146
     147#ifdef DEBUG_TEST
     148            if (PORT_READ(in_EVENT_ADDRESS_NEXT_VAL) and not PORT_READ(in_EVENT_IS_DS_TAKE))
     149              throw ERRORMORPHEO(FUNCTION,_("Event : address_next_next_val but next is not a ds take"));
     150#endif
    130151
    131152#ifdef STATISTICS
    132             (*_stat_nb_transaction_event) ++;
     153            if (usage_is_set(_usage,USE_STATISTICS))
     154              (*_stat_nb_transaction_event) ++;
    133155#endif
    134156          }
    135157      }
    136158
    137 #if DEBUG >= DEBUG_TRACE
    138     log_printf(TRACE,Address_management,FUNCTION,"Address_Management : ");
    139     log_printf(TRACE,Address_management,FUNCTION,"Current   : %d %d 0x%x",reg_PC_CURRENT_VAL, reg_PC_CURRENT_IS_DS_TAKE, reg_PC_CURRENT);
    140     log_printf(TRACE,Address_management,FUNCTION,"Next      : %d %d 0x%x",reg_PC_NEXT_VAL, reg_PC_NEXT_IS_DS_TAKE, reg_PC_NEXT);   
    141     log_printf(TRACE,Address_management,FUNCTION,"Next_Next : %d %d 0x%x",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT);   
     159#if defined(DEBUG) and (DEBUG >= DEBUG_TRACE)
     160    log_printf(TRACE,Address_management,FUNCTION,"  * Dump PC");
     161    log_printf(TRACE,Address_management,FUNCTION,"    * Current   : %d %d 0x%.8x (%.8x)",reg_PC_CURRENT_VAL  , reg_PC_CURRENT_IS_DS_TAKE  , reg_PC_CURRENT  , reg_PC_CURRENT  <<2);
     162    log_printf(TRACE,Address_management,FUNCTION,"    * Next      : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_VAL     , reg_PC_NEXT_IS_DS_TAKE     , reg_PC_NEXT     , reg_PC_NEXT     <<2);   
     163    log_printf(TRACE,Address_management,FUNCTION,"    * Next_Next : %d %d 0x%.8x (%.8x)",reg_PC_NEXT_NEXT_VAL, reg_PC_NEXT_NEXT_IS_DS_TAKE, reg_PC_NEXT_NEXT, reg_PC_NEXT_NEXT<<2);   
    142164#endif
    143165
     
    145167    end_cycle ();
    146168#endif
    147 
    148     log_printf(FUNC,Address_management,FUNCTION,"End");
     169   
     170    log_end(Address_management,FUNCTION);
    149171  };
    150172
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