Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp

Timestamp:

Dec 10, 2008, 7:31:39 PM (15 years ago)

Author:

rosiere

Message:

Almost complete design
with Test and test platform

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp (modified) (4 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/src/Branch_Target_Buffer_Register_transition.cpp

@@ -22 +22 @@
   void Branch_Target_Buffer_Register::transition (void)
   {
-    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"Begin");
+    log_begin(Branch_Target_Buffer_Register,FUNCTION);
+    log_function(Branch_Target_Buffer_Register,FUNCTION,_name.c_str());
 
     if (PORT_READ(in_NRESET) == 0)
@@ -83 +84 @@
           if (PORT_READ(in_UPDATE_VAL [i]) and internal_UPDATE_ACK [i])
             {
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"  * UPDATE [%d]",i);
+ 
               bool     hit       = internal_UPDATE_HIT      [i];
               uint32_t num_bank  = internal_UPDATE_NUM_BANK [i];
@@ -89 +92 @@
 
               // detect new branch !!! insert in branch target buffer
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * hit       : %d",hit);
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * num_bank  : %d",num_bank );
+              log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    * num_entry : %d",num_entry);
+
               Tcounter_t accurate_new = 0;
 
@@ -123 +130 @@
                   accurate_new =  (miss_pred)?_param->_first_accurate_if_miss:_param->_first_accurate_if_hit;
 
-                  reg_BTB[num_bank][num_entry]._val              = 1;
-                  reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
-                  reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
-                  reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
-                  reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
-                }
+//                reg_BTB[num_bank][num_entry]._val              = 1;
+//                reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
+//                reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
+//                reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
+//                reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
+                  reg_BTB[num_bank][num_entry]._address_dest_val = 0;
+                }
 
               // =====[ All Case ]
-              if (reg_BTB[num_bank][num_entry]._address_dest_val == 0)
-                {
-                  reg_BTB[num_bank][num_entry]._address_dest_val = 1;
-                  reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
-                }
+//            if (reg_BTB[num_bank][num_entry]._address_dest_val == 0)
+//              {
+//                reg_BTB[num_bank][num_entry]._address_dest_val = 1;
+//                reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
+//              }
+              reg_BTB[num_bank][num_entry]._val              = 1;
+              reg_BTB[num_bank][num_entry]._context          = (_param->_have_port_context_id)?PORT_READ(in_UPDATE_CONTEXT_ID [i]):0;
+              reg_BTB[num_bank][num_entry]._address_src      = PORT_READ(in_UPDATE_ADDRESS_SRC  [i]);
+              reg_BTB[num_bank][num_entry]._condition        = PORT_READ(in_UPDATE_CONDITION    [i]);
+              reg_BTB[num_bank][num_entry]._last_take        = PORT_READ(in_UPDATE_LAST_TAKE    [i]);
+              reg_BTB[num_bank][num_entry]._address_dest_val = 1;
+              reg_BTB[num_bank][num_entry]._address_dest     = PORT_READ(in_UPDATE_ADDRESS_DEST [i]);
               reg_BTB[num_bank][num_entry]._accurate         = accurate_new;
             }
 
+#if (DEBUG >= DEBUG_TRACE) and DEBUG_Branch_Target_Buffer_Register
+        log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"  * Dump BTB");
         for (uint32_t i=0; i<_param->_size_bank; i++)
           for (uint32_t j=0; j<_param->_associativity; j++)
-            log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"[%.4d][%.4d] %d - %.2d %.8x %.1d %.8x %.3d %.1d %.4d", 
+            log_printf(TRACE,Branch_Target_Buffer_Register,FUNCTION,"    [%.4d][%.4d] %d - %.4d %.8x (%.8x) %.1d %.8x (%.8x) %.3d %.1d %.4d", 
                        i,j,
                        reg_BTB [i][j]._val             ,
                        reg_BTB [i][j]._context         ,
                        reg_BTB [i][j]._address_src     ,
+                       reg_BTB [i][j]._address_src <<2,
                        reg_BTB [i][j]._address_dest_val,
                        reg_BTB [i][j]._address_dest    ,
+                       reg_BTB [i][j]._address_dest<<2 ,
                        reg_BTB [i][j]._condition       ,
                        reg_BTB [i][j]._last_take       ,
                        reg_BTB [i][j]._accurate        );
+#endif
       }
-    
+
 #if defined(STATISTICS) or defined(VHDL_TESTBENCH)
     end_cycle ();
 #endif
 
-    log_printf(FUNC,Branch_Target_Buffer_Register,FUNCTION,"End");
+    log_end(Branch_Target_Buffer_Register,FUNCTION);
   };