Changeset 88 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/src/test.cpp

Timestamp:

Dec 10, 2008, 7:31:39 PM (15 years ago)

Author:

rosiere

Message:

Almost complete design
with Test and test platform

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/src/test.cpp (modified) (5 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/src/test.cpp

@@ -7 +7 @@
  */
 
-#define NB_ITERATION  1024
-#define CYCLE_MAX     (128*NB_ITERATION)
+#define NB_ITERATION  1
+#define CYCLE_MAX     (10000*NB_ITERATION)
 
 #include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/SelfTest/include/test.h"
 #include "Common/include/Test.h"
 #include "Behavioural/include/Allocation.h"
+#include "Behavioural/Core/Multi_Front_end/Front_end/Prediction_unit/Branch_Target_Buffer/Branch_Target_Buffer_Register/SelfTest/include/test_BTB.h"
 
 void test (string name,
@@ -20 +21 @@
 
 #ifdef STATISTICS
-  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,50);
+  morpheo::behavioural::Parameters_Statistics * _parameters_statistics = new morpheo::behavioural::Parameters_Statistics (5,CYCLE_MAX);
 #endif
+
+  Tusage_t _usage = USE_ALL;
+
+//   _usage = usage_unset(_usage,USE_SYSTEMC              );
+//   _usage = usage_unset(_usage,USE_VHDL                 );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH       );
+//   _usage = usage_unset(_usage,USE_VHDL_TESTBENCH_ASSERT);
+//   _usage = usage_unset(_usage,USE_POSITION             );
+//   _usage = usage_unset(_usage,USE_STATISTICS           );
+//   _usage = usage_unset(_usage,USE_INFORMATION          );
 
   Branch_Target_Buffer * _Branch_Target_Buffer = new Branch_Target_Buffer 
@@ -29 +40 @@
 #endif
      _param,
-     USE_ALL);
-  
+     _usage);
+
 #ifdef SYSTEMC
   /*********************************************************************
@@ -110 +121 @@
   msg(_("<%s> : Start Simulation ............\n"),name.c_str());
     
+  // Initialisation
+  const uint32_t seed = 0;
+//const uint32_t seed = static_cast<uint32_t>(time(NULL));
+
+  srand(seed);
+
+  const  int32_t percent_transaction_decod   = 75;
+  const  int32_t percent_transaction_predict = 75;
+
+  SC_START(0);
+
   Time * _time = new Time();
 
@@ -116 +138 @@
    ********************************************************/
 
-  // Initialisation
-
-  const uint32_t seed = 0;
-//const uint32_t seed = static_cast<uint32_t>(time(NULL));
-
-  srand(seed);
-
-  SC_START(0);
-  LABEL("Initialisation");
-
-  LABEL("Reset");
-  in_NRESET->write(0);
-  SC_START(5);
-  in_NRESET->write(1);  
-
-  LABEL("Loop of Test");
-
-  for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
-    {
-      LABEL("Iteration %d",iteration);
-
-      SC_START(1);
-    }
+  {
+    LABEL("Reset");
+    in_NRESET->write(0);
+    SC_START(5);
+    in_NRESET->write(1);  
+    
+    LABEL("Loop of Test");
+    
+    Taddress_t btb_address [_param->_associativity];
+    Tcontext_t btb_context [_param->_associativity];
+
+    for (uint32_t iteration=0; iteration<NB_ITERATION; iteration ++)
+      {
+        LABEL("Iteration %d",iteration);
+
+        // FIRST STEP - Test (without sort, with concurent access, same context)
+
+        // fill a btb line
+#define NB_REQUEST (8*_param->_associativity)
+        uint32_t   nb_request;
+        uint32_t   index      = rand()&_param->_param_branch_target_buffer_register->_mask_bank;
+        Tcontext_t context    = rand()&_param->_nb_context;
+
+        for (uint32_t j=0; j<_param->_associativity; j++)
+//        btb_val     [j] = false;
+          btb_address [j] = static_cast<Taddress_t>(-1);
+
+        {
+          uint32_t associativity = 0;
+          
+          while (associativity < _param->_associativity)
+            {
+              for (uint32_t j=0; j<_param->_nb_inst_decod; j++)
+                {
+                  Taddress_t address = ((associativity << _param->_param_branch_target_buffer_register->_shift_tag) |
+                                        (index         << _param->_param_branch_target_buffer_register->_shift_bank)|
+                                        (0));
+                  
+                  in_DECOD_VAL             [j]->write(((rand()%100)<percent_transaction_decod) and ((associativity+j) < _param->_associativity));
+                  in_DECOD_CONTEXT_ID      [j]->write(context);
+                  in_DECOD_ADDRESS_SRC     [j]->write( address );
+                  in_DECOD_ADDRESS_DEST    [j]->write(~address );
+                  in_DECOD_CONDITION       [j]->write(BRANCH_CONDITION_FLAG_SET);
+                  in_DECOD_LAST_TAKE       [j]->write(address&1);
+                  in_DECOD_MISS_PREDICTION [j]->write(1);
+                  in_DECOD_IS_ACCURATE     [j]->write(1);
+                }
+              
+              SC_START(0);
+              
+              for (uint32_t j=0; j<_param->_nb_inst_decod; j++)
+                if (in_DECOD_VAL [j]->read() and out_DECOD_ACK [j]->read())
+                  {
+                    LABEL("DECOD     [%d] Transaction Accepted",j);
+                    
+                    Taddress_t address = in_DECOD_ADDRESS_SRC [j]->read();
+                    
+                    btb_address[associativity] = address;
+                    btb_context[associativity] = context;
+                    associativity ++;
+                  }
+              
+              SC_START(1);
+            }
+        }
+        
+        nb_request = 0;
+
+        while (nb_request < NB_REQUEST)
+          {
+            for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
+              {
+                in_PREDICT_VAL        [i]->write(((rand()%100)<percent_transaction_predict));
+                in_PREDICT_CONTEXT_ID [i]->write(rand()&_param->_nb_context);
+                in_PREDICT_ADDRESS    [i]->write(gen_addr(_param->_param_branch_target_buffer_register,index));
+              }
+
+            SC_START(0);
+
+            for (uint32_t i=0; i<_param->_nb_inst_predict; i++)
+              if (in_PREDICT_VAL [i]->read() and out_PREDICT_ACK [i]->read())
+                {
+                  LABEL("PREDICT   [%d] Transaction Accepted",i);
+                  
+                  Tcontrol_t hit          = out_PREDICT_HIT          [i]->read();
+                  Taddress_t address      =  in_PREDICT_ADDRESS      [i]->read();
+                  Taddress_t address_src  = out_PREDICT_ADDRESS_SRC  [i]->read();
+                  Taddress_t address_dest = out_PREDICT_ADDRESS_DEST [i]->read();
+
+                  Taddress_t tag          = address >> _param->_param_branch_target_buffer_register->_shift_tag;
+                  
+                  Tcontrol_t my_hit = false;
+                  Tcontrol_t my_addr;
+
+                  for (uint32_t i=0; i<_param->_associativity; i++)
+                    {
+                      Taddress_t btb_address [_param->_associativity];
+                      Tcontext_t btb_context [_param->_associativity];
+                    }
+                  
+                  if (hit)
+                    {
+                      TEST(Tbranch_condition_t,out_PREDICT_CONDITION   [i]->read(),BRANCH_CONDITION_FLAG_SET);
+                      TEST(Tcontrol_t         ,out_PREDICT_LAST_TAKE   [i]->read(),address_src&1);
+//                    TEST(Tcontrol_t         ,out_PREDICT_IS_ACCURATE [i]->read(), );
+                    }
+
+                  nb_request ++;
+                }
+            
+            SC_START(1);
+          }
+      }
+  }
 
   /********************************************************