Ignore:
Timestamp:
Dec 10, 2008, 7:31:39 PM (15 years ago)
Author:
rosiere
Message:

Almost complete design
with Test and test platform

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/Sort/src/Sort_end_cycle.cpp

    r81 r88  
    2222
    2323#ifdef STATISTICS
    24     _stat->end_cycle();
     24    if (usage_is_set(_usage,USE_STATISTICS))
     25      _stat->end_cycle();
    2526#endif   
    2627
     
    2829    // Evaluation before read the ouput signal
    2930//  sc_start(0);
    30     _interfaces->testbench();
     31    if (usage_is_set(_usage,USE_VHDL_TESTBENCH))
     32      _interfaces->testbench();
    3133#endif
    3234
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