- Timestamp:
- Dec 10, 2008, 7:31:39 PM (15 years ago)
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trunk/IPs/systemC/processor/Morpheo/Behavioural/include/Constants.h
r81 r88 2 2 #define morpheo_behavioural_Constants_h 3 3 4 /* 5 WARNING : 6 7 I Use reserved exception : 8 9 0x10 - EXCEPTION_MEMORY_MISS_SPECULATION - Load miss speculation 10 0x11 - EXCEPTION_MEMORY_LOAD_SPECULATIVE - The load is speculative : write in register file, but don't commit 11 0x12 - EXCEPTION_ALU_SPR_ACCESS_INVALID - SPR present in ALU but not compatible privilege 12 0x13 - EXCEPTION_ALU_SPR_ACCESS_MUST_READ - SPR not present in ALU 13 0x14 - EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE - SPR not present in ALU 14 15 I Use reserved SPR : 16 [0][19] - SPR_CID 17 */ 18 4 19 namespace morpheo { 5 20 namespace behavioural { 21 22 # define SET_FLAG( x,pos) {(x) |= (1<<(pos));} while (0) 23 # define UNSET_FLAG( x,pos) {(x) &= ~(1<<(pos));} while (0) 24 # define IS_SET_FLAG( x,pos) (((x) & (1<<(pos))) != 0) 25 # define IS_UNSET_FLAG(x,pos) (((x) & (1<<(pos))) == 0) 26 # define CHANGE_FLAG( x,pos,f) \ 27 { \ 28 if (f) \ 29 {SET_FLAG(x,pos);} \ 30 else \ 31 {UNSET_FLAG(x,pos);} \ 32 } while (0) 6 33 7 34 //=========================================================[ Type ]===== … … 10 37 # define TYPE_MOVE 0x2 // 00000 - unit multiple 11 38 # define TYPE_TEST 0x3 // 00000 - unit multiple 12 # define TYPE_MUL_DIV 0x4 // 00000 - unit multiple 13 # define TYPE_EXTEND 0x5 // 00000 - unit multiple, type optionnal 14 # define TYPE_FIND 0x6 // 00000 - unit multiple, type optionnal 15 # define TYPE_SPECIAL 0x7 // 00000 - unit uniq 16 # define TYPE_CUSTOM 0x8 // 00000 - unit uniq , type optionnal 17 # define TYPE_BRANCH 0x9 // 00000 - unit multiple 18 # define TYPE_MEMORY 0xa // 00000 - unit uniq 19 39 # define TYPE_MUL 0x4 // 00000 - unit multiple 40 # define TYPE_DIV 0x5 // 00000 - unit multiple, type optionnal 41 # define TYPE_EXTEND 0x6 // 00000 - unit multiple, type optionnal 42 # define TYPE_FIND 0x7 // 00000 - unit multiple, type optionnal 43 # define TYPE_SPECIAL 0x8 // 00000 - unit uniq 44 # define TYPE_CUSTOM 0x9 // 00000 - unit uniq , type optionnal 45 # define TYPE_BRANCH 0xa // 00000 - unit multiple 46 # define TYPE_MEMORY 0xb // 00000 - unit uniq 47 48 //#define NB_TYPE 11 20 49 # define SIZE_TYPE 5 21 50 # define MAX_TYPE (1<<SIZE_TYPE) 51 52 # define is_type_valid(x) \ 53 (( x == TYPE_ALU ) or \ 54 ( x == TYPE_SHIFT ) or \ 55 ( x == TYPE_MOVE ) or \ 56 ( x == TYPE_TEST ) or \ 57 ( x == TYPE_MUL ) or \ 58 ( x == TYPE_DIV ) or \ 59 ( x == TYPE_EXTEND ) or \ 60 ( x == TYPE_FIND ) or \ 61 ( x == TYPE_SPECIAL) or \ 62 ( x == TYPE_CUSTOM ) or \ 63 ( x == TYPE_BRANCH ) or \ 64 ( x == TYPE_MEMORY )) 22 65 23 66 //====================================================[ Operation ]===== … … 149 192 # define OPERATION_TEST_L_SFNE 0x20 // 000_0000 l.sfne , l.sfnei 150 193 151 # define OPERATION_MUL_DIV_L_MUL 0x1 // 000_0000 l.mul , l.muli 152 # define OPERATION_MUL_DIV_L_MULU 0x2 // 000_0000 l.mulu 153 # define OPERATION_MUL_DIV_L_DIV 0x4 // 000_0000 l.div 154 # define OPERATION_MUL_DIV_L_DIVU 0x8 // 000_0000 l.divu 194 # define OPERATION_MUL_L_MUL 0x1 // 000_0000 l.mul , l.muli 195 # define OPERATION_MUL_L_MULU 0x2 // 000_0000 l.mulu 196 197 # define OPERATION_DIV_L_DIV 0x1 // 000_0000 l.div 198 # define OPERATION_DIV_L_DIVU 0x2 // 000_0000 l.divu 155 199 156 200 # define OPERATION_EXTEND_L_EXTEND_Z 0x1 // 000_0000 l.extbz , l.exthz, l.extwz … … 204 248 # define SIZE_EXCEPTION 5 205 249 # define SIZE_EXCEPTION_USE 4 206 # define SIZE_EXCEPTION_MEMORY 3207 # define SIZE_EXCEPTION_CUSTOM 3208 # define SIZE_EXCEPTION_ALU 2209 # define SIZE_EXCEPTION_DECOD 2210 # define SIZE_EXCEPTION_IFETCH 2250 # define SIZE_EXCEPTION_MEMORY 5 251 # define SIZE_EXCEPTION_CUSTOM 5 252 # define SIZE_EXCEPTION_ALU 5 253 # define SIZE_EXCEPTION_DECOD 5 254 # define SIZE_EXCEPTION_IFETCH 5 211 255 212 256 # define EXCEPTION_NONE 0x00 // none exception … … 243 287 # define EXCEPTION_CUSTOM_6 0x1f // Reserved for custom exceptions 244 288 245 246 #define exception_to_address(x) (x<<8) 289 //SR[14].EPH : Exception Prefix High 290 // EPH = 0 Exceptions vectors are located in memory area starting at 0x0 291 // EPH = 1 Exception vectors are located in memory area starting at 0xF0000000 292 293 #define exception_to_address(eph,x) (((eph==0)?0x0:0xF0000000)+(x<<8)) 247 294 248 295 // Exception Execution 249 # define EXCEPTION_MEMORY_NONE 0x0 // Load/Store generate none exception 250 # define EXCEPTION_MEMORY_ALIGNMENT 0x1 // Load/Store access is not aligned 251 # define EXCEPTION_MEMORY_DATA_TLB 0x2 // DTLB miss 252 # define EXCEPTION_MEMORY_DATA_PAGE 0x3 // No matching or page violation protection in pages tables 253 # define EXCEPTION_MEMORY_BUS_ERROR 0x4 // Access at a invalid physical address 254 # define EXCEPTION_MEMORY_MISS_SPECULATION 0x5 // Load miss speculation 255 # define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x6 // The load is speculative : write in register file, but don't commit 256 257 # define EXCEPTION_CUSTOM_NONE 0x1 // Custom unit generate none exception 258 # define EXCEPTION_CUSTOM_CUST_0 0x1 // Reserved for custom exceptions 259 # define EXCEPTION_CUSTOM_CUST_1 0x2 // Reserved for custom exceptions 260 # define EXCEPTION_CUSTOM_CUST_2 0x3 // Reserved for custom exceptions 261 # define EXCEPTION_CUSTOM_CUST_3 0x4 // Reserved for custom exceptions 262 # define EXCEPTION_CUSTOM_CUST_4 0x5 // Reserved for custom exceptions 263 # define EXCEPTION_CUSTOM_CUST_5 0x6 // Reserved for custom exceptions 264 # define EXCEPTION_CUSTOM_CUST_6 0x7 // Reserved for custom exceptions 265 266 # define EXCEPTION_ALU_NONE 0x0 // Functionnal unit generate none exception 267 # define EXCEPTION_ALU_RANGE 0x1 // 268 # define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x2 // SPR present in ALU but not compatible privilege 269 # define EXCEPTION_ALU_SPR_ACCESS_NOT_COMPLETE 0x3 // SPR not present in ALU 270 271 # define EXCEPTION_DECOD_NONE 0x0 // none exception 272 # define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x1 // Instruction is illegal (no implemented) 273 # define EXCEPTION_DECOD_SYSCALL 0x2 // System Call 274 //#define EXCEPTION_DECOD_TRAP 0x4 // L.trap or debug unit (note : must read SR !) 275 276 # define EXCEPTION_IFETCH_NONE 0x0 // Fetch Unit generate none exception 277 # define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x1 // ITLB miss 278 # define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x2 // No matching or page violation protection in pages tables 279 # define EXCEPTION_IFETCH_BUS_ERROR 0x3 // Access at a invalid physical address 280 281 # define EXCEPTION_USE_NONE 0x0 // 282 # define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x1 // illegal_instruction 283 # define EXCEPTION_USE_RANGE 0x2 // range 284 # define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x3 // TLB miss, page fault, bus error, alignment 285 # define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x4 // TLB miss, page fault, bus error 286 # define EXCEPTION_USE_SYSCALL 0x5 // syscall 287 # define EXCEPTION_USE_TRAP 0x6 // trap 288 # define EXCEPTION_USE_CUSTOM_0 0x7 // 289 # define EXCEPTION_USE_CUSTOM_1 0x8 // 290 # define EXCEPTION_USE_CUSTOM_2 0x9 // 291 # define EXCEPTION_USE_CUSTOM_3 0xa // 292 # define EXCEPTION_USE_CUSTOM_4 0xb // 293 # define EXCEPTION_USE_CUSTOM_5 0xc // 294 # define EXCEPTION_USE_CUSTOM_6 0xd // 296 # define EXCEPTION_IFETCH_NONE 0x00 // Fetch Unit generate none exception 297 # define EXCEPTION_IFETCH_INSTRUCTION_TLB 0x0a // ITLB miss 298 # define EXCEPTION_IFETCH_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables 299 # define EXCEPTION_IFETCH_BUS_ERROR 0x02 // Access at a invalid physical address 300 301 # define EXCEPTION_DECOD_NONE 0x00 // none exception 302 # define EXCEPTION_DECOD_ILLEGAL_INSTRUCTION 0x01 // Instruction is illegal (no implemented) 303 # define EXCEPTION_DECOD_SYSCALL 0x02 // System Call 304 //#define EXCEPTION_DECOD_TRAP 0x0e // L.trap or debug unit (note : must read SR !) 305 # define EXCEPTION_DECOD_INSTRUCTION_TLB 0x0a // ITLB miss 306 # define EXCEPTION_DECOD_INSTRUCTION_PAGE 0x04 // No matching or page violation protection in pages tables 307 # define EXCEPTION_DECOD_BUS_ERROR 0x02 // Access at a invalid physical address 308 309 # define EXCEPTION_ALU_NONE 0x00 // Functionnal unit generate none exception 310 # define EXCEPTION_ALU_RANGE 0x0b // 311 # define EXCEPTION_ALU_SPR_ACCESS_INVALID 0x12 // SPR present in ALU but not compatible privilege 312 # define EXCEPTION_ALU_SPR_ACCESS_MUST_READ 0x13 // SPR not present in ALU 313 # define EXCEPTION_ALU_SPR_ACCESS_MUST_WRITE 0x14 // SPR not present in ALU 314 315 # define EXCEPTION_MEMORY_NONE 0x00 // Load/Store generate none exception 316 # define EXCEPTION_MEMORY_ALIGNMENT 0x06 // Load/Store access is not aligned 317 # define EXCEPTION_MEMORY_DATA_TLB 0x09 // DTLB miss 318 # define EXCEPTION_MEMORY_DATA_PAGE 0x03 // No matching or page violation protection in pages tables 319 # define EXCEPTION_MEMORY_BUS_ERROR 0x02 // Access at a invalid physical address 320 # define EXCEPTION_MEMORY_MISS_SPECULATION 0x10 // Load miss speculation 321 # define EXCEPTION_MEMORY_LOAD_SPECULATIVE 0x11 // The load is speculative : write in register file, but don't commit 322 323 # define EXCEPTION_CUSTOM_NONE 0x00 // Custom unit generate none exception 324 # define EXCEPTION_CUSTOM_CUST_0 0x19 // Reserved for custom exceptions 325 # define EXCEPTION_CUSTOM_CUST_1 0x1a // Reserved for custom exceptions 326 # define EXCEPTION_CUSTOM_CUST_2 0x1b // Reserved for custom exceptions 327 # define EXCEPTION_CUSTOM_CUST_3 0x1c // Reserved for custom exceptions 328 # define EXCEPTION_CUSTOM_CUST_4 0x1d // Reserved for custom exceptions 329 # define EXCEPTION_CUSTOM_CUST_5 0x1e // Reserved for custom exceptions 330 # define EXCEPTION_CUSTOM_CUST_6 0x1f // Reserved for custom exceptions 331 332 # define EXCEPTION_USE_NONE 0x00 // 333 # define EXCEPTION_USE_ILLEGAL_INSTRUCTION 0x01 // illegal_instruction 334 # define EXCEPTION_USE_RANGE 0x02 // range 335 # define EXCEPTION_USE_MEMORY_WITH_ALIGNMENT 0x03 // TLB miss, page fault, bus error, alignment 336 # define EXCEPTION_USE_MEMORY_WITHOUT_ALIGNMENT 0x04 // TLB miss, page fault, bus error 337 # define EXCEPTION_USE_SYSCALL 0x05 // syscall 338 # define EXCEPTION_USE_TRAP 0x06 // trap 339 # define EXCEPTION_USE_CUSTOM_0 0x07 // 340 # define EXCEPTION_USE_CUSTOM_1 0x08 // 341 # define EXCEPTION_USE_CUSTOM_2 0x09 // 342 # define EXCEPTION_USE_CUSTOM_3 0x0a // 343 # define EXCEPTION_USE_CUSTOM_4 0x0b // 344 # define EXCEPTION_USE_CUSTOM_5 0x0c // 345 # define EXCEPTION_USE_CUSTOM_6 0x0d // 346 347 # define exception_ifetch_to_exception_decod(x) x 348 # define exception_decod_to_exception(x) x 349 # define exception_alu_to_exception(x) x 350 # define exception_memory_to_exception(x) x 351 # define exception_custom_to_exception(x) x 295 352 296 353 //=======================================================[ icache ]===== … … 298 355 //--------------------------------------------------[ icache_type ]----- 299 356 300 # define SIZE_ICACHE_TYPE 301 302 # define ICACHE_TYPE_LOAD 303 # define ICACHE_TYPE_LOCK 304 # define ICACHE_TYPE_INVALIDATE 305 # define ICACHE_TYPE_PREFETCH 357 # define SIZE_ICACHE_TYPE 2 358 359 # define ICACHE_TYPE_LOAD 0x0 // 0000 360 # define ICACHE_TYPE_LOCK 0x1 // 0001 361 # define ICACHE_TYPE_INVALIDATE 0x2 // 0010 362 # define ICACHE_TYPE_PREFETCH 0x3 // 0011 306 363 307 364 // just take the 2 less significative bits. … … 310 367 //-------------------------------------------------[ icache_error ]----- 311 368 312 # define SIZE_ICACHE_ERROR 313 314 # define ICACHE_ERROR_NONE 315 # define ICACHE_ERROR_BUS_ERROR 369 # define SIZE_ICACHE_ERROR 1 370 371 # define ICACHE_ERROR_NONE 0x0 372 # define ICACHE_ERROR_BUS_ERROR 0x1 316 373 317 374 //=======================================================[ dcache ]===== … … 319 376 //--------------------------------------------------[ dcache_type ]----- 320 377 321 # define SIZE_DCACHE_TYPE 322 323 //#define DCACHE_TYPE_ 324 # define DCACHE_TYPE_LOCK 325 # define DCACHE_TYPE_INVALIDATE 326 # define DCACHE_TYPE_PREFETCH 327 //#define DCACHE_TYPE_ 328 //#define DCACHE_TYPE_ 329 # define DCACHE_TYPE_FLUSH 330 # define DCACHE_TYPE_SYNCHRONIZATION 331 # define DCACHE_TYPE_LOAD_8 332 # define DCACHE_TYPE_LOAD_16 333 # define DCACHE_TYPE_LOAD_32 334 # define DCACHE_TYPE_LOAD_64 335 # define DCACHE_TYPE_STORE_8 336 # define DCACHE_TYPE_STORE_16 337 # define DCACHE_TYPE_STORE_32 338 # define DCACHE_TYPE_STORE_64 378 # define SIZE_DCACHE_TYPE 4 379 380 //#define DCACHE_TYPE_ 0x0 // 0000 381 # define DCACHE_TYPE_LOCK 0x1 // 0001 382 # define DCACHE_TYPE_INVALIDATE 0x2 // 0010 383 # define DCACHE_TYPE_PREFETCH 0x3 // 0011 384 //#define DCACHE_TYPE_ 0x4 // 0100 385 //#define DCACHE_TYPE_ 0x5 // 0101 386 # define DCACHE_TYPE_FLUSH 0x6 // 0110 387 # define DCACHE_TYPE_SYNCHRONIZATION 0x7 // 0111 388 # define DCACHE_TYPE_LOAD_8 0x8 // 1000 389 # define DCACHE_TYPE_LOAD_16 0x9 // 1001 390 # define DCACHE_TYPE_LOAD_32 0xa // 1010 391 # define DCACHE_TYPE_LOAD_64 0xb // 1011 392 # define DCACHE_TYPE_STORE_8 0xc // 1100 393 # define DCACHE_TYPE_STORE_16 0xd // 1101 394 # define DCACHE_TYPE_STORE_32 0xe // 1110 395 # define DCACHE_TYPE_STORE_64 0xf // 1111 339 396 340 397 // just take the 4 less significative bits. … … 343 400 //-------------------------------------------------[ dcache_error ]----- 344 401 345 # define SIZE_DCACHE_ERROR 346 347 # define DCACHE_ERROR_NONE 348 # define DCACHE_ERROR_BUS_ERROR 402 # define SIZE_DCACHE_ERROR 1 403 404 # define DCACHE_ERROR_NONE 0x0 405 # define DCACHE_ERROR_BUS_ERROR 0x1 349 406 350 407 //=================================================[ special_data ]===== 351 408 352 # define SIZE_SPECIAL_DATA 409 # define SIZE_SPECIAL_DATA 2 353 410 354 411 // Position of flag in "rename register SR" (NOT IN "SR") 355 # define FLAG_POSITION_F 356 # define FLAG_POSITION_CY 357 # define FLAG_POSITION_OV 358 359 # define FLAG_F 360 # define FLAG_CY 361 # define FLAG_OV 412 # define FLAG_POSITION_F 0x0 // Conditionnal branch flag 413 # define FLAG_POSITION_CY 0x1 // Carry was produced by last arithmetic operation 414 # define FLAG_POSITION_OV 0x0 // Overflow occured during last arithmetic operation 415 416 # define FLAG_F (1<<FLAG_POSITION_F ) // Conditionnal branch flag 417 # define FLAG_CY (1<<FLAG_POSITION_CY) // Carry was produced by last arithmetic operation 418 # define FLAG_OV (1<<FLAG_POSITION_OV) // Overflow occured during last arithmetic operation 362 419 363 420 //==========================================================[ spr ]===== … … 396 453 GROUP_CUSTOM_6, // 29 397 454 GROUP_CUSTOM_7, // 30 398 GROUP_CUSTOM_8 // 31 455 GROUP_CUSTOM_8, // 31 456 NB_GROUP 399 457 }; 400 458 401 # define NB_GROUP 32402 459 # define NB_REG_GROUP_SYSTEM_AND_CONTROL 1536 403 460 # define NB_REG_GROUP_DMMU 1536 … … 432 489 # define NB_REG_GROUP_CUSTOM_7 0 433 490 # define NB_REG_GROUP_CUSTOM_8 0 434 491 492 static const uint32_t NB_REG_GROUP [] = 493 {NB_REG_GROUP_SYSTEM_AND_CONTROL , 494 NB_REG_GROUP_DMMU , 495 NB_REG_GROUP_IMMU , 496 NB_REG_GROUP_DCACHE , 497 NB_REG_GROUP_ICACHE , 498 NB_REG_GROUP_MAC , 499 NB_REG_GROUP_DEBUG , 500 NB_REG_GROUP_PERFORMANCE_COUNTER , 501 NB_REG_GROUP_POWER_MANAGEMENT , 502 NB_REG_GROUP_PIC , 503 NB_REG_GROUP_TICK_TIMER , 504 NB_REG_GROUP_FLOATING_POINT , 505 NB_REG_GROUP_RESERVED_1 , 506 NB_REG_GROUP_RESERVED_2 , 507 NB_REG_GROUP_RESERVED_3 , 508 NB_REG_GROUP_RESERVED_4 , 509 NB_REG_GROUP_RESERVED_5 , 510 NB_REG_GROUP_RESERVED_6 , 511 NB_REG_GROUP_RESERVED_7 , 512 NB_REG_GROUP_RESERVED_8 , 513 NB_REG_GROUP_RESERVED_9 , 514 NB_REG_GROUP_RESERVED_10 , 515 NB_REG_GROUP_RESERVED_11 , 516 NB_REG_GROUP_RESERVED_12 , 517 NB_REG_GROUP_CUSTOM_1 , 518 NB_REG_GROUP_CUSTOM_2 , 519 NB_REG_GROUP_CUSTOM_3 , 520 NB_REG_GROUP_CUSTOM_4 , 521 NB_REG_GROUP_CUSTOM_5 , 522 NB_REG_GROUP_CUSTOM_6 , 523 NB_REG_GROUP_CUSTOM_7 , 524 NB_REG_GROUP_CUSTOM_8 }; 525 526 // GROUP_SYSTEM_AND_CONTROL 527 # define SPR_VR 0 // Version register 528 # define SPR_UPR 1 // Unit Present register 529 # define SPR_CPUCFGR 2 // CPU Configuration register 530 # define SPR_DMMUCFGR 3 // Data MMU Configuration register 531 # define SPR_IMMUCFGR 4 // Instruction MMU Configuration register 532 # define SPR_DCCFGR 5 // Data Cache Configuration register 533 # define SPR_ICCFGR 6 // Instruction Cache Configuration register 534 # define SPR_DCFGR 7 // Debug Configuration register 535 # define SPR_PCCFGR 8 // Performance Counters Configuration register 536 # define SPR_NPC 16 // PC mapped to SPR space (next PC) 537 # define SPR_SR 17 // Supervision register 538 # define SPR_PPC 18 // PC mapped to SPR space (previous PC) 539 # define SPR_CID 19 // Context Id 540 # define SPR_FPCSR 20 // FP Control Status register 541 # define SPR_EPCR 32 // Exception PC register 542 # define SPR_EEAR 48 // Exception EA register 543 # define SPR_ESR 64 // Exception SR register 544 # define SPR_GPR 1024 // GPRs mappted to SPR space 545 546 // GROUP_DCACHE 547 # define SPR_DCCR 0 // DC Control register 548 # define SPR_DCBPR 1 // DC Block Prefetch register 549 # define SPR_DCBFR 2 // DC Block Flush register 550 # define SPR_DCBIR 3 // DC Block Invalidate register 551 # define SPR_DCBWR 4 // DC Block Write-back register 552 # define SPR_DCBLR 5 // DC Block Lock register 553 554 // GROUP_ICACHE 555 # define SPR_ICCR 0 // IC Control register 556 # define SPR_ICBPR 1 // IC Block Prefetch register 557 # define SPR_ICBIR 2 // IC Block Invalidate register 558 # define SPR_ICBLR 3 // IC Block Lock register 435 559 436 560 // GROUP_MAC … … 438 562 # define SPR_MACHI 2 // MAC High 439 563 564 565 566 // SR RENAME 440 567 # define NB_SPR_LOGIC 2 441 568 # define LOG2_NB_SPR_LOGIC 1 … … 863 990 # define OPCOD_L_EXTWZ 0x1 // 0001 864 991 865 /*866 867 //--------------------------------------------------[ destination ]-----868 #define _size_destination1 4869 870 #define cst_DESTINATION1_NONE 0x0871 #define mask_DESTINATION1_GPR 0x1872 #define mask_DESTINATION1_MEMORY 0x2873 #define mask_DESTINATION1_SPR 0x4874 #define mask_DESTINATION1_MAC_UNIT 0x8875 876 #define _size_destination2 3877 878 #define cst_DESTINATION2_NONE 0x0879 #define mask_DESTINATION2_COMMIT 0x1880 #define mask_DESTINATION2_MEMORY 0x2881 #define mask_DESTINATION2_SPR 0x4882 883 //----------------------------------------------------[ exec_flag ]-----884 #define _size_exec_flag 2885 886 #define mask_EXEC_FLAG_NONE 0x1887 #define mask_EXEC_FLAG_CARRY 0x1888 #define mask_EXEC_FLAG_FLAG 0x1889 #define mask_EXEC_FLAG_OVERFLOW 0x2890 891 //---------------------------------------------------[ exec_excep ]-----892 #define _size_exec_excep 1893 894 #define mask_EXEC_EXCEP_NONE 0x0895 #define mask_EXEC_EXCEP_RANGE 0x1896 897 //----------------------------------------------------[ Condition ]-----898 #define _size_condition 3899 900 #define cst_CONDITION_UNCONDITIONAL 0x0 // None condition (jump)901 #define mask_CONDITION_CONDITIONAL 0x2902 #define mask_CONDITION_CONDITIONAL_NF 0x0 // Branch if Flag is clear903 #define mask_CONDITION_CONDITIONAL_F 0x1 // Branch if Flag is set904 #define mask_CONDITION_REG 0x4 // Branch if a register is read905 #define mask_CONDITION_STACK 0x8 // Branch with pop in stack pointer906 907 */908 909 /*910 #define M_CPU_SIZE_INST 32911 912 //----------------------------------------------------913 // Exception type914 //----------------------------------------------------915 916 #define M_CPU_LOG2_NB_EXCP 5917 #define M_CPU_NB_EXCP 32918 919 #define EXCP_NO 0x00 // none exception920 #define EXCP_RESET 0x01 // software or hardware reset921 #define EXCP_BERR 0x02 // Access at a invalid physical adress922 #define EXCP_D_PAGE 0x03 // No matching or page violation protection in pages tables923 #define EXCP_I_PAGE 0x04 // No matching or page violation protection in pages tables924 #define EXCP_TICK_TIMER 0x05 // Tick timer interruption925 #define EXCP_ALIGNMENT 0x06 // Load/Store access is not aligned926 #define EXCP_ILL_INST 0x07 // Instruction is illegal (no implemented)927 #define EXCP_IRQ 0x08 // External interruption928 #define EXCP_D_TLB 0x09 // DTLB miss929 #define EXCP_I_TLB 0x0a // ITLB miss930 #define EXCP_RANGE 0x0b // Overflow or access at a unimplemented register or context931 #define EXCP_SYSCALL 0x0c // System Call932 #define EXCP_FP 0x0d // Caused by a floating instruction933 #define EXCP_TRAP 0x0e // L.trap or debug unit934 #define EXCP_RES0 0x0f // Reserved for a futur usage935 #define EXCP_RES1 0x10 // Reserved for a futur usage936 #define EXCP_RES2 0x11 // Reserved for a futur usage937 #define EXCP_RES3 0x12 // Reserved for a futur usage938 #define EXCP_RES4 0x13 // Reserved for a futur usage939 #define EXCP_RES5 0x14 // Reserved for a futur usage940 #define EXCP_RES6 0x15 // Reserved for implemented specific exceptions941 #define EXCP_RES7 0x16 // Reserved for implemented specific exceptions942 #define EXCP_RES8 0x17 // Reserved for implemented specific exceptions943 #define EXCP_RES9 0x18 // Reserved for implemented specific exceptions944 #define EXCP_CUST0 0x19 // Reserved for custom exceptions945 #define EXCP_CUST1 0x1a // Reserved for custom exceptions946 #define EXCP_CUST2 0x1b // Reserved for custom exceptions947 #define EXCP_CUST3 0x1c // Reserved for custom exceptions948 #define EXCP_CUST4 0x1d // Reserved for custom exceptions949 #define EXCP_CUST5 0x1e // Reserved for custom exceptions950 #define EXCP_CUST6 0x1f // Reserved for custom exceptions951 952 //----------------------------------------------------953 // Flags954 //----------------------------------------------------955 956 #define M_CPU_NB_FLAG 3957 958 // Integer flags959 #define FLAG_F 0x1 // Conditionnal branch flag960 #define FLAG_CY 0x2 // Carry was produced by last arithmétic operation961 #define FLAG_OV 0x4 // Overflow occured during last arithmetic operation962 963 // Floating flags964 #define FLAG_OVF 0x004 // Overflow occured during last arithmetic operation965 #define FLAG_UNF 0x008 // Underflow flags966 #define FLAG_SNF 0x010 // Result SNAN967 #define FLAG_QNF 0x020 // Result QNAN968 #define FLAG_ZF 0x040 // Result is nul969 #define FLAG_IXF 0x080 // Result is inexact970 #define FLAG_IVF 0x100 // Result is invalid971 #define FLAG_INF 0x200 // Result is infinite972 #define FLAG_DZF 0x400 // Division by zero973 974 // Position of flag in "rename register SR" (NOT IN "SR")975 #define FLAG_POS_F 0x0 // Conditionnal branch flag976 #define FLAG_POS_CY 0x1 // Carry was produced by last arithmétic operation977 #define FLAG_POS_OV 0x0 // Overflow occured during last arithmetic operation978 979 //----------------------------------------------------980 // Instruction type981 //----------------------------------------------------982 983 #define M_CPU_LOG2_NB_TYPE 4984 985 #define TYPE_NOP 0x0986 #define TYPE_ALU_F 0x1 // Instruction ALU with flag using (ADD, SUB, ADDC ...)987 #define TYPE_ALU_NF 0x2 // Instruction ALU without flag using (AND, OR ...)988 #define TYPE_MAC 0x3 // Instruction ALU with utilisation of register HI/LO989 #define TYPE_J 0x4 // Branch instruction990 #define TYPE_SPR_READ 0x5 // Instruction special : l.mfspr991 #define TYPE_SPR_WRITE 0x6 // Instruction special : l.mtspr992 #define TYPE_SPECIAL 0x7 // Instruction execute in decode stage993 #define TYPE_CUSTOM 0x8 // Instruction Custom994 995 #define TYPE_LOAD_Z 0x9 // Load access (extended by zero)996 #define TYPE_LOAD_S 0xa // Load access (sign extended)997 #define TYPE_STORE 0xc // Store access998 999 //----------------------------------------------------1000 // Condition to branch1001 //----------------------------------------------------1002 1003 #define M_CPU_LOG2_NB_COND 41004 1005 #define COND_NONE 0x0 // None condition (jump)1006 #define COND_F 0x2 // Branch if Flag is set1007 #define COND_NF 0x3 // Branch if Flag is clear1008 #define COND_REG 0x4 // Branch if a register is read1009 #define COND_STACK 0x8 // Branch with pop in stack pointer1010 1011 //----------------------------------------------------1012 // Event : State and Type1013 //----------------------------------------------------1014 1015 #define EVENT_STATE_NO_EVENT 0 // no event : current case1016 #define EVENT_STATE_EVENT 1 // Have a event : make necessary to manage the event1017 #define EVENT_STATE_WAITEND 2 // Wait end of manage event (restaure a good context)1018 #define EVENT_STATE_END 3 // CPU can continue1019 1020 #define EVENT_TYPE_MISS 0 // miss of speculation1021 #define EVENT_TYPE_EXCP 1 // exception or interruption occure1022 1023 // SPEC? TAKE?1024 #define BRANCH_STATE_NONE 0 // 0 01025 #define BRANCH_STATE_NSPEC_TAKE 1 // 0 1 -> incondionnal1026 #define BRANCH_STATE_SPEC_NTAKE 2 // 1 01027 #define BRANCH_STATE_SPEC_TAKE 3 // 1 11028 1029 //----------------------------------------------------1030 // Name to particular register1031 //----------------------------------------------------1032 1033 //~~~~~~~~~~~~~~~~~~~~~~~~~~1034 // GENERAL PURPOSE REGISTER1035 //~~~~~~~~~~~~~~~~~~~~~~~~~~1036 #define M_CPU_LOG2_NB_GPR_LOG 51037 #define M_CPU_NB_GPR_LOG (1<<M_CPU_LOG2_NB_GPR_LOG)1038 1039 #define GPR_LOG_LR 0x09 // Link register1040 #define REG_PHY_SR 0x00 // Status register1041 1042 //~~~~~~~~~~~~~~~~~~~~~~~~~~1043 // SPECIAL PURPOSE REGISTER1044 //~~~~~~~~~~~~~~~~~~~~~~~~~~1045 #define M_CPU_LOG2_NB_SPR_LOG 11046 #define M_CPU_NB_SPR_LOG (1<<M_CPU_LOG2_NB_SPR_LOG)1047 #define M_CPU_SPR_SIZE_DATA 2 // Size of the most great register1048 1049 #define SPR_LOG_SR_F 0x00 // Status register bit F (size = 1)1050 #define SPR_LOG_SR_CY_OV 0x01 // Status register bit overflow and carry (size = 2)1051 //#define SPR_LOG_SR_LO 0x02 // MAC LSB (size = 32)1052 //#define SPR_LOG_SR_HI 0x03 // MAC MSB (size = 32)1053 */1054 1055 /*1056 */1057 1058 992 }; // end namespace behavioural 1059 993 }; // end namespace morpheo
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