Changeset 94 for trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp

Timestamp:

Dec 15, 2008, 12:04:03 PM (15 years ago)

Author:

rosiere

Message:

Update document on Vhdl generation.

File:

• trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp (modified) (5 diffs)

trunk/IPs/systemC/processor/Morpheo/Behavioural/Generic/RegisterFile/RegisterFile_Monolithic/src/RegisterFile_Monolithic_vhdl_body.cpp

@@ -17 +17 @@
   void RegisterFile_Monolithic::vhdl_body (Vhdl * & vhdl)
   {
-    vhdl->set_body ("");
-    vhdl->set_body ("-----------------------------------------------------------------------------");
-    vhdl->set_body ("-- Ackitement");
-    vhdl->set_body ("-----------------------------------------------------------------------------");
-    vhdl->set_body ("");
+    vhdl->set_body   (0,"");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_comment(0," Ackitement");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_body   (0,"");
 
     for (uint32_t i = 0; i < _param->_nb_port_read; i++)
-      vhdl->set_body ("out_READ_"+toString(i)+"_ACK  <= '1';");
+      vhdl->set_body   (0,"out_READ_"+toString(i)+"_ACK  <= '1';");
     for (uint32_t i = 0; i < _param->_nb_port_write; i++)
-      vhdl->set_body ("out_WRITE_"+toString(i)+"_ACK <= '1';");
+      vhdl->set_body   (0,"out_WRITE_"+toString(i)+"_ACK <= '1';");
     for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
-      vhdl->set_body ("out_READ_WRITE_"+toString(i)+"_ACK  <= '1';");
+      vhdl->set_body   (0,"out_READ_WRITE_"+toString(i)+"_ACK  <= '1';");
 
-    vhdl->set_body ("");
-    vhdl->set_body ("-----------------------------------------------------------------------------");
-    vhdl->set_body ("-- Read RegisterFile");
-    vhdl->set_body ("-----------------------------------------------------------------------------");
-    vhdl->set_body ("");
+    vhdl->set_body   (0,"");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_comment(0," Read RegisterFile");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_body   (0,"");
     
     for (uint32_t i = 0; i < _param->_nb_port_read; i++)
@@ -44 +44 @@
           str_address = "0";
 
-        vhdl->set_body ("out_READ_"+toString(i)+"_DATA <= reg_DATA ("+str_address+") when in_READ_"+toString(i)+"_VAL = '1' else "+std_logic_others(_param->_size_word,0)+";");
+        vhdl->set_body   (0,"out_READ_"+toString(i)+"_DATA <= reg_DATA ("+str_address+") when in_READ_"+toString(i)+"_VAL = '1' else "+std_logic_others(_param->_size_word,0)+";");
       }
     for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
@@ -53 +53 @@
         else
           str_address = "0";
-        vhdl->set_body ("out_READ_WRITE_"+toString(i)+"_RDATA <= reg_DATA ("+str_address+") when in_READ_WRITE_"+toString(i)+"_VAL = '1' and in_READ_WRITE_"+toString(i)+"_RW = '"+toString(RW_READ)+"' else "+std_logic_others(_param->_size_word,0)+";");
+        vhdl->set_body   (0,"out_READ_WRITE_"+toString(i)+"_RDATA <= reg_DATA ("+str_address+") when in_READ_WRITE_"+toString(i)+"_VAL = '1' and in_READ_WRITE_"+toString(i)+"_RW = '"+toString(RW_READ)+"' else "+std_logic_others(_param->_size_word,0)+";");
       }
 
-    vhdl->set_body ("");
-    vhdl->set_body ("-----------------------------------------------------------------------------");
-    vhdl->set_body ("-- Write RegisterFile");
-    vhdl->set_body ("-----------------------------------------------------------------------------");
-    vhdl->set_body ("");
+    vhdl->set_body   (0,"");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_comment(0," Write RegisterFile");
+    vhdl->set_comment(0,"---------------------------------------------------------------------------");
+    vhdl->set_body   (0,"");
 
-    vhdl->set_body ("RegisterFile_write: process (in_CLOCK)");
-    vhdl->set_body ("begin  -- process RegisterFile_write");
-    vhdl->set_body ("\tif in_CLOCK'event and in_CLOCK = '1' then");
+    vhdl->set_body   (0,"RegisterFile_write: process (in_CLOCK)");
+    vhdl->set_body   (0,"begin  -- process RegisterFile_write");
+    vhdl->set_body   (1,"if in_CLOCK'event and in_CLOCK = '1' then");
     
     for (uint32_t i = 0; i < _param->_nb_port_write; i++)
@@ -74 +74 @@
           str_address = "0";
 
-        vhdl->set_body ("\t\tif (in_WRITE_"+toString(i)+"_VAL = '1') then");
-        vhdl->set_body ("\t\t\treg_DATA("+str_address+") <= in_WRITE_"+toString(i)+"_DATA;");
-        vhdl->set_body ("\t\tend if;");
+        vhdl->set_body   (2,"if (in_WRITE_"+toString(i)+"_VAL = '1') then");
+        vhdl->set_body   (3,"reg_DATA("+str_address+") <= in_WRITE_"+toString(i)+"_DATA;");
+        vhdl->set_body   (2,"end if;");
       }
     for (uint32_t i = 0; i < _param->_nb_port_read_write; i++)
@@ -86 +86 @@
           str_address = "0";
         
-        vhdl->set_body ("\t\tif (in_READ_WRITE_"+toString(i)+"_VAL = '1' and in_READ_WRITE_"+toString(i)+"_RW = '"+toString(RW_WRITE)+"') then");
-        vhdl->set_body ("\t\t\treg_DATA("+str_address+") <= in_READ_WRITE_"+toString(i)+"_WDATA;");
-        vhdl->set_body ("\t\tend if;");
+        vhdl->set_body   (2,"if (in_READ_WRITE_"+toString(i)+"_VAL = '1' and in_READ_WRITE_"+toString(i)+"_RW = '"+toString(RW_WRITE)+"') then");
+        vhdl->set_body   (3,"reg_DATA("+str_address+") <= in_READ_WRITE_"+toString(i)+"_WDATA;");
+        vhdl->set_body   (2,"end if;");
       }
 
-    vhdl->set_body ("\tend if;");
-    vhdl->set_body ("end process RegisterFile_write;");
+    vhdl->set_body   (1,"end if;");
+    vhdl->set_body   (0,"end process RegisterFile_write;");
   };