Ignore:
Timestamp:
Dec 16, 2008, 5:24:26 PM (15 years ago)
Author:
rosiere
Message:

1) Update Prediction Table - New architecture (systemC) done (and tested) -> need change interface in top level
2) Change documentation on VHDL generation
3) Change VHDL constant (case std_logic and std_logic_vector)

File:
1 edited

Legend:

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  • trunk/IPs/systemC/processor/Morpheo/Behavioural/Core/Multi_Front_end/Front_end/Decod_unit/Decod/src/Decod_allocation.cpp

    r88 r95  
    8989      ALLOC1_SIGNAL_OUT(out_DECOD_NO_EXECUTE   ,"no_execute"   ,Tcontrol_t        ,1                                   );
    9090      ALLOC1_SIGNAL_OUT(out_DECOD_IS_DELAY_SLOT,"is_delay_slot",Tcontrol_t        ,1                                   );
    91       ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS      ,"address"      ,Tgeneral_data_t   ,_param->_size_instruction_address          );
     91      ALLOC1_SIGNAL_OUT(out_DECOD_ADDRESS      ,"address"      ,Tgeneral_data_t   ,_param->_size_instruction_address   );
    9292      ALLOC1_SIGNAL_OUT(out_DECOD_HAS_IMMEDIAT ,"has_immediat" ,Tcontrol_t        ,1                                   );
    9393      ALLOC1_SIGNAL_OUT(out_DECOD_IMMEDIAT     ,"immediat"     ,Tgeneral_data_t   ,_param->_size_general_data          );
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