Opened 14 years ago

Closed 13 years ago

#39 closed defect (invalid)

Handle Mips delay slot in exception handler

Reported by: Nicolas Pouillon Owned by: Nicolas Pouillon
Priority: critical Milestone: Preemptive scheduler usage
Component: cpu/mips Keywords:
Cc:

Description

We dont currently handle CAUSE/BD which tells us we are actually in a delay slot. This can make the return address of an interrupt wrong.

We should:

  • Add a bit in cpu_context save/restore mask
  • Copy CAUSE/BD to save/restore mask
  • Substract 4 when restoring PC with BD = 1

Change History (3)

comment:1 Changed 14 years ago by Nicolas Pouillon

Component: Build system → cpu/mips
Priority: major → critical

comment:2 Changed 14 years ago by Nicolas Pouillon

Milestone: → Preempt merge

comment:3 Changed 13 years ago by becoulet

Resolution: → invalid
Status: new → closed

Mips processor already set EPC=fault_instruction_pc-4 when in branch delay slot.

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