Changeset 59 for sources/src/module_hierarchy2dot.cc

Timestamp:

Feb 6, 2017, 11:35:42 AM (7 years ago)

Author:

meunier

Message:

• Fixed memory leaks
• Fixed indentation in some files

File:

• sources/src/module_hierarchy2dot.cc (modified) (3 diffs)

sources/src/module_hierarchy2dot.cc

@@ -1 +1 @@
 /*------------------------------------------------------------\
-|                                                             |
-| Tool    :                  systemcass                       |
-|                                                             |
-| File    :                  module_hierarchy2dot.cc          |
-|                                                             |
-| Author  :                 Buchmann Richard                  |
-|                                                             |
-| Date    :                   26_01_2006                      |
-|                                                             |
-\------------------------------------------------------------*/
+  |                                                             |
+  | Tool    :                  systemcass                       |
+  |                                                             |
+  | File    :                  module_hierarchy2dot.cc          |
+  |                                                             |
+  | Author  :                 Buchmann Richard                  |
+  |                                                             |
+  | Date    :                   26_01_2006                      |
+  |                                                             |
+  \------------------------------------------------------------*/
 
 /* 
@@ -53 +53 @@
 namespace sc_core {
 
-/*
-static
-const char*
-get_parent_name (const sc_object &obj)
-{
-  const sc_object *parent = NULL;//get_parent_object (obj);
-  if (parent == NULL)
-    return "";
-  return parent->basename ();
-}
-*/
-
 typedef set<const char*> node_set_t;
 node_set_t node_set;
 
-static
-void
-print_edge (ostream &o)
+static void print_edge (ostream &o)
 {
-  typedef map<const char*, const char*> edge_t;
-  edge_t edges;
-  const equi_list_t &eq_list = get_equi_list ();
-  equi_list_t::const_iterator jt;
-  for (jt = eq_list.begin (); jt != eq_list.end (); ++jt)
-  {
-    const equi_t &eq = (*jt);
-    sc_port_base *out   = get_out_port (eq);
-    if (out == NULL)
-      continue;
-    if (is_clock (*out))
-      continue;
-    const sc_module &out_mod = out->get_module ();
-    const char *out_mod_name = out_mod.basename ();
-    equi_t::const_iterator it;
-    for (it = eq.begin (); it != eq.end (); ++it)
+    typedef map<const char*, const char*> edge_t;
+    edge_t edges;
+    const equi_list_t &eq_list = get_equi_list ();
+    equi_list_t::const_iterator jt;
+    for (jt = eq_list.begin (); jt != eq_list.end (); ++jt)
     {
-      const entity &in_entity  = *it;
-      sc_object    *in_obj     = in_entity.object;
-      assert(in_obj != NULL);
-      const sc_module *in_parent = NULL;
-      switch (in_entity.type) {
-      case entity::PORT :
-        in_parent = &(in_entity.port->get_module ());
-        if (&out_mod == in_parent)
-          continue;
-        break;
-      case entity::SIGNAL :
-      default :
-        continue;
-      }
-      edges[out_mod_name] = in_parent->basename ();
-      node_set.insert(out_mod_name);
-      node_set.insert(in_parent->basename ());
+        const equi_t & eq = (*jt);
+        sc_port_base * out   = get_out_port (eq);
+        if (out == NULL) {
+            continue;
+        }
+        if (is_clock(*out)) {
+            continue;
+        }
+        const sc_module &out_mod = out->get_module ();
+        const char *out_mod_name = out_mod.basename ();
+        equi_t::const_iterator it;
+        for (it = eq.begin (); it != eq.end (); ++it)
+        {
+            const entity &in_entity  = *it;
+            sc_object    *in_obj     = in_entity.object;
+            assert(in_obj != NULL);
+            const sc_module *in_parent = NULL;
+            switch (in_entity.type) {
+                case entity::PORT :
+                    in_parent = &(in_entity.port->get_module ());
+                    if (&out_mod == in_parent) {
+                        continue;
+                    }
+                    break;
+                case entity::SIGNAL :
+                default :
+                    continue;
+            }
+            edges[out_mod_name] = in_parent->basename ();
+            node_set.insert(out_mod_name);
+            node_set.insert(in_parent->basename ());
+        }
     }
-  }
 #if 0
-  const equi_t &signal_eq = *(eq_list.begin ());
-  const char *signal_name = get_name (signal_eq);
-  o << "edge [label=\"" << signal_name << "\"]\n";
+    const equi_t &signal_eq = *(eq_list.begin ());
+    const char *signal_name = get_name (signal_eq);
+    o << "edge [label=\"" << signal_name << "\"]\n";
 #endif
-  edge_t::const_iterator i;
-  for (i = edges.begin (); i != edges.end (); ++i)
-  {
-    o << i->first
-      << " -> " 
-      << i->second 
-      << ";\n";
-  }
+    edge_t::const_iterator i;
+    for (i = edges.begin (); i != edges.end (); ++i)
+    {
+        o << i->first
+          << " -> " 
+          << i->second 
+          << ";\n";
+    }
 }
 
@@ -126 +115 @@
 
 static
-void
+    void
 print_node (ostream         &o,
-            const sc_object &obj)
+        const sc_object &obj)
 {
-  const vector<sc_object*> &obj_list = get_child_objects (obj);
-  bool subgraph = (obj_list.empty() == false);
-//                  && (get_parent_object (obj) != NULL);
-  if (subgraph) {
-    const char *name = obj.basename ();
-    o << "subgraph \"cluster" << name << "\" {\n"
-      << "label=\"" << name << "\";\n";
-    print_node (o, obj_list);
-    o << "}\n";
-  } /*else*/ {
-//    if (obj.kind () == sc_module::kind_string)
-    if (node_set.find (obj.basename ()) != node_set.end())
-      o << obj.basename () << endl;
-  }
+    const vector<sc_object*> &obj_list = get_child_objects (obj);
+    bool subgraph = (obj_list.empty() == false);
+    //                  && (get_parent_object (obj) != NULL);
+    if (subgraph) {
+        const char *name = obj.basename ();
+        o << "subgraph \"cluster" << name << "\" {\n"
+            << "label=\"" << name << "\";\n";
+        print_node (o, obj_list);
+        o << "}\n";
+    } /*else*/ {
+        //    if (obj.kind () == sc_module::kind_string)
+        if (node_set.find (obj.basename ()) != node_set.end()) {
+            o << obj.basename () << endl;
+        }
+    }
 }
 
 static
-void
+    void
 print_node (ostream                  &o,
-            const vector<sc_object*> &obj_list)
+        const vector<sc_object*> &obj_list)
 {
-  vector<sc_object*>::const_iterator it;
-  for (it = obj_list.begin(); it != obj_list.end(); ++it)
-  {
-    sc_object *obj = *it;
-    print_node (o, *obj);
-  }
+    vector<sc_object*>::const_iterator it;
+    for (it = obj_list.begin(); it != obj_list.end(); ++it)
+    {
+        sc_object *obj = *it;
+        print_node (o, *obj);
+    }
 }
 
-bool
+    bool
 module_hierarchy2dot (const char *name)
 {
-        if (!name)
-                return false;
-        string filename;
-        filename =  name;
-        filename += ".dot";
-        ofstream o;
-  o.open (filename.c_str(),ios::out | ios::trunc);
-        if (o.is_open () == false)
-                return false;
-        o << "strict digraph " << name << " {\n";
-  o << "node [shape=box];\n";
-  print_edge (o);
-        print_node (o,sc_get_top_level_objects ());
-        o << "}\n";
-        o.close ();
-        return true;
+    if (!name) {
+        return false;
+    }
+    string filename;
+    filename =  name;
+    filename += ".dot";
+    ofstream o;
+    o.open (filename.c_str(),ios::out | ios::trunc);
+    if (o.is_open () == false) {
+        return false;
+    }
+    o << "strict digraph " << name << " {\n";
+    o << "node [shape=box];\n";
+    print_edge (o);
+    print_node (o,sc_get_top_level_objects ());
+    o << "}\n";
+    o.close ();
+    return true;
 }