source: branches/RWT/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd @ 604

Last change on this file since 604 was 468, checked in by cfuguet, 10 years ago


Merging vci_mem_cache from branches/v5 to trunk [441-467]

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r441 | cfuguet | 2013-07-17 10:54:07 +0200 (Wed, 17 Jul 2013) | 14 lines

Modifications in branches/v5/vci_mem_cache:

  • Changing name of CC DSPIN ports: + p_dspin_in => p_dspin_p2m + p_dspin_out => p_dspin_m2p
  • Splitting the Update Table in two tables: + UPT (Update Table): Stores the MULTI-UPDATE transactions + IVT (Invalidate Table): Stores the MULTI/BROADCAST INVALIDATE

transactions

Each table has its own allocator FSM: r_alloc_upt and r_alloc_ivt

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/modules/vci_mem_cache:

  • Introducing third port for the CLACK network.
  • CLEANUP FSM is no more a CC_SEND FSM client.
  • CLEANUP FSM controls directly the p_dspin_clack port

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r445 | cfuguet | 2013-07-18 10:49:36 +0200 (Thu, 18 Jul 2013) | 7 lines

Bugfix in vci_mem_cache:

  • Adding missing "strings" for print_trace() function
  • Adding alloc_ivt fsm (Invalidate Table) in the

print_trace() function

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r455 | cfuguet | 2013-07-19 10:16:17 +0200 (Fri, 19 Jul 2013) | 8 lines

Merged

/trunk/modules/vci_mem_cache:449 with
/branches/v5/modules/vci_mem_cache:446.

This merge introduces into the branch the last modifications concerning
the VCI memory cache configuration interface


Merging vci_cc_vcache_wrapper from branches/v5 to trunk [444-467]

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r444 | cfuguet | 2013-07-17 14:46:46 +0200 (Wed, 17 Jul 2013) | 7 lines

Modifications in branches/v5/modules/vci_cc_vcache_wrapper:

  • Renaming FROM_MC DSPIN flits fields in M2P
  • Renaming FROM_L1 DSPIN flits fields in P2M
  • Renaming CLEANUP_ACK DSPIN flits fields in CLACK

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r446 | cfuguet | 2013-07-18 11:37:47 +0200 (Thu, 18 Jul 2013) | 13 lines

Modifications in vci_cc_vcache_wrapper:

  • Merging the states DCACHE/ICACHE_CC_BROADCAST and DCACHE/ICACHE_CC_INVAL. This is because, the BROADCAST INVALIDATE and the MULTICAST INVALIDATE are both acknowledged by a CLEANUP.
  • Adding third port for the clack coherence network.
  • Renaming the port dspin_in to dspin_m2p and the port dspin_out to dspin_p2m

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r454 | haoliu | 2013-07-19 10:15:13 +0200 (Fri, 19 Jul 2013) | 2 lines

modified CC_RECEIVE FSM and CC_CHECK FSM (icache and dcache) for new
version V5

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r461 | cfuguet | 2013-07-19 15:49:43 +0200 (Fri, 19 Jul 2013) | 9 lines

Bugfix in vci_cc_vcache_wrapper:

  • In the states DCACHE/ICACHE CC_UPDT the FSM returns to the state CC_CHECK only when the cc_send_req is occupied.

We must not return to the CC_CHECK state if not ROK of the
DATA FIFO because the counter word counter will be reset.

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r462 | cfuguet | 2013-07-19 16:26:26 +0200 (Fri, 19 Jul 2013) | 8 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. We can handle a CLACK and a CC request if the latter does a MISS match. This is because the CC request doing MISS match does not need to access the directory

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r463 | cfuguet | 2013-07-19 16:52:06 +0200 (Fri, 19 Jul 2013) | 12 lines

Modification in vci_cc_vcache_wrapper:

  • Optimization in DCACHE/ICACHE CC_CHECK state. If pending request to CC_SEND, we wait in the CC_CHECK state. Doing this, during the wait, we can handle incoming CLACK avoiding any deadlock situation.

The states CC_UPDT and CC_INVAL do not need to test anymore if
there is a pending request to CC_SEND.


Merging tsar_generic_xbar from branches/v5 to trunk [447-467]

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r447 | cfuguet | 2013-07-18 16:12:05 +0200 (Thu, 18 Jul 2013) | 8 lines

Adding tsar_generic_xbar platform in branches/v5/platforms:

  • This platform contains a third local crossbar interconnect for the CLACK network.
  • It works only in a monocluster topology

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r448 | cfuguet | 2013-07-18 17:51:18 +0200 (Thu, 18 Jul 2013) | 9 lines

Modification in branches/v5/platforms/tsar_generic_xbar:

  • Adding a DSPIN router to the platform to allow the inter-cluster communication for the CLACK commands.

With this modification, the tsar_generic_xbar platform can be used
for multi-cluster simulations

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r466 | cfuguet | 2013-07-23 17:01:49 +0200 (Tue, 23 Jul 2013) | 9 lines

Modifications in branches/v5 vci_mem_cache:

  • Replacing the third router CLACK by a third virtual channel in the new virtual_dspin_router supporting several virtual channels.

The third channel has been added in the COMMAND router.

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r467 | cfuguet | 2013-07-23 17:23:13 +0200 (Tue, 23 Jul 2013) | 5 lines

Modifications in branches/v5 tsar_generic_xbar:

  • Adding preprocessor conditional statements for ALMOS support


Merging dspin_dhccp_param from branches/v5 to trunk [377-467]

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r442 | cfuguet | 2013-07-17 12:13:51 +0200 (Wed, 17 Jul 2013) | 13 lines

Modifications in branches/v5/communication/dspin_dhccp_param:

  • Renaming FROM_MC fields in M2P
  • Renaming FROM_L1 fields in P2M
  • Renaming CLEANUP_ACK fields in CLACK
File size: 2.7 KB
Line 
1
2# -*- python -*-
3
4Module('caba:vci_cc_vcache_wrapper',
5            classname = 'soclib::caba::VciCcVCacheWrapper',
6
7            tmpl_parameters = [
8            parameter.Module('vci_param', default = 'caba:vci_param'),
9            parameter.Int('dspin_in_width'),
10            parameter.Int('dspin_out_width'),
11                parameter.Module('iss_t')
12        ],
13
14            header_files = [ '../source/include/vci_cc_vcache_wrapper.h' ],
15
16            implementation_files = [ '../source/src/vci_cc_vcache_wrapper.cpp' ],
17
18            uses = [
19            Uses('caba:base_module'),
20            Uses('common:mapping_table'),
21                Uses('common:iss2'),
22                Uses('caba:multi_write_buffer'),
23                Uses('caba:generic_fifo'),
24                Uses('caba:generic_cache_tsar',
25                addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
26                parameter.Reference('addr_size'))),
27            Uses('caba:generic_tlb', 
28                addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
29                parameter.Reference('addr_size'))),
30            Uses('common:address_masking_table', 
31                data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 
32                parameter.Reference('addr_size'))
33            ),
34                        Uses('caba:dspin_dhccp_param'),
35        ],
36
37            ports = [
38            Port('caba:vci_initiator', 'p_vci'),
39            Port('caba:dspin_input', 'p_dspin_m2p', 
40                  dspin_data_size = parameter.Reference('dspin_in_width')),
41            Port('caba:dspin_output', 'p_dspin_p2m', 
42                  dspin_data_size = parameter.Reference('dspin_out_width')),
43            Port('caba:dspin_input', 'p_dspin_clack', 
44                  dspin_data_size = parameter.Reference('dspin_in_width')),
45                Port('caba:bit_in','p_irq', parameter.Constant('n_irq')),
46                Port('caba:bit_in', 'p_resetn', auto = 'resetn'),
47                Port('caba:clock_in', 'p_clk', auto = 'clock')
48        ],
49
50            instance_parameters = [
51            parameter.Int('proc_id'),
52                parameter.Module('mt', 'common:mapping_table'),
53                parameter.Module('mc', 'common:mapping_table'),
54                parameter.IntTab('initiator_rw_index'),
55                parameter.IntTab('initiator_c_index'),
56                parameter.IntTab('target_index'),
57            parameter.Int('itlb_ways'),
58            parameter.Int('itlb_sets'),
59            parameter.Int('dtlb_ways'),
60            parameter.Int('dtlb_sets'),
61            parameter.Int('icache_ways'),
62            parameter.Int('icache_sets'),
63            parameter.Int('icache_words'),
64            parameter.Int('dcache_ways'),
65            parameter.Int('dcache_sets'),
66            parameter.Int('dcache_words'),
67            parameter.Int('wbuf_nlines'),
68            parameter.Int('wbuf_nwords'),
69            parameter.Int('max_frozen_cycles')
70        ],
71)
72
73
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