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source: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h @ 458

Last change on this file since 458 was 456, checked in by lgarcia, 11 years ago

Introduction of RWT branch
New components :
-dspin_rwt_param (Cleanup Data, Rename dspin_dhccp_param to dspin_rwt_param)
-generic_cache_rwt (STATE : VALID_CC and VALID_NCC)
-vci_cc_vcache_wrapper (Hybrid cache Write-Through / Write-Back,

Cleanup Data, dirty bit, local CAS, new pktid for NCC miss read)

-vci_mem_cache (Support for Cleanup Data, Bit coherent for directory entry,

support NCC to CC mecanism)

File size: 49.7 KB

Line
1	/* -- c++ --
2	* File : vci_mem_cache.h
3	* Date : 26/10/2008
4	* Copyright : UPMC / LIP6
5	* Authors : Alain Greiner / Eric Guthmuller
6	*
7	* SOCLIB_LGPL_HEADER_BEGIN
8	*
9	* This file is part of SoCLib, GNU LGPLv2.1.
10	*
11	* SoCLib is free software; you can redistribute it and/or modify it
12	* under the terms of the GNU Lesser General Public License as published
13	* by the Free Software Foundation; version 2.1 of the License.
14	*
15	* SoCLib is distributed in the hope that it will be useful, but
16	* WITHOUT ANY WARRANTY; without even the implied warranty of
17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
18	* Lesser General Public License for more details.
19	*
20	* You should have received a copy of the GNU Lesser General Public
21	* License along with SoCLib; if not, write to the Free Software
22	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23	* 02110-1301 USA
24	*
25	* SOCLIB_LGPL_HEADER_END
26	*
27	* Maintainers: alain eric.guthmuller@polytechnique.edu
28	* cesar.fuguet-tortolero@lip6.fr
29	* alexandre.joannou@lip6.fr
30	*/
31
32	#ifndef SOCLIB_CABA_MEM_CACHE_H
33	#define SOCLIB_CABA_MEM_CACHE_H
34
35	#include <inttypes.h>
36	#include <systemc>
37	#include <list>
38	#include <cassert>
39	#include "arithmetics.h"
40	#include "alloc_elems.h"
41	#include "caba_base_module.h"
42	#include "vci_target.h"
43	#include "vci_initiator.h"
44	#include "generic_fifo.h"
45	#include "mapping_table.h"
46	#include "int_tab.h"
47	#include "generic_llsc_global_table.h"
48	#include "mem_cache_directory.h"
49	#include "xram_transaction.h"
50	#include "update_tab.h"
51	#include "dspin_interface.h"
52	#include "dspin_rwt_param.h"
53
54	#define TRT_ENTRIES 4 // Number of entries in TRT
55	#define UPT_ENTRIES 4 // Number of entries in UPT
56	#define HEAP_ENTRIES 1024 // Number of entries in HEAP
57
58	namespace soclib { namespace caba {
59
60	using namespace sc_core;
61
62	template<typename vci_param_int,
63	typename vci_param_ext,
64	size_t dspin_in_width,
65	size_t dspin_out_width>
66	class VciMemCache
67	: public soclib::caba::BaseModule
68	{
69	typedef typename vci_param_int::fast_addr_t addr_t;
70	typedef typename sc_dt::sc_uint<64> wide_data_t;
71	typedef uint32_t data_t;
72	typedef uint32_t tag_t;
73	typedef uint32_t be_t;
74	typedef uint32_t copy_t;
75
76	/* States of the TGT_CMD fsm */
77	enum tgt_cmd_fsm_state_e
78	{
79	TGT_CMD_IDLE,
80	TGT_CMD_ERROR,
81	TGT_CMD_READ,
82	TGT_CMD_WRITE,
83	TGT_CMD_CAS,
84	TGT_CMD_CONFIG
85	};
86
87	/* States of the TGT_RSP fsm */
88	enum tgt_rsp_fsm_state_e
89	{
90	TGT_RSP_CONFIG_IDLE,
91	TGT_RSP_TGT_CMD_IDLE,
92	TGT_RSP_READ_IDLE,
93	TGT_RSP_WRITE_IDLE,
94	TGT_RSP_CAS_IDLE,
95	TGT_RSP_XRAM_IDLE,
96	TGT_RSP_MULTI_ACK_IDLE,
97	TGT_RSP_CLEANUP_IDLE,
98	TGT_RSP_CONFIG,
99	TGT_RSP_TGT_CMD,
100	TGT_RSP_READ,
101	TGT_RSP_WRITE,
102	TGT_RSP_CAS,
103	TGT_RSP_XRAM,
104	TGT_RSP_MULTI_ACK,
105	TGT_RSP_CLEANUP
106	};
107
108	/* States of the DSPIN_TGT fsm */
109	enum cc_receive_fsm_state_e
110	{
111	CC_RECEIVE_IDLE,
112	CC_RECEIVE_CLEANUP,
113	CC_RECEIVE_CLEANUP_EOP,
114	CC_RECEIVE_MULTI_ACK
115	};
116
117	/* States of the CC_SEND fsm */
118	enum cc_send_fsm_state_e
119	{
120	CC_SEND_CONFIG_IDLE,
121	CC_SEND_XRAM_RSP_IDLE,
122	CC_SEND_WRITE_IDLE,
123	CC_SEND_CAS_IDLE,
124	CC_SEND_CLEANUP_IDLE,
125	CC_SEND_CONFIG_INVAL_HEADER,
126	CC_SEND_CONFIG_INVAL_NLINE,
127	CC_SEND_CONFIG_BRDCAST_HEADER,
128	CC_SEND_CONFIG_BRDCAST_NLINE,
129	CC_SEND_CLEANUP_ACK,
130	CC_SEND_XRAM_RSP_BRDCAST_HEADER,
131	CC_SEND_XRAM_RSP_BRDCAST_NLINE,
132	CC_SEND_XRAM_RSP_INVAL_HEADER,
133	CC_SEND_XRAM_RSP_INVAL_NLINE,
134	CC_SEND_READ_NCC_INVAL_HEADER,
135	CC_SEND_READ_NCC_INVAL_NLINE,
136	CC_SEND_WRITE_NCC_INVAL_HEADER,
137	CC_SEND_WRITE_NCC_INVAL_NLINE,
138	CC_SEND_WRITE_BRDCAST_HEADER,
139	CC_SEND_WRITE_BRDCAST_NLINE,
140	CC_SEND_WRITE_UPDT_HEADER,
141	CC_SEND_WRITE_UPDT_NLINE,
142	CC_SEND_WRITE_UPDT_DATA,
143	CC_SEND_CAS_BRDCAST_HEADER,
144	CC_SEND_CAS_BRDCAST_NLINE,
145	CC_SEND_CAS_UPDT_HEADER,
146	CC_SEND_CAS_UPDT_NLINE,
147	CC_SEND_CAS_UPDT_DATA,
148	CC_SEND_CAS_UPDT_DATA_HIGH
149	};
150
151	/* States of the MULTI_ACK fsm */
152	enum multi_ack_fsm_state_e
153	{
154	MULTI_ACK_IDLE,
155	MULTI_ACK_UPT_LOCK,
156	MULTI_ACK_UPT_CLEAR,
157	MULTI_ACK_WRITE_RSP,
158	MULTI_ACK_CONFIG_ACK
159	};
160
161	/* States of the CONFIG fsm */
162	enum config_fsm_state_e
163	{
164	CONFIG_IDLE,
165	CONFIG_LOOP,
166	CONFIG_RSP,
167	CONFIG_DIR_REQ,
168	CONFIG_DIR_ACCESS,
169	CONFIG_DIR_UPT_LOCK,
170	CONFIG_BC_SEND,
171	CONFIG_BC_WAIT,
172	CONFIG_INV_SEND,
173	CONFIG_HEAP_REQ,
174	CONFIG_HEAP_SCAN,
175	CONFIG_HEAP_LAST,
176	CONFIG_INV_WAIT
177	};
178
179	/* States of the READ fsm */
180	enum read_fsm_state_e
181	{
182	READ_IDLE,
183	READ_DIR_REQ,
184	READ_DIR_LOCK,
185	READ_UPT_LOCK,
186	READ_WAIT,
187	READ_DIR_HIT,
188	READ_HEAP_REQ,
189	READ_HEAP_LOCK,
190	READ_HEAP_WRITE,
191	READ_HEAP_ERASE,
192	READ_HEAP_LAST,
193	READ_RSP,
194	READ_TRT_LOCK,
195	READ_TRT_SET,
196	READ_TRT_REQ
197	};
198
199	/* States of the WRITE fsm */
200	enum write_fsm_state_e
201	{
202	WRITE_IDLE,
203	WRITE_NEXT,
204	WRITE_DIR_REQ,
205	WRITE_DIR_LOCK,
206	WRITE_UPT_LOCK_HIT_WB,
207	WRITE_DIR_READ,
208	WRITE_DIR_HIT,
209	WRITE_UPT_LOCK,
210	WRITE_UPT_HEAP_LOCK,
211	WRITE_UPT_REQ,
212	WRITE_UPT_NEXT,
213	WRITE_UPT_DEC,
214	WRITE_RSP,
215	WRITE_MISS_UPT_LOCK,
216	WRITE_MISS_TRT_LOCK,
217	WRITE_MISS_TRT_DATA,
218	WRITE_MISS_TRT_SET,
219	WRITE_MISS_XRAM_REQ,
220	WRITE_BC_TRT_LOCK,
221	WRITE_BC_UPT_LOCK,
222	WRITE_BC_DIR_INVAL,
223	WRITE_BC_CC_SEND,
224	WRITE_BC_XRAM_REQ,
225	WRITE_WAIT
226	};
227
228	/* States of the IXR_RSP fsm */
229	enum ixr_rsp_fsm_state_e
230	{
231	IXR_RSP_IDLE,
232	IXR_RSP_ACK,
233	IXR_RSP_TRT_ERASE,
234	IXR_RSP_TRT_READ
235	};
236
237	/* States of the XRAM_RSP fsm */
238	enum xram_rsp_fsm_state_e
239	{
240	XRAM_RSP_IDLE,
241	XRAM_RSP_TRT_COPY,
242	XRAM_RSP_TRT_DIRTY,
243	XRAM_RSP_DIR_LOCK,
244	XRAM_RSP_DIR_UPDT,
245	XRAM_RSP_DIR_RSP,
246	XRAM_RSP_INVAL_LOCK,
247	XRAM_RSP_INVAL_WAIT,
248	XRAM_RSP_INVAL,
249	XRAM_RSP_WRITE_DIRTY,
250	XRAM_RSP_HEAP_REQ,
251	XRAM_RSP_HEAP_ERASE,
252	XRAM_RSP_HEAP_LAST,
253	XRAM_RSP_ERROR_ERASE,
254	XRAM_RSP_ERROR_RSP
255	};
256
257	/* States of the IXR_CMD fsm */
258	enum ixr_cmd_fsm_state_e
259	{
260	IXR_CMD_READ_IDLE,
261	IXR_CMD_WRITE_IDLE,
262	IXR_CMD_CAS_IDLE,
263	IXR_CMD_XRAM_IDLE,
264	IXR_CMD_CLEANUP_IDLE,
265	IXR_CMD_READ,
266	IXR_CMD_WRITE,
267	IXR_CMD_CAS,
268	IXR_CMD_XRAM,
269	IXR_CMD_CLEANUP_DATA
270	};
271
272	/* States of the CAS fsm */
273	enum cas_fsm_state_e
274	{
275	CAS_IDLE,
276	CAS_DIR_REQ,
277	CAS_DIR_LOCK,
278	CAS_DIR_HIT_READ,
279	CAS_DIR_HIT_COMPARE,
280	CAS_DIR_HIT_WRITE,
281	CAS_UPT_LOCK,
282	CAS_UPT_HEAP_LOCK,
283	CAS_UPT_REQ,
284	CAS_UPT_NEXT,
285	CAS_BC_TRT_LOCK,
286	CAS_BC_UPT_LOCK,
287	CAS_BC_DIR_INVAL,
288	CAS_BC_CC_SEND,
289	CAS_BC_XRAM_REQ,
290	CAS_RSP_FAIL,
291	CAS_RSP_SUCCESS,
292	CAS_MISS_TRT_LOCK,
293	CAS_MISS_TRT_SET,
294	CAS_MISS_XRAM_REQ,
295	CAS_WAIT
296	};
297
298	/* States of the CLEANUP fsm */
299	enum cleanup_fsm_state_e
300	{
301	CLEANUP_IDLE,
302	CLEANUP_GET_NLINE,
303	CLEANUP_GET_DATA,
304	CLEANUP_DIR_REQ,
305	CLEANUP_DIR_LOCK,
306	CLEANUP_DIR_WRITE,
307	CLEANUP_UPT_LOCK_DATA,
308	CLEANUP_UPT_CLEAR_DATA,
309	CLEANUP_READ_RSP,
310	CLEANUP_HEAP_REQ,
311	CLEANUP_HEAP_LOCK,
312	CLEANUP_HEAP_SEARCH,
313	CLEANUP_HEAP_CLEAN,
314	CLEANUP_HEAP_FREE,
315	CLEANUP_UPT_LOCK,
316	CLEANUP_UPT_DECREMENT,
317	CLEANUP_UPT_CLEAR,
318	CLEANUP_WRITE_RSP,
319	CLEANUP_IXR_REQ,
320	CLEANUP_WAIT,
321	CLEANUP_CONFIG_ACK,
322	CLEANUP_SEND_CLACK
323	};
324
325	/* States of the ALLOC_DIR fsm */
326	enum alloc_dir_fsm_state_e
327	{
328	ALLOC_DIR_RESET,
329	ALLOC_DIR_CONFIG,
330	ALLOC_DIR_READ,
331	ALLOC_DIR_WRITE,
332	ALLOC_DIR_CAS,
333	ALLOC_DIR_CLEANUP,
334	ALLOC_DIR_XRAM_RSP
335	};
336
337	/* States of the ALLOC_TRT fsm */
338	enum alloc_trt_fsm_state_e
339	{
340	ALLOC_TRT_READ,
341	ALLOC_TRT_WRITE,
342	ALLOC_TRT_CAS,
343	ALLOC_TRT_XRAM_RSP,
344	ALLOC_TRT_IXR_RSP,
345	ALLOC_TRT_CLEANUP
346	};
347
348	/* States of the ALLOC_UPT fsm */
349	enum alloc_upt_fsm_state_e
350	{
351	ALLOC_UPT_CONFIG,
352	ALLOC_UPT_WRITE,
353	ALLOC_UPT_XRAM_RSP,
354	ALLOC_UPT_MULTI_ACK,
355	ALLOC_UPT_CLEANUP,
356	ALLOC_UPT_CAS,
357	ALLOC_UPT_READ
358	};
359
360	/* States of the ALLOC_HEAP fsm */
361	enum alloc_heap_fsm_state_e
362	{
363	ALLOC_HEAP_RESET,
364	ALLOC_HEAP_READ,
365	ALLOC_HEAP_WRITE,
366	ALLOC_HEAP_CAS,
367	ALLOC_HEAP_CLEANUP,
368	ALLOC_HEAP_XRAM_RSP,
369	ALLOC_HEAP_CONFIG
370	};
371
372	/* transaction type, pktid field */
373	enum transaction_type_e
374	{
375	// b3 unused
376	// b2 READ / NOT READ
377	// Si READ
378	// b1 DATA / INS
379	// b0 UNC / MISS
380	// Si NOT READ
381	// b1 accÃšs table llsc type SW / other
382	// b2 WRITE/CAS/LL/SC
383	TYPE_READ_DATA_UNC = 0x0,
384	TYPE_READ_DATA_MISS = 0x1,
385	TYPE_READ_INS_UNC = 0x2,
386	TYPE_READ_INS_MISS = 0x3,
387	TYPE_WRITE = 0x4,
388	TYPE_CAS = 0x5,
389	TYPE_LL = 0x6,
390	TYPE_SC = 0x7
391	};
392
393	/* SC return values */
394	enum sc_status_type_e
395	{
396	SC_SUCCESS = 0x00000000,
397	SC_FAIL = 0x00000001
398	};
399
400	/* Configuration commands */
401	enum cmd_config_type_e
402	{
403	CMD_CONFIG_INVAL = 0,
404	CMD_CONFIG_SYNC = 1
405	};
406
407	// debug variables (for each FSM)
408	bool m_debug;
409	bool m_debug_previous_valid;
410	size_t m_debug_previous_count;
411	bool m_debug_previous_dirty;
412	sc_signal<data_t>* m_debug_previous_data;
413	sc_signal<data_t>* m_debug_data;
414
415	bool m_monitor_ok;
416	addr_t m_monitor_base;
417	addr_t m_monitor_length;
418
419	// instrumentation counters
420	uint32_t m_cpt_cycles; // Counter of cycles
421
422	uint32_t m_cpt_read; // Number of READ transactions
423	uint32_t m_cpt_read_remote; // number of remote READ transactions
424	uint32_t m_cpt_read_flits; // number of flits for READs
425	uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs
426
427	uint32_t m_cpt_read_miss; // Number of MISS READ
428
429	uint32_t m_cpt_write; // Number of WRITE transactions
430	uint32_t m_cpt_write_remote; // number of remote WRITE transactions
431	uint32_t m_cpt_write_flits; // number of flits for WRITEs
432	uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs
433
434	uint32_t m_cpt_write_miss; // Number of MISS WRITE
435	uint32_t m_cpt_write_cells; // Cumulated length for WRITE transactions
436	uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions
437	uint32_t m_cpt_update; // Number of UPDATE transactions
438	uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt
439	uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt
440	uint32_t m_cpt_update_mult; // Number of targets for UPDATE
441	uint32_t m_cpt_inval; // Number of INVAL transactions
442	uint32_t m_cpt_inval_mult; // Number of targets for INVAL
443	uint32_t m_cpt_inval_brdcast; // Number of BROADCAST INVAL
444	uint32_t m_cpt_cleanup; // Number of CLEANUP transactions
445	uint32_t m_cpt_ll; // Number of LL transactions
446	uint32_t m_cpt_sc; // Number of SC transactions
447	uint32_t m_cpt_cas; // Number of CAS transactions
448
449	uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK
450	uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK
451	uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK
452	uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK
453	uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK
454	uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK
455	uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK
456	uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK
457	uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK
458	uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK
459
460	uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused
461	uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used
462	uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used
463	uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used
464	uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used
465	uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used
466
467	uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK
468	uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK
469	uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK
470	uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK
471	uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK
472
473	uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK
474	uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK
475	uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK
476	uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK
477	uint32_t m_cpt_ixr_fsm_n_trt_lock; // NB TRT LOCK
478
479	uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used
480	uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used
481	uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used
482	uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used
483	uint32_t m_cpt_ixr_fsm_trt_used; // NB cycles TRT LOCK used
484
485	uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused
486
487	uint32_t m_cpt_write_fsm_upt_lock; // wait UPT LOCK
488	uint32_t m_cpt_xram_rsp_fsm_upt_lock; // wait UPT LOCK
489	uint32_t m_cpt_multi_ack_fsm_upt_lock; // wait UPT LOCK
490	uint32_t m_cpt_cleanup_fsm_upt_lock; // wait UPT LOCK
491	uint32_t m_cpt_cas_fsm_upt_lock; // wait UPT LOCK
492
493	uint32_t m_cpt_write_fsm_n_upt_lock; // NB UPT LOCK
494	uint32_t m_cpt_xram_rsp_fsm_n_upt_lock; // NB UPT LOCK
495	uint32_t m_cpt_multi_ack_fsm_n_upt_lock; // NB UPT LOCK
496	uint32_t m_cpt_cleanup_fsm_n_upt_lock; // NB UPT LOCK
497	uint32_t m_cpt_cas_fsm_n_upt_lock; // NB UPT LOCK
498
499	uint32_t m_cpt_write_fsm_upt_used; // NB cycles UPT LOCK used
500	uint32_t m_cpt_xram_rsp_fsm_upt_used; // NB cycles UPT LOCK used
501	uint32_t m_cpt_multi_ack_fsm_upt_used; // NB cycles UPT LOCK used
502	uint32_t m_cpt_cleanup_fsm_upt_used; // NB cycles UPT LOCK used
503	uint32_t m_cpt_cas_fsm_upt_used; // NB cycles UPT LOCK used
504
505	uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused
506
507	uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK
508	uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK
509	uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK
510	uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK
511	uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK
512
513	uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK
514	uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK
515	uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK
516	uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK
517	uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK
518
519	uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used
520	uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used
521	uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used
522	uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used
523	uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used
524
525	uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused
526
527	//RWT
528	uint32_t m_cpt_cleanup_data;
529	uint32_t m_cpt_ncc_to_cc_read; // NB change from NCC to CC caused by a READ
530	uint32_t m_cpt_ncc_to_cc_write; // NB change from NCC to CC caused by a WRITE
531	uint32_t m_cpt_ncc_to_cc; // NB change from NCC to CC
532
533	uint32_t m_cpt_read_data_unc;
534	uint32_t m_cpt_read_data_miss_CC;
535	uint32_t m_cpt_read_ins_unc;
536	uint32_t m_cpt_read_ins_miss;
537	uint32_t m_cpt_read_ll_CC;
538	uint32_t m_cpt_read_data_miss_NCC;
539	uint32_t m_cpt_read_ll_NCC;
540	uint32_t m_cpt_read_WTF;
541
542	uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs
543
544	uint32_t m_cpt_update_flits; // Number of flits for UPDATEs
545	uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDATEs
546
547	uint32_t m_cpt_inval_cost; // Number of (flits * distance) for INVALs
548
549	uint32_t m_cpt_get;
550
551	uint32_t m_cpt_put;
552
553	size_t m_prev_count;
554
555	protected:
556
557	SC_HAS_PROCESS(VciMemCache);
558
559	public:
560	sc_in<bool> p_clk;
561	sc_in<bool> p_resetn;
562	soclib::caba::VciTarget<vci_param_int> p_vci_tgt;
563	soclib::caba::VciInitiator<vci_param_ext> p_vci_ixr;
564	soclib::caba::DspinInput<dspin_in_width> p_dspin_in;
565	soclib::caba::DspinOutput<dspin_out_width> p_dspin_out;
566
567	VciMemCache(
568	sc_module_name name, // Instance Name
569	const soclib::common::MappingTable &mtp, // Mapping table INT network
570	const soclib::common::MappingTable &mtx, // Mapping table RAM network
571	const soclib::common::IntTab &srcid_x, // global index RAM network
572	const soclib::common::IntTab &tgtid_d, // global index INT network
573	const size_t cc_global_id, // global index CC network
574	const size_t nways, // Number of ways per set
575	const size_t nsets, // Number of sets
576	const size_t nwords, // Number of words per line
577	const size_t max_copies, // max number of copies
578	const size_t heap_size=HEAP_ENTRIES,
579	const size_t trt_lines=TRT_ENTRIES,
580	const size_t upt_lines=UPT_ENTRIES,
581	const size_t debug_start_cycle=0,
582	const bool debug_ok=false );
583
584	~VciMemCache();
585
586	void clear_stats();
587	void print_stats();
588	void print_trace();
589	void cache_monitor(addr_t addr);
590	void start_monitor(addr_t addr, addr_t length);
591	void stop_monitor();
592
593	private:
594
595	void transition();
596	void genMoore();
597	void check_monitor(addr_t addr, data_t data, bool read);
598
599	// Component attributes
600	std::list<soclib::common::Segment> m_seglist; // segments allocated
601	size_t m_nseg; // number of segments
602	soclib::common::Segment **m_seg; // array of segments pointers
603	size_t m_seg_config; // config segment index
604	const size_t m_srcid_x; // global index on RAM network
605	const size_t m_initiators; // Number of initiators
606	const size_t m_heap_size; // Size of the heap
607	const size_t m_ways; // Number of ways in a set
608	const size_t m_sets; // Number of cache sets
609	const size_t m_words; // Number of words in a line
610	const size_t m_cc_global_id; // global_index on cc network
611	size_t m_debug_start_cycle;
612	bool m_debug_ok;
613	uint32_t m_trt_lines;
614	TransactionTab m_trt; // xram transaction table
615	uint32_t m_upt_lines;
616	UpdateTab m_upt; // pending update & invalidate
617	CacheDirectory m_cache_directory; // data cache directory
618	CacheData m_cache_data; // data array[set][way][word]
619	HeapDirectory m_heap; // heap for copies
620	size_t m_max_copies; // max number of copies in heap
621	GenericLLSCGlobalTable
622	< 32 , // number of slots
623	4096, // number of processors in the system
624	8000, // registration life (# of LL operations)
625	addr_t > m_llsc_table; // ll/sc registration table
626
627	// adress masks
628	const soclib::common::AddressMaskingTable<addr_t> m_x;
629	const soclib::common::AddressMaskingTable<addr_t> m_y;
630	const soclib::common::AddressMaskingTable<addr_t> m_z;
631	const soclib::common::AddressMaskingTable<addr_t> m_nline;
632
633	// broadcast address
634	uint32_t m_broadcast_boundaries;
635
636	//////////////////////////////////////////////////
637	// Registers controlled by the TGT_CMD fsm
638	//////////////////////////////////////////////////
639
640	sc_signal<int> r_tgt_cmd_fsm;
641
642	// Fifo between TGT_CMD fsm and READ fsm
643	GenericFifo<addr_t> m_cmd_read_addr_fifo;
644	GenericFifo<size_t> m_cmd_read_length_fifo;
645	GenericFifo<size_t> m_cmd_read_srcid_fifo;
646	GenericFifo<size_t> m_cmd_read_trdid_fifo;
647	GenericFifo<size_t> m_cmd_read_pktid_fifo;
648
649	// Fifo between TGT_CMD fsm and WRITE fsm
650	GenericFifo<addr_t> m_cmd_write_addr_fifo;
651	GenericFifo<bool> m_cmd_write_eop_fifo;
652	GenericFifo<size_t> m_cmd_write_srcid_fifo;
653	GenericFifo<size_t> m_cmd_write_trdid_fifo;
654	GenericFifo<size_t> m_cmd_write_pktid_fifo;
655	GenericFifo<data_t> m_cmd_write_data_fifo;
656	GenericFifo<be_t> m_cmd_write_be_fifo;
657
658	// Fifo between TGT_CMD fsm and CAS fsm
659	GenericFifo<addr_t> m_cmd_cas_addr_fifo;
660	GenericFifo<bool> m_cmd_cas_eop_fifo;
661	GenericFifo<size_t> m_cmd_cas_srcid_fifo;
662	GenericFifo<size_t> m_cmd_cas_trdid_fifo;
663	GenericFifo<size_t> m_cmd_cas_pktid_fifo;
664	GenericFifo<data_t> m_cmd_cas_wdata_fifo;
665
666	// Fifo between CC_RECEIVE fsm and CLEANUP fsm
667	GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo;
668
669	// Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
670	GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo;
671
672	// Buffer between TGT_CMD fsm and TGT_RSP fsm
673	// (segmentation violation response request)
674	sc_signal<bool> r_tgt_cmd_to_tgt_rsp_req;
675
676	sc_signal<uint32_t> r_tgt_cmd_to_tgt_rsp_rdata;
677	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_error;
678	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_srcid;
679	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_trdid;
680	sc_signal<size_t> r_tgt_cmd_to_tgt_rsp_pktid;
681
682	sc_signal<addr_t> r_tgt_cmd_config_addr;
683	sc_signal<size_t> r_tgt_cmd_config_cmd;
684
685	///////////////////////////////////////////////////////
686	// Registers controlled by the CONFIG fsm
687	///////////////////////////////////////////////////////
688
689	sc_signal<int> r_config_fsm; // FSM state
690	sc_signal<bool> r_config_lock; // lock protecting exclusive access
691	sc_signal<int> r_config_cmd; // config request status
692	sc_signal<addr_t> r_config_address; // target buffer physical address
693	sc_signal<size_t> r_config_srcid; // config request srcid
694	sc_signal<size_t> r_config_trdid; // config request trdid
695	sc_signal<size_t> r_config_pktid; // config request pktid
696	sc_signal<size_t> r_config_nlines; // number of lines covering the buffer
697	sc_signal<size_t> r_config_dir_way; // DIR: selected way
698	sc_signal<size_t> r_config_dir_count; // DIR: number of copies
699	sc_signal<bool> r_config_dir_is_cnt; // DIR: counter mode (broadcast required)
700	sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
701	sc_signal<bool> r_config_dir_copy_inst; // DIR: first copy L1 type
702	sc_signal<size_t> r_config_dir_next_ptr; // DIR: index of next copy in HEAP
703	sc_signal<size_t> r_config_heap_next; // current pointer to scan HEAP
704
705	sc_signal<size_t> r_config_upt_index; // UPT index
706
707	// Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
708	sc_signal<bool> r_config_to_tgt_rsp_req; // valid request
709	sc_signal<bool> r_config_to_tgt_rsp_error; // error response
710	sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
711	sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
712	sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
713
714	// Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
715	sc_signal<bool> r_config_to_cc_send_multi_req; // multi-inval request
716	sc_signal<bool> r_config_to_cc_send_brdcast_req; // broadcast-inval request
717	sc_signal<addr_t> r_config_to_cc_send_nline; // line index
718	sc_signal<size_t> r_config_to_cc_send_trdid; // UPT index
719	GenericFifo<bool> m_config_to_cc_send_inst_fifo; // fifo for the L1 type
720	GenericFifo<size_t> m_config_to_cc_send_srcid_fifo; // fifo for owners srcid
721
722	#if L1_MULTI_CACHE
723	GenericFifo<size_t> m_config_to_cc_send_cache_id_fifo; // fifo for cache_id
724	#endif
725
726	///////////////////////////////////////////////////////
727	// Registers controlled by the READ fsm
728	///////////////////////////////////////////////////////
729
730	sc_signal<int> r_read_fsm; // FSM state
731	sc_signal<size_t> r_read_copy; // Srcid of the first copy
732	sc_signal<size_t> r_read_copy_cache; // Srcid of the first copy
733	sc_signal<bool> r_read_copy_inst; // Type of the first copy
734	sc_signal<tag_t> r_read_tag; // cache line tag (in directory)
735	sc_signal<bool> r_read_is_cnt; // is_cnt bit (in directory)
736	sc_signal<bool> r_read_lock; // lock bit (in directory)
737	sc_signal<bool> r_read_dirty; // dirty bit (in directory)
738	sc_signal<size_t> r_read_count; // number of copies
739	sc_signal<size_t> r_read_ptr; // pointer to the heap
740	sc_signal<data_t> * r_read_data; // data (one cache line)
741	sc_signal<size_t> r_read_way; // associative way (in cache)
742	sc_signal<size_t> r_read_trt_index; // Transaction Table index
743	sc_signal<size_t> r_read_next_ptr; // Next entry to point to
744	sc_signal<bool> r_read_last_free; // Last free entry
745	sc_signal<addr_t> r_read_ll_key; // LL key from the llsc_global_table
746
747	// Buffer between READ fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
748	sc_signal<bool> r_read_to_ixr_cmd_req; // valid request
749	sc_signal<addr_t> r_read_to_ixr_cmd_nline; // cache line index
750	sc_signal<size_t> r_read_to_ixr_cmd_trdid; // index in Transaction Table
751
752	// Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
753	sc_signal<bool> r_read_to_tgt_rsp_req; // valid request
754	sc_signal<size_t> r_read_to_tgt_rsp_srcid; // Transaction srcid
755	sc_signal<size_t> r_read_to_tgt_rsp_trdid; // Transaction trdid
756	sc_signal<size_t> r_read_to_tgt_rsp_pktid; // Transaction pktid
757	sc_signal<data_t> * r_read_to_tgt_rsp_data; // data (one cache line)
758	sc_signal<size_t> r_read_to_tgt_rsp_word; // first word of the response
759	sc_signal<size_t> r_read_to_tgt_rsp_length; // length of the response
760	sc_signal<addr_t> r_read_to_tgt_rsp_ll_key; // LL key from the llsc_global_table
761
762	//RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
763	sc_signal<bool> r_read_to_cc_send_req;
764	sc_signal<size_t> r_read_to_cc_send_dest;
765	sc_signal<addr_t> r_read_to_cc_send_nline;
766	sc_signal<bool> r_read_to_cc_send_inst;
767
768	//RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache)
769	sc_signal<bool> r_read_to_cleanup_req; // valid request
770	sc_signal<addr_t> r_read_to_cleanup_nline; // cache line index
771	sc_signal<size_t> r_read_to_cleanup_srcid;
772	sc_signal<size_t> r_read_to_cleanup_length;
773	sc_signal<size_t> r_read_to_cleanup_first_word;
774	sc_signal<bool> r_read_to_cleanup_cached_read;
775	sc_signal<bool> r_read_to_cleanup_is_ll;
776	sc_signal<addr_t> r_read_to_cleanup_addr;
777	sc_signal<addr_t> r_read_to_cleanup_ll_key;
778
779	//RWT:
780	sc_signal<bool> r_read_coherent; // State of the cache slot after transaction
781	sc_signal<bool> r_read_ll_done;
782
783	///////////////////////////////////////////////////////////////
784	// Registers controlled by the WRITE fsm
785	///////////////////////////////////////////////////////////////
786
787	sc_signal<int> r_write_fsm; // FSM state
788	sc_signal<addr_t> r_write_address; // first word address
789	sc_signal<size_t> r_write_word_index; // first word index in line
790	sc_signal<size_t> r_write_word_count; // number of words in line
791	sc_signal<size_t> r_write_srcid; // transaction srcid
792	sc_signal<size_t> r_write_trdid; // transaction trdid
793	sc_signal<size_t> r_write_pktid; // transaction pktid
794	sc_signal<data_t> * r_write_data; // data (one cache line)
795	sc_signal<be_t> * r_write_be; // one byte enable per word
796	sc_signal<bool> r_write_byte; // (BE != 0X0) and (BE != 0xF)
797	sc_signal<bool> r_write_is_cnt; // is_cnt bit (in directory)
798	sc_signal<bool> r_write_lock; // lock bit (in directory)
799	sc_signal<tag_t> r_write_tag; // cache line tag (in directory)
800	sc_signal<size_t> r_write_copy; // first owner of the line
801	sc_signal<size_t> r_write_copy_cache; // first owner of the line
802	sc_signal<bool> r_write_copy_inst; // is this owner a ICache ?
803	sc_signal<size_t> r_write_count; // number of copies
804	sc_signal<size_t> r_write_ptr; // pointer to the heap
805	sc_signal<size_t> r_write_next_ptr; // next pointer to the heap
806	sc_signal<bool> r_write_to_dec; // need to decrement update counter
807	sc_signal<size_t> r_write_way; // way of the line
808	sc_signal<size_t> r_write_trt_index; // index in Transaction Table
809	sc_signal<size_t> r_write_upt_index; // index in Update Table
810	sc_signal<bool> r_write_sc_fail; // sc command failed
811	sc_signal<bool> r_write_pending_sc; // sc command pending
812
813	// Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
814	sc_signal<bool> r_write_to_tgt_rsp_req; // valid request
815	sc_signal<size_t> r_write_to_tgt_rsp_srcid; // transaction srcid
816	sc_signal<size_t> r_write_to_tgt_rsp_trdid; // transaction trdid
817	sc_signal<size_t> r_write_to_tgt_rsp_pktid; // transaction pktid
818	sc_signal<bool> r_write_to_tgt_rsp_sc_fail; // sc command failed
819
820	// Buffer between WRITE fsm and IXR_CMD fsm (ask a missing cache line to XRAM)
821	sc_signal<bool> r_write_to_ixr_cmd_req; // valid request
822	sc_signal<bool> r_write_to_ixr_cmd_write; // write request
823	sc_signal<addr_t> r_write_to_ixr_cmd_nline; // cache line index
824	sc_signal<data_t> * r_write_to_ixr_cmd_data; // cache line data
825	sc_signal<size_t> r_write_to_ixr_cmd_trdid; // index in Transaction Table
826
827	// Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
828	sc_signal<bool> r_write_to_cc_send_multi_req; // valid multicast request
829	sc_signal<bool> r_write_to_cc_send_brdcast_req; // valid brdcast request
830	sc_signal<addr_t> r_write_to_cc_send_nline; // cache line index
831	sc_signal<size_t> r_write_to_cc_send_trdid; // index in Update Table
832	sc_signal<data_t> * r_write_to_cc_send_data; // data (one cache line)
833	sc_signal<be_t> * r_write_to_cc_send_be; // word enable
834	sc_signal<size_t> r_write_to_cc_send_count; // number of words in line
835	sc_signal<size_t> r_write_to_cc_send_index; // index of first word in line
836	GenericFifo<bool> m_write_to_cc_send_inst_fifo; // fifo for the L1 type
837	GenericFifo<size_t> m_write_to_cc_send_srcid_fifo; // fifo for srcids
838
839	#if L1_MULTI_CACHE
840	GenericFifo<size_t> m_write_to_cc_send_cache_id_fifo; // fifo for srcids
841	#endif
842
843	// Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry)
844	sc_signal<bool> r_write_to_multi_ack_req; // valid request
845	sc_signal<size_t> r_write_to_multi_ack_upt_index; // index in update table
846
847	// RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
848	sc_signal<bool> r_write_to_cleanup_req; // valid request
849	sc_signal<addr_t> r_write_to_cleanup_nline; // cache line index
850
851	// RWT
852	sc_signal<bool> r_write_coherent; // cache slot state after transaction
853
854	//Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
855	sc_signal<bool> r_write_to_cc_send_req;
856	sc_signal<size_t> r_write_to_cc_send_dest;
857
858
859	/////////////////////////////////////////////////////////
860	// Registers controlled by MULTI_ACK fsm
861	//////////////////////////////////////////////////////////
862
863	sc_signal<int> r_multi_ack_fsm; // FSM state
864	sc_signal<size_t> r_multi_ack_upt_index; // index in the Update Table
865	sc_signal<size_t> r_multi_ack_srcid; // pending write srcid
866	sc_signal<size_t> r_multi_ack_trdid; // pending write trdid
867	sc_signal<size_t> r_multi_ack_pktid; // pending write pktid
868	sc_signal<addr_t> r_multi_ack_nline; // pending write nline
869
870	// signaling completion of multi-inval to CONFIG fsm
871	sc_signal<bool> r_multi_ack_to_config_ack;
872
873	// Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction)
874	sc_signal<bool> r_multi_ack_to_tgt_rsp_req; // valid request
875	sc_signal<size_t> r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid
876	sc_signal<size_t> r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid
877	sc_signal<size_t> r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid
878
879	///////////////////////////////////////////////////////
880	// Registers controlled by CLEANUP fsm
881	///////////////////////////////////////////////////////
882
883	sc_signal<int> r_cleanup_fsm; // FSM state
884	sc_signal<size_t> r_cleanup_srcid; // transaction srcid
885	sc_signal<bool> r_cleanup_inst; // Instruction or Data ?
886	sc_signal<size_t> r_cleanup_way_index; // L1 Cache Way index
887	sc_signal<addr_t> r_cleanup_nline; // cache line index
888
889	#if L1_MULTI_CACHE
890	sc_signal<size_t> r_cleanup_pktid; // transaction pktid
891	#endif
892
893	sc_signal<copy_t> r_cleanup_copy; // first copy
894	sc_signal<copy_t> r_cleanup_copy_cache; // first copy
895	sc_signal<size_t> r_cleanup_copy_inst; // type of the first copy
896	sc_signal<copy_t> r_cleanup_count; // number of copies
897	sc_signal<size_t> r_cleanup_ptr; // pointer to the heap
898	sc_signal<size_t> r_cleanup_prev_ptr; // previous pointer to the heap
899	sc_signal<size_t> r_cleanup_prev_srcid; // srcid of previous heap entry
900	sc_signal<size_t> r_cleanup_prev_cache_id; // srcid of previous heap entry
901	sc_signal<bool> r_cleanup_prev_inst; // inst bit of previous heap entry
902	sc_signal<size_t> r_cleanup_next_ptr; // next pointer to the heap
903	sc_signal<tag_t> r_cleanup_tag; // cache line tag (in directory)
904	sc_signal<bool> r_cleanup_is_cnt; // inst bit (in directory)
905	sc_signal<bool> r_cleanup_lock; // lock bit (in directory)
906	sc_signal<bool> r_cleanup_dirty; // dirty bit (in directory)
907	sc_signal<size_t> r_cleanup_way; // associative way (in cache)
908
909	sc_signal<size_t> r_cleanup_write_srcid; // srcid of write rsp
910	sc_signal<size_t> r_cleanup_write_trdid; // trdid of write rsp
911	sc_signal<size_t> r_cleanup_write_pktid; // pktid of write rsp
912
913	sc_signal<bool> r_cleanup_need_rsp; // write response required
914	sc_signal<bool> r_cleanup_need_ack; // config acknowledge required
915
916	sc_signal<size_t> r_cleanup_index; // index of the INVAL line (in the UPT)
917
918	// signaling completion of broadcast-inval to CONFIG fsm
919	sc_signal<bool> r_cleanup_to_config_ack;
920
921	// Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1)
922	sc_signal<bool> r_cleanup_to_tgt_rsp_req; // valid request
923	sc_signal<size_t> r_cleanup_to_tgt_rsp_srcid; // transaction srcid
924	sc_signal<size_t> r_cleanup_to_tgt_rsp_trdid; // transaction trdid
925	sc_signal<size_t> r_cleanup_to_tgt_rsp_pktid; // transaction pktid
926	sc_signal<addr_t> r_cleanup_to_tgt_rsp_ll_key;
927
928	// Buffer between CLEANUP fsm and CC_SEND fsm (acknowledge a cleanup command from L1)
929	sc_signal<bool> r_cleanup_to_cc_send_req; // valid request
930	sc_signal<size_t> r_cleanup_to_cc_send_srcid; // L1 srcid
931	sc_signal<size_t> r_cleanup_to_cc_send_set_index; // L1 set index
932	sc_signal<size_t> r_cleanup_to_cc_send_way_index; // L1 way index
933	sc_signal<bool> r_cleanup_to_cc_send_inst; // Instruction Cleanup Ack
934
935	//RWT
936	sc_signal<size_t> r_cleanup_read_srcid;
937	sc_signal<size_t> r_cleanup_read_trdid;
938	sc_signal<size_t> r_cleanup_read_pktid;
939	sc_signal<bool> r_cleanup_read_need_rsp;
940	sc_signal<bool> r_cleanup_to_tgt_rsp_type;
941	sc_signal<data_t> * r_cleanup_to_tgt_rsp_data;
942	sc_signal<size_t> r_cleanup_to_tgt_rsp_length;
943	sc_signal<size_t> r_cleanup_to_tgt_rsp_first_word;
944
945	///////////////////////////////////////////////////////
946	// Registers controlled by CAS fsm
947	///////////////////////////////////////////////////////
948
949	sc_signal<int> r_cas_fsm; // FSM state
950	sc_signal<data_t> r_cas_wdata; // write data word
951	sc_signal<data_t> * r_cas_rdata; // read data word
952	sc_signal<uint32_t> r_cas_lfsr; // lfsr for random introducing
953	sc_signal<size_t> r_cas_cpt; // size of command
954	sc_signal<copy_t> r_cas_copy; // Srcid of the first copy
955	sc_signal<copy_t> r_cas_copy_cache; // Srcid of the first copy
956	sc_signal<bool> r_cas_copy_inst; // Type of the first copy
957	sc_signal<size_t> r_cas_count; // number of copies
958	sc_signal<size_t> r_cas_ptr; // pointer to the heap
959	sc_signal<size_t> r_cas_next_ptr; // next pointer to the heap
960	sc_signal<bool> r_cas_is_cnt; // is_cnt bit (in directory)
961	sc_signal<bool> r_cas_dirty; // dirty bit (in directory)
962	sc_signal<size_t> r_cas_way; // way in directory
963	sc_signal<size_t> r_cas_set; // set in directory
964	sc_signal<data_t> r_cas_tag; // cache line tag (in directory)
965	sc_signal<size_t> r_cas_trt_index; // Transaction Table index
966	sc_signal<size_t> r_cas_upt_index; // Update Table index
967	sc_signal<data_t> * r_cas_data; // cache line data
968
969	sc_signal<bool> r_cas_coherent;
970
971	// Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
972	sc_signal<bool> r_cas_to_ixr_cmd_req; // valid request
973	sc_signal<addr_t> r_cas_to_ixr_cmd_nline; // cache line index
974	sc_signal<size_t> r_cas_to_ixr_cmd_trdid; // index in Transaction Table
975	sc_signal<bool> r_cas_to_ixr_cmd_write; // write request
976	sc_signal<data_t> * r_cas_to_ixr_cmd_data; // cache line data
977
978
979	// Buffer between CAS fsm and TGT_RSP fsm
980	sc_signal<bool> r_cas_to_tgt_rsp_req; // valid request
981	sc_signal<data_t> r_cas_to_tgt_rsp_data; // read data word
982	sc_signal<size_t> r_cas_to_tgt_rsp_srcid; // Transaction srcid
983	sc_signal<size_t> r_cas_to_tgt_rsp_trdid; // Transaction trdid
984	sc_signal<size_t> r_cas_to_tgt_rsp_pktid; // Transaction pktid
985
986	// Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches)
987	sc_signal<bool> r_cas_to_cc_send_multi_req; // valid request
988	sc_signal<bool> r_cas_to_cc_send_brdcast_req; // brdcast request
989	sc_signal<addr_t> r_cas_to_cc_send_nline; // cache line index
990	sc_signal<size_t> r_cas_to_cc_send_trdid; // index in Update Table
991	sc_signal<data_t> r_cas_to_cc_send_wdata; // data (one word)
992	sc_signal<bool> r_cas_to_cc_send_is_long; // it is a 64 bits CAS
993	sc_signal<data_t> r_cas_to_cc_send_wdata_high; // data high (one word)
994	sc_signal<size_t> r_cas_to_cc_send_index; // index of the word in line
995	GenericFifo<bool> m_cas_to_cc_send_inst_fifo; // fifo for the L1 type
996	GenericFifo<size_t> m_cas_to_cc_send_srcid_fifo; // fifo for srcids
997
998	#if L1_MULTI_CACHE
999	GenericFifo<size_t> m_cas_to_cc_send_cache_id_fifo; // fifo for srcids
1000	#endif
1001
1002	////////////////////////////////////////////////////
1003	// Registers controlled by the IXR_RSP fsm
1004	////////////////////////////////////////////////////
1005
1006	sc_signal<int> r_ixr_rsp_fsm; // FSM state
1007	sc_signal<size_t> r_ixr_rsp_trt_index; // TRT entry index
1008	sc_signal<size_t> r_ixr_rsp_cpt; // word counter
1009
1010	// Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM)
1011	sc_signal<bool> * r_ixr_rsp_to_xram_rsp_rok; // A xram response is ready
1012
1013	////////////////////////////////////////////////////
1014	// Registers controlled by the XRAM_RSP fsm
1015	////////////////////////////////////////////////////
1016
1017	sc_signal<int> r_xram_rsp_fsm; // FSM state
1018	sc_signal<size_t> r_xram_rsp_trt_index; // TRT entry index
1019	TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer
1020	sc_signal<bool> r_xram_rsp_victim_inval; // victim line invalidate
1021	sc_signal<bool> r_xram_rsp_victim_is_cnt; // victim line inst bit
1022	sc_signal<bool> r_xram_rsp_victim_dirty; // victim line dirty bit
1023	sc_signal<size_t> r_xram_rsp_victim_way; // victim line way
1024	sc_signal<size_t> r_xram_rsp_victim_set; // victim line set
1025	sc_signal<addr_t> r_xram_rsp_victim_nline; // victim line index
1026	sc_signal<copy_t> r_xram_rsp_victim_copy; // victim line first copy
1027	sc_signal<copy_t> r_xram_rsp_victim_copy_cache; // victim line first copy
1028	sc_signal<bool> r_xram_rsp_victim_copy_inst; // victim line type of first copy
1029	sc_signal<size_t> r_xram_rsp_victim_count; // victim line number of copies
1030	sc_signal<size_t> r_xram_rsp_victim_ptr; // victim line pointer to the heap
1031	sc_signal<data_t> * r_xram_rsp_victim_data; // victim line data
1032	sc_signal<size_t> r_xram_rsp_upt_index; // UPT entry index
1033	sc_signal<size_t> r_xram_rsp_next_ptr; // Next pointer to the heap
1034
1035	// Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache)
1036	sc_signal<bool> r_xram_rsp_to_tgt_rsp_req; // Valid request
1037	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid
1038	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid
1039	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid
1040	sc_signal<data_t> * r_xram_rsp_to_tgt_rsp_data; // data (one cache line)
1041	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_word; // first word index
1042	sc_signal<size_t> r_xram_rsp_to_tgt_rsp_length; // length of the response
1043	sc_signal<bool> r_xram_rsp_to_tgt_rsp_rerror; // send error to requester
1044	sc_signal<addr_t> r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table
1045
1046	// Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches)
1047	sc_signal<bool> r_xram_rsp_to_cc_send_multi_req; // Valid request
1048	sc_signal<bool> r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request
1049	sc_signal<addr_t> r_xram_rsp_to_cc_send_nline; // cache line index;
1050	sc_signal<size_t> r_xram_rsp_to_cc_send_trdid; // index of UPT entry
1051	GenericFifo<bool> m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type
1052	GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids
1053
1054	#if L1_MULTI_CACHE
1055	GenericFifo<size_t> m_xram_rsp_to_cc_send_cache_id_fifo; // fifo for srcids
1056	#endif
1057
1058	// Buffer between XRAM_RSP fsm and IXR_CMD fsm (XRAM write)
1059	sc_signal<bool> r_xram_rsp_to_ixr_cmd_req; // Valid request
1060	sc_signal<addr_t> r_xram_rsp_to_ixr_cmd_nline; // cache line index
1061	sc_signal<data_t> * r_xram_rsp_to_ixr_cmd_data; // cache line data
1062	sc_signal<size_t> r_xram_rsp_to_ixr_cmd_trdid; // index in transaction table
1063
1064	//RWT
1065	sc_signal<bool> r_xram_rsp_victim_coherent; // victim's cache slot state
1066	sc_signal<bool> r_xram_rsp_coherent; // coherence of the read
1067	////////////////////////////////////////////////////
1068	// Registers controlled by the IXR_CMD fsm
1069	////////////////////////////////////////////////////
1070
1071	sc_signal<int> r_ixr_cmd_fsm;
1072	sc_signal<size_t> r_ixr_cmd_cpt;
1073
1074	////////////////////////////////////////////////////
1075	// Registers controlled by TGT_RSP fsm
1076	////////////////////////////////////////////////////
1077
1078	sc_signal<int> r_tgt_rsp_fsm;
1079	sc_signal<size_t> r_tgt_rsp_cpt;
1080	sc_signal<bool> r_tgt_rsp_key_sent;
1081
1082	////////////////////////////////////////////////////
1083	// Registers controlled by CC_SEND fsm
1084	////////////////////////////////////////////////////
1085
1086	sc_signal<int> r_cc_send_fsm;
1087	sc_signal<size_t> r_cc_send_cpt;
1088	sc_signal<bool> r_cc_send_inst;
1089
1090	////////////////////////////////////////////////////
1091	// Registers controlled by CC_RECEIVE fsm
1092	////////////////////////////////////////////////////
1093
1094	sc_signal<int> r_cc_receive_fsm;
1095
1096	////////////////////////////////////////////////////
1097	// Registers controlled by ALLOC_DIR fsm
1098	////////////////////////////////////////////////////
1099
1100	sc_signal<int> r_alloc_dir_fsm;
1101	sc_signal<unsigned> r_alloc_dir_reset_cpt;
1102
1103	////////////////////////////////////////////////////
1104	// Registers controlled by ALLOC_TRT fsm
1105	////////////////////////////////////////////////////
1106
1107	sc_signal<int> r_alloc_trt_fsm;
1108
1109	////////////////////////////////////////////////////
1110	// Registers controlled by ALLOC_UPT fsm
1111	////////////////////////////////////////////////////
1112
1113	sc_signal<int> r_alloc_upt_fsm;
1114
1115	////////////////////////////////////////////////////
1116	// Registers controlled by ALLOC_HEAP fsm
1117	////////////////////////////////////////////////////
1118
1119	sc_signal<int> r_alloc_heap_fsm;
1120	sc_signal<unsigned> r_alloc_heap_reset_cpt;
1121
1122
1123	////////////////////////////////////////////////////
1124	// REGISTERS FOR ODCCP
1125	////////////////////////////////////////////////////
1126
1127	sc_signal<uint32_t> r_cleanup_data_index;
1128	sc_signal<uint32_t> r_cleanup_trdid;
1129	sc_signal<uint32_t> r_cleanup_pktid;
1130	sc_signal<bool> r_cleanup_coherent;
1131	sc_signal<data_t> *r_cleanup_data;
1132	sc_signal<data_t> *r_cleanup_old_data;
1133	sc_signal<bool> r_cleanup_contains_data;
1134
1135	sc_signal<bool> r_cleanup_ncc;
1136	sc_signal<bool> r_cleanup_to_ixr_cmd_ncc_l1_dirty;
1137	sc_signal<bool> r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
1138
1139	sc_signal<bool> r_cleanup_to_ixr_cmd_req;
1140	sc_signal<data_t> *r_cleanup_to_ixr_cmd_data;
1141	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_srcid;
1142	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_trdid;
1143	sc_signal<uint32_t> r_cleanup_to_ixr_cmd_pktid;
1144	sc_signal<addr_t> r_cleanup_to_ixr_cmd_nline;
1145	}; // end class VciMemCache
1146
1147	}}
1148
1149	#endif
1150
1151	// Local Variables:
1152	// tab-width: 2
1153	// c-basic-offset: 2
1154	// c-file-offsets:((innamespace . 0)(inline-open . 0))
1155	// indent-tabs-mode: nil
1156	// End:
1157
1158	// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2
1159

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