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source: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 846

Last change on this file since 846 was 846, checked in by cfuguet, 10 years ago
reconf: adding external access type to read/write WDT threshold
File size: 243.9 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include <signal.h>
32
33	#include "arithmetics.h"
34	#include "../include/vci_cc_vcache_wrapper.h"
35
36	#define DEBUG_DCACHE 1
37	#define DEBUG_ICACHE 1
38	#define DEBUG_CMD 0
39
40	namespace soclib {
41	namespace caba {
42
43	namespace {
44	const char * icache_fsm_state_str[] = {
45	"ICACHE_IDLE",
46
47	"ICACHE_XTN_TLB_FLUSH",
48	"ICACHE_XTN_CACHE_FLUSH",
49	"ICACHE_XTN_CACHE_FLUSH_GO",
50	"ICACHE_XTN_TLB_INVAL",
51	"ICACHE_XTN_CACHE_INVAL_VA",
52	"ICACHE_XTN_CACHE_INVAL_PA",
53	"ICACHE_XTN_CACHE_INVAL_GO",
54
55	"ICACHE_TLB_WAIT",
56
57	"ICACHE_MISS_SELECT",
58	"ICACHE_MISS_CLEAN",
59	"ICACHE_MISS_WAIT",
60	"ICACHE_MISS_DATA_UPDT",
61	"ICACHE_MISS_DIR_UPDT",
62
63	"ICACHE_UNC_WAIT",
64
65	"ICACHE_CC_CHECK",
66	"ICACHE_CC_UPDT",
67	"ICACHE_CC_INVAL",
68	};
69
70	const char * dcache_fsm_state_str[] = {
71	"DCACHE_IDLE",
72
73	"DCACHE_TLB_MISS",
74	"DCACHE_TLB_PTE1_GET",
75	"DCACHE_TLB_PTE1_SELECT",
76	"DCACHE_TLB_PTE1_UPDT",
77	"DCACHE_TLB_PTE2_GET",
78	"DCACHE_TLB_PTE2_SELECT",
79	"DCACHE_TLB_PTE2_UPDT",
80	"DCACHE_TLB_LR_UPDT",
81	"DCACHE_TLB_LR_WAIT",
82	"DCACHE_TLB_RETURN",
83
84	"DCACHE_XTN_SWITCH",
85	"DCACHE_XTN_SYNC",
86	"DCACHE_XTN_IC_INVAL_VA",
87	"DCACHE_XTN_IC_FLUSH",
88	"DCACHE_XTN_IC_INVAL_PA",
89	"DCACHE_XTN_IC_PADDR_EXT",
90	"DCACHE_XTN_IT_INVAL",
91	"DCACHE_XTN_DC_FLUSH",
92	"DCACHE_XTN_DC_FLUSH_GO",
93	"DCACHE_XTN_DC_INVAL_VA",
94	"DCACHE_XTN_DC_INVAL_PA",
95	"DCACHE_XTN_DC_INVAL_END",
96	"DCACHE_XTN_DC_INVAL_GO",
97	"DCACHE_XTN_DT_INVAL",
98
99	"DCACHE_DIRTY_GET_PTE",
100	"DCACHE_DIRTY_WAIT",
101
102	"DCACHE_MISS_SELECT",
103	"DCACHE_MISS_CLEAN",
104	"DCACHE_MISS_WAIT",
105	"DCACHE_MISS_DATA_UPDT",
106	"DCACHE_MISS_DIR_UPDT",
107
108	"DCACHE_UNC_WAIT",
109	"DCACHE_LL_WAIT",
110	"DCACHE_SC_WAIT",
111
112	"DCACHE_CC_CHECK",
113	"DCACHE_CC_UPDT",
114	"DCACHE_CC_INVAL",
115
116	"DCACHE_INVAL_TLB_SCAN",
117	};
118
119	const char * cmd_fsm_state_str[] = {
120	"CMD_IDLE",
121	"CMD_INS_MISS",
122	"CMD_INS_UNC",
123	"CMD_DATA_MISS",
124	"CMD_DATA_UNC_READ",
125	"CMD_DATA_UNC_WRITE",
126	"CMD_DATA_WRITE",
127	"CMD_DATA_LL",
128	"CMD_DATA_SC",
129	"CMD_DATA_CAS",
130	};
131
132	const char * vci_pktid_type_str[] = {
133	"TYPE_DATA_UNC",
134	"TYPE_READ_DATA_MISS",
135	"TYPE_READ_INS_UNC",
136	"TYPE_READ_INS_MISS",
137	"TYPE_WRITE",
138	"TYPE_CAS",
139	"TYPE_LL",
140	"TYPE_SC",
141	};
142
143	const char * vci_cmd_type_str[] = {
144	"NOP or STORE_COND",
145	"READ",
146	"WRITE",
147	"LOCKED_READ"
148	};
149
150	const char * rsp_fsm_state_str[] = {
151	"RSP_IDLE",
152	"RSP_INS_MISS",
153	"RSP_INS_UNC",
154	"RSP_DATA_MISS",
155	"RSP_DATA_UNC",
156	"RSP_DATA_LL",
157	"RSP_DATA_WRITE",
158	};
159
160	const char * cc_receive_fsm_state_str[] = {
161	"CC_RECEIVE_IDLE",
162	"CC_RECEIVE_BRDCAST_HEADER",
163	"CC_RECEIVE_BRDCAST_NLINE",
164	"CC_RECEIVE_INS_INVAL_HEADER",
165	"CC_RECEIVE_INS_INVAL_NLINE",
166	"CC_RECEIVE_INS_UPDT_HEADER",
167	"CC_RECEIVE_INS_UPDT_NLINE",
168	"CC_RECEIVE_INS_UPDT_DATA",
169	"CC_RECEIVE_DATA_INVAL_HEADER",
170	"CC_RECEIVE_DATA_INVAL_NLINE",
171	"CC_RECEIVE_DATA_UPDT_HEADER",
172	"CC_RECEIVE_DATA_UPDT_NLINE",
173	"CC_RECEIVE_DATA_UPDT_DATA",
174	};
175
176	const char * cc_send_fsm_state_str[] = {
177	"CC_SEND_IDLE",
178	"CC_SEND_CLEANUP_1",
179	"CC_SEND_CLEANUP_2",
180	"CC_SEND_MULTI_ACK",
181	};
182	}
183
184	#define tmpl(...) \
185	template<typename vci_param, \
186	size_t dspin_in_width, \
187	size_t dspin_out_width, \
188	typename iss_t> __VA_ARGS__ \
189	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
190
191	using namespace soclib::common;
192
193	/////////////////////////////////
194	tmpl(/**/)::VciCcVCacheWrapper(
195	sc_module_name name,
196	const int proc_id,
197	const MappingTable &mtd,
198	const IntTab &srcid,
199	const size_t cc_global_id,
200	const size_t itlb_ways,
201	const size_t itlb_sets,
202	const size_t dtlb_ways,
203	const size_t dtlb_sets,
204	const size_t icache_ways,
205	const size_t icache_sets,
206	const size_t icache_words,
207	const size_t dcache_ways,
208	const size_t dcache_sets,
209	const size_t dcache_words,
210	const size_t wbuf_nlines,
211	const size_t wbuf_nwords,
212	const size_t x_width,
213	const size_t y_width,
214	const uint32_t max_frozen_cycles,
215	const uint32_t debug_start_cycle,
216	const bool debug_ok)
217	: soclib::caba::BaseModule(name),
218
219	p_clk("p_clk"),
220	p_resetn("p_resetn"),
221	p_vci("p_vci"),
222	p_dspin_m2p("p_dspin_m2p"),
223	p_dspin_p2m("p_dspin_p2m"),
224	p_dspin_clack("p_dspin_clack"),
225
226	m_cacheability_table( mtd.getCacheabilityTable()),
227	m_srcid(mtd.indexForId(srcid)),
228	m_cc_global_id(cc_global_id),
229	m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2),
230	m_itlb_ways(itlb_ways),
231	m_itlb_sets(itlb_sets),
232	m_dtlb_ways(dtlb_ways),
233	m_dtlb_sets(dtlb_sets),
234	m_icache_ways(icache_ways),
235	m_icache_sets(icache_sets),
236	m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)),
237	m_icache_words(icache_words),
238	m_dcache_ways(dcache_ways),
239	m_dcache_sets(dcache_sets),
240	m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)),
241	m_dcache_words(dcache_words),
242	m_x_width(x_width),
243	m_y_width(y_width),
244	m_proc_id(proc_id),
245	m_max_frozen_cycles(max_frozen_cycles),
246	m_paddr_nbits(vci_param::N),
247	m_debug_start_cycle(debug_start_cycle),
248	m_debug_ok(debug_ok),
249	m_dcache_paddr_ext_reset(0),
250	m_icache_paddr_ext_reset(0),
251
252	r_mmu_ptpr("r_mmu_ptpr"),
253	r_mmu_mode("r_mmu_mode"),
254	r_mmu_word_lo("r_mmu_word_lo"),
255	r_mmu_word_hi("r_mmu_word_hi"),
256	r_mmu_ibvar("r_mmu_ibvar"),
257	r_mmu_dbvar("r_mmu_dbvar"),
258	r_mmu_ietr("r_mmu_ietr"),
259	r_mmu_detr("r_mmu_detr"),
260
261	r_icache_fsm("r_icache_fsm"),
262	r_icache_fsm_save("r_icache_fsm_save"),
263	r_icache_vci_paddr("r_icache_vci_paddr"),
264	r_icache_vaddr_save("r_icache_vaddr_save"),
265
266	r_icache_miss_way("r_icache_miss_way"),
267	r_icache_miss_set("r_icache_miss_set"),
268	r_icache_miss_word("r_icache_miss_word"),
269	r_icache_miss_inval("r_icache_miss_inval"),
270	r_icache_miss_clack("r_icache_miss_clack"),
271
272	r_icache_cc_way("r_icache_cc_way"),
273	r_icache_cc_set("r_icache_cc_set"),
274	r_icache_cc_word("r_icache_cc_word"),
275	r_icache_cc_need_write("r_icache_cc_need_write"),
276
277	r_icache_flush_count("r_icache_flush_count"),
278
279	r_icache_miss_req("r_icache_miss_req"),
280	r_icache_unc_req("r_icache_unc_req"),
281
282	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
283	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
284
285	r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
286	r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
287
288	r_icache_cc_send_req("r_icache_cc_send_req"),
289	r_icache_cc_send_type("r_icache_cc_send_type"),
290	r_icache_cc_send_nline("r_icache_cc_send_nline"),
291	r_icache_cc_send_way("r_icache_cc_send_way"),
292	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
293
294	r_dcache_fsm("r_dcache_fsm"),
295	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
296	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
297
298	r_dcache_wbuf_req("r_dcache_wbuf_req"),
299	r_dcache_updt_req("r_dcache_updt_req"),
300	r_dcache_save_vaddr("r_dcache_save_vaddr"),
301	r_dcache_save_wdata("r_dcache_save_wdata"),
302	r_dcache_save_be("r_dcache_save_be"),
303	r_dcache_save_paddr("r_dcache_save_paddr"),
304	r_dcache_save_cache_way("r_dcache_save_cache_way"),
305	r_dcache_save_cache_set("r_dcache_save_cache_set"),
306	r_dcache_save_cache_word("r_dcache_save_cache_word"),
307
308	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
309	r_dcache_dirty_way("r_dcache_dirty_way"),
310	r_dcache_dirty_set("r_dcache_dirty_set"),
311
312	r_dcache_vci_paddr("r_dcache_vci_paddr"),
313	r_dcache_vci_wdata("r_dcache_vci_wdata"),
314	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
315	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
316	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
317	r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
318	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
319	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
320	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
321	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
322	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
323	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
324
325	r_dcache_xtn_way("r_dcache_xtn_way"),
326	r_dcache_xtn_set("r_dcache_xtn_set"),
327
328	r_dcache_miss_type("r_dcache_miss_type"),
329	r_dcache_miss_word("r_dcache_miss_word"),
330	r_dcache_miss_way("r_dcache_miss_way"),
331	r_dcache_miss_set("r_dcache_miss_set"),
332	r_dcache_miss_inval("r_dcache_miss_inval"),
333	r_dcache_miss_wdt_max("r_dcache_miss_wdt_max"),
334	r_dcache_miss_wdt("r_dcache_miss_wdt"),
335
336	r_dcache_cc_way("r_dcache_cc_way"),
337	r_dcache_cc_set("r_dcache_cc_set"),
338	r_dcache_cc_word("r_dcache_cc_word"),
339	r_dcache_cc_need_write("r_dcache_cc_need_write"),
340
341	r_dcache_flush_count("r_dcache_flush_count"),
342
343	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
344
345	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
346	r_dcache_tlb_ins("r_dcache_tlb_ins"),
347	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
348	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
349	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
350	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
351	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
352	r_dcache_tlb_way("r_dcache_tlb_way"),
353	r_dcache_tlb_set("r_dcache_tlb_set"),
354
355	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
356	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
357
358	r_dcache_xtn_req("r_dcache_xtn_req"),
359	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
360
361	r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
362	r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
363
364	r_dcache_cc_send_req("r_dcache_cc_send_req"),
365	r_dcache_cc_send_type("r_dcache_cc_send_type"),
366	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
367	r_dcache_cc_send_way("r_dcache_cc_send_way"),
368	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
369
370	r_vci_cmd_fsm("r_vci_cmd_fsm"),
371	r_vci_cmd_min("r_vci_cmd_min"),
372	r_vci_cmd_max("r_vci_cmd_max"),
373	r_vci_cmd_cpt("r_vci_cmd_cpt"),
374	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
375
376	r_vci_rsp_fsm("r_vci_rsp_fsm"),
377	r_vci_rsp_cpt("r_vci_rsp_cpt"),
378	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
379	r_vci_rsp_data_error("r_vci_rsp_data_error"),
380	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
381	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
382
383	r_cc_send_fsm("r_cc_send_fsm"),
384	r_cc_send_last_client("r_cc_send_last_client"),
385
386	r_cc_receive_fsm("r_cc_receive_fsm"),
387	r_cc_receive_data_ins("r_cc_receive_data_ins"),
388	r_cc_receive_word_idx("r_cc_receive_word_idx"),
389	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
390	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
391	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
392
393	r_cc_receive_icache_req("r_cc_receive_icache_req"),
394	r_cc_receive_icache_type("r_cc_receive_icache_type"),
395	r_cc_receive_icache_way("r_cc_receive_icache_way"),
396	r_cc_receive_icache_set("r_cc_receive_icache_set"),
397	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
398	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
399
400	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
401	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
402	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
403	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
404	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
405	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
406
407	r_iss(this->name(), proc_id),
408	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
409	r_icache("icache", icache_ways, icache_sets, icache_words),
410	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
411	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
412	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
413	{
414	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
415
416	assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and
417	"Need more PLEN bits.");
418
419	assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and
420	"Need more TRDID bits.");
421
422	assert((icache_words == dcache_words) and
423	"icache_words and dcache_words parameters must be equal");
424
425	assert((itlb_sets == dtlb_sets) and
426	"itlb_sets and dtlb_sets parameters must be etqual");
427
428	assert((itlb_ways == dtlb_ways) and
429	"itlb_ways and dtlb_ways parameters must be etqual");
430
431	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
432	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
433	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
434	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
435	(uint32_log2(m_icache_words << 2));
436
437	r_mmu_release = (uint32_t) (1 << 16) \| 0x1;
438
439	r_dcache_in_tlb = new bool[dcache_ways * dcache_sets];
440	r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets];
441
442	SC_METHOD(transition);
443	dont_initialize();
444	sensitive << p_clk.pos();
445
446	SC_METHOD(genMoore);
447	dont_initialize();
448	sensitive << p_clk.neg();
449
450	typename iss_t::CacheInfo cache_info;
451	cache_info.has_mmu = true;
452	cache_info.icache_line_size = icache_words * sizeof(uint32_t);
453	cache_info.icache_assoc = icache_ways;
454	cache_info.icache_n_lines = icache_sets;
455	cache_info.dcache_line_size = dcache_words * sizeof(uint32_t);
456	cache_info.dcache_assoc = dcache_ways;
457	cache_info.dcache_n_lines = dcache_sets;
458	r_iss.setCacheInfo(cache_info);
459	}
460
461	/////////////////////////////////////
462	tmpl(/**/)::~VciCcVCacheWrapper()
463	/////////////////////////////////////
464	{
465	delete [] r_dcache_in_tlb;
466	delete [] r_dcache_contains_ptd;
467	}
468
469	////////////////////////
470	tmpl(void)::print_cpi()
471	////////////////////////
472	{
473	std::cout << name() << " CPI = "
474	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
475	}
476
477	////////////////////////////////////
478	tmpl(void)::print_trace(size_t mode)
479	////////////////////////////////////
480	{
481	// b0 : write buffer trace
482	// b1 : dump processor registers
483	// b2 : dcache trace
484	// b3 : icache trace
485	// b4 : dtlb trace
486	// b5 : itlb trace
487	// b6 : SR (ISS register 32)
488
489	std::cout << std::dec << "PROC " << name() << std::endl;
490
491	std::cout << " " << m_ireq << std::endl;
492	std::cout << " " << m_irsp << std::endl;
493	std::cout << " " << m_dreq << std::endl;
494	std::cout << " " << m_drsp << std::endl;
495
496	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
497	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
498	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
499	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
500	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
501	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
502	<< " \| MMU = " << r_mmu_mode.read();
503
504	if (r_dcache_updt_req.read()) std::cout << " \| P1_UPDT";
505	if (r_dcache_wbuf_req.read()) std::cout << " \| P1_WBUF";
506	std::cout << std::endl;
507
508	if (mode & 0x01)
509	{
510	if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl;
511	if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl;
512	if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl;
513	if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl;
514
515	r_wbuf.printTrace((mode >> 1) & 1);
516	}
517	if (mode & 0x02)
518	{
519	r_iss.dump();
520	}
521	if (mode & 0x04)
522	{
523	std::cout << " Data Cache" << std::endl;
524	r_dcache.printTrace();
525	}
526	if (mode & 0x08)
527	{
528	std::cout << " Instruction Cache" << std::endl;
529	r_icache.printTrace();
530	}
531	if (mode & 0x10)
532	{
533	std::cout << " Data TLB" << std::endl;
534	r_dtlb.printTrace();
535	}
536	if (mode & 0x20)
537	{
538	std::cout << " Instruction TLB" << std::endl;
539	r_itlb.printTrace();
540	}
541	if (mode & 0x40)
542	{
543	uint32_t status = r_iss.debugGetRegisterValue(32);
544	std::cout << name();
545	if (status != m_previous_status ) std::cout << " NEW ";
546	std::cout << " status = " << std::hex << status << " " << std::endl;
547	m_previous_status = status;
548	}
549	}
550
551	//////////////////////////////////////////
552	tmpl(void)::cache_monitor(paddr_t addr)
553	//////////////////////////////////////////
554	{
555	bool cache_hit;
556	size_t cache_way = 0;
557	size_t cache_set = 0;
558	size_t cache_word = 0;
559	uint32_t cache_rdata = 0;
560
561	cache_hit = r_dcache.read_neutral(addr,
562	&cache_rdata,
563	&cache_way,
564	&cache_set,
565	&cache_word);
566
567	if (cache_hit != m_debug_previous_d_hit)
568	{
569	std::cout << "Monitor PROC " << name()
570	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
571	<< " / HIT = " << cache_hit
572	<< " / PADDR = " << std::hex << addr
573	<< " / DATA = " << cache_rdata
574	<< " / WAY = " << cache_way << std::endl;
575	m_debug_previous_d_hit = cache_hit;
576	}
577
578	cache_hit = r_icache.read_neutral(addr,
579	&cache_rdata,
580	&cache_way,
581	&cache_set,
582	&cache_word);
583
584	if (cache_hit != m_debug_previous_i_hit)
585	{
586	std::cout << "Monitor PROC " << name()
587	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
588	<< " / HIT = " << cache_hit
589	<< " / PADDR = " << std::hex << addr
590	<< " / DATA = " << cache_rdata
591	<< " / WAY = " << cache_way << std::endl;
592	m_debug_previous_i_hit = cache_hit;
593	}
594	}
595
596	/*
597	////////////////////////
598	tmpl(void)::print_stats()
599	////////////////////////
600	{
601	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
602	std::cout << name() << std::endl
603	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
604	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
605	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
606	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
607	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
608	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
609	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
610	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
611	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
612	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
613	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
614	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
615	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
616	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
617	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
618	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
619	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
620	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
621	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
622	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
623	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
624	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
625	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
626	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
627	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
628	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
629	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
630	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
631	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
632	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
633	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
634	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
635	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
636	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
637	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
638	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
639	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
640	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
641	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
642	}
643
644	////////////////////////
645	tmpl(void)::clear_stats()
646	////////////////////////
647	{
648	m_cpt_dcache_data_read = 0;
649	m_cpt_dcache_data_write = 0;
650	m_cpt_dcache_dir_read = 0;
651	m_cpt_dcache_dir_write = 0;
652	m_cpt_icache_data_read = 0;
653	m_cpt_icache_data_write = 0;
654	m_cpt_icache_dir_read = 0;
655	m_cpt_icache_dir_write = 0;
656
657	m_cpt_frz_cycles = 0;
658	m_cpt_dcache_frz_cycles = 0;
659	m_cpt_total_cycles = 0;
660
661	m_cpt_read = 0;
662	m_cpt_write = 0;
663	m_cpt_data_miss = 0;
664	m_cpt_ins_miss = 0;
665	m_cpt_unc_read = 0;
666	m_cpt_write_cached = 0;
667	m_cpt_ins_read = 0;
668
669	m_cost_write_frz = 0;
670	m_cost_data_miss_frz = 0;
671	m_cost_unc_read_frz = 0;
672	m_cost_ins_miss_frz = 0;
673
674	m_cpt_imiss_transaction = 0;
675	m_cpt_dmiss_transaction = 0;
676	m_cpt_unc_transaction = 0;
677	m_cpt_write_transaction = 0;
678	m_cpt_icache_unc_transaction = 0;
679
680	m_cost_imiss_transaction = 0;
681	m_cost_dmiss_transaction = 0;
682	m_cost_unc_transaction = 0;
683	m_cost_write_transaction = 0;
684	m_cost_icache_unc_transaction = 0;
685	m_length_write_transaction = 0;
686
687	m_cpt_ins_tlb_read = 0;
688	m_cpt_ins_tlb_miss = 0;
689	m_cpt_ins_tlb_update_acc = 0;
690
691	m_cpt_data_tlb_read = 0;
692	m_cpt_data_tlb_miss = 0;
693	m_cpt_data_tlb_update_acc = 0;
694	m_cpt_data_tlb_update_dirty = 0;
695	m_cpt_ins_tlb_hit_dcache = 0;
696	m_cpt_data_tlb_hit_dcache = 0;
697	m_cpt_ins_tlb_occup_cache = 0;
698	m_cpt_data_tlb_occup_cache = 0;
699
700	m_cost_ins_tlb_miss_frz = 0;
701	m_cost_data_tlb_miss_frz = 0;
702	m_cost_ins_tlb_update_acc_frz = 0;
703	m_cost_data_tlb_update_acc_frz = 0;
704	m_cost_data_tlb_update_dirty_frz = 0;
705	m_cost_ins_tlb_occup_cache_frz = 0;
706	m_cost_data_tlb_occup_cache_frz = 0;
707
708	m_cpt_itlbmiss_transaction = 0;
709	m_cpt_itlb_ll_transaction = 0;
710	m_cpt_itlb_sc_transaction = 0;
711	m_cpt_dtlbmiss_transaction = 0;
712	m_cpt_dtlb_ll_transaction = 0;
713	m_cpt_dtlb_sc_transaction = 0;
714	m_cpt_dtlb_ll_dirty_transaction = 0;
715	m_cpt_dtlb_sc_dirty_transaction = 0;
716
717	m_cost_itlbmiss_transaction = 0;
718	m_cost_itlb_ll_transaction = 0;
719	m_cost_itlb_sc_transaction = 0;
720	m_cost_dtlbmiss_transaction = 0;
721	m_cost_dtlb_ll_transaction = 0;
722	m_cost_dtlb_sc_transaction = 0;
723	m_cost_dtlb_ll_dirty_transaction = 0;
724	m_cost_dtlb_sc_dirty_transaction = 0;
725
726	m_cpt_cc_update_data = 0;
727	m_cpt_cc_inval_ins = 0;
728	m_cpt_cc_inval_data = 0;
729	m_cpt_cc_broadcast = 0;
730
731	m_cost_updt_data_frz = 0;
732	m_cost_inval_ins_frz = 0;
733	m_cost_inval_data_frz = 0;
734	m_cost_broadcast_frz = 0;
735
736	m_cpt_cc_cleanup_data = 0;
737	m_cpt_cc_cleanup_ins = 0;
738	}
739
740	*/
741
742	/////////////////////////
743	tmpl(void)::transition()
744	/////////////////////////
745	{
746	if (not p_resetn.read())
747	{
748	r_iss.reset();
749	r_wbuf.reset();
750	r_icache.reset();
751	r_dcache.reset();
752	r_itlb.reset();
753	r_dtlb.reset();
754
755	r_dcache_fsm = DCACHE_IDLE;
756	r_icache_fsm = ICACHE_IDLE;
757	r_vci_cmd_fsm = CMD_IDLE;
758	r_vci_rsp_fsm = RSP_IDLE;
759	r_cc_receive_fsm = CC_RECEIVE_IDLE;
760	r_cc_send_fsm = CC_SEND_IDLE;
761
762	// reset data physical address extension
763	r_dcache_paddr_ext = m_dcache_paddr_ext_reset;
764
765	// reset inst physical address extension
766	r_icache_paddr_ext = m_icache_paddr_ext_reset;
767
768	// reset dcache directory extension
769	for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++)
770	{
771	r_dcache_in_tlb[i] = false;
772	r_dcache_contains_ptd[i] = false;
773	}
774
775	// Response FIFOs and cleanup buffer
776	r_vci_rsp_fifo_icache.init();
777	r_vci_rsp_fifo_dcache.init();
778
779	// ICACHE & DCACHE activated
780	// ITLB & DTLB desactivated
781	r_mmu_mode = 0x3;
782
783	// No request from ICACHE FSM to CMD FSM
784	r_icache_miss_req = false;
785	r_icache_unc_req = false;
786
787	// No request from ICACHE_FSM to DCACHE FSM
788	r_icache_tlb_miss_req = false;
789
790	// No request from ICACHE_FSM to CC_SEND FSM
791	r_icache_cc_send_req = false;
792	r_icache_cleanup_victim_req = false;
793
794	r_icache_clack_req = false;
795
796	// No pending write in pipeline
797	r_dcache_wbuf_req = false;
798	r_dcache_updt_req = false;
799
800	// No request from DCACHE_FSM to CMD_FSM
801	r_dcache_vci_miss_req = false;
802	r_dcache_vci_unc_req = false;
803	r_dcache_vci_cas_req = false;
804	r_dcache_vci_ll_req = false;
805	r_dcache_vci_sc_req = false;
806
807	// No processor XTN request pending
808	r_dcache_xtn_req = false;
809
810	// No request from DCACHE FSM to CC_SEND FSM
811	r_dcache_cc_send_req = false;
812	r_dcache_cleanup_victim_req = false;
813
814	r_dcache_clack_req = false;
815
816	// Reset watchdog timer threshold to max value
817	r_dcache_miss_wdt_max = UINT32_MAX;
818
819	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
820	r_cc_receive_icache_req = false;
821	r_cc_receive_dcache_req = false;
822
823	// last cc_send client was dcache
824	r_cc_send_last_client = false;
825
826	// No pending cleanup after a replacement
827	r_icache_miss_clack = false;
828	r_dcache_miss_clack = false;
829
830	// No signalisation of a coherence request matching a pending miss
831	r_icache_miss_inval = false;
832	r_dcache_miss_inval = false;
833
834	r_dspin_clack_req = false;
835
836	// No signalisation of errors
837	r_vci_rsp_ins_error = false;
838	r_vci_rsp_data_error = false;
839
840	// Debug variables
841	m_debug_previous_i_hit = false;
842	m_debug_previous_d_hit = false;
843	m_debug_icache_fsm = false;
844	m_debug_dcache_fsm = false;
845	m_debug_cmd_fsm = false;
846
847	// activity counters
848	m_cpt_dcache_data_read = 0;
849	m_cpt_dcache_data_write = 0;
850	m_cpt_dcache_dir_read = 0;
851	m_cpt_dcache_dir_write = 0;
852	m_cpt_icache_data_read = 0;
853	m_cpt_icache_data_write = 0;
854	m_cpt_icache_dir_read = 0;
855	m_cpt_icache_dir_write = 0;
856
857	m_cpt_frz_cycles = 0;
858	m_cpt_total_cycles = 0;
859	m_cpt_stop_simulation = 0;
860
861	m_cpt_data_miss = 0;
862	m_cpt_ins_miss = 0;
863	m_cpt_unc_read = 0;
864	m_cpt_write_cached = 0;
865	m_cpt_ins_read = 0;
866
867	m_cost_write_frz = 0;
868	m_cost_data_miss_frz = 0;
869	m_cost_unc_read_frz = 0;
870	m_cost_ins_miss_frz = 0;
871
872	m_cpt_imiss_transaction = 0;
873	m_cpt_dmiss_transaction = 0;
874	m_cpt_unc_transaction = 0;
875	m_cpt_write_transaction = 0;
876	m_cpt_icache_unc_transaction = 0;
877
878	m_cost_imiss_transaction = 0;
879	m_cost_dmiss_transaction = 0;
880	m_cost_unc_transaction = 0;
881	m_cost_write_transaction = 0;
882	m_cost_icache_unc_transaction = 0;
883	m_length_write_transaction = 0;
884
885	m_cpt_ins_tlb_read = 0;
886	m_cpt_ins_tlb_miss = 0;
887	m_cpt_ins_tlb_update_acc = 0;
888
889	m_cpt_data_tlb_read = 0;
890	m_cpt_data_tlb_miss = 0;
891	m_cpt_data_tlb_update_acc = 0;
892	m_cpt_data_tlb_update_dirty = 0;
893	m_cpt_ins_tlb_hit_dcache = 0;
894	m_cpt_data_tlb_hit_dcache = 0;
895	m_cpt_ins_tlb_occup_cache = 0;
896	m_cpt_data_tlb_occup_cache = 0;
897
898	m_cost_ins_tlb_miss_frz = 0;
899	m_cost_data_tlb_miss_frz = 0;
900	m_cost_ins_tlb_update_acc_frz = 0;
901	m_cost_data_tlb_update_acc_frz = 0;
902	m_cost_data_tlb_update_dirty_frz = 0;
903	m_cost_ins_tlb_occup_cache_frz = 0;
904	m_cost_data_tlb_occup_cache_frz = 0;
905
906	m_cpt_ins_tlb_inval = 0;
907	m_cpt_data_tlb_inval = 0;
908	m_cost_ins_tlb_inval_frz = 0;
909	m_cost_data_tlb_inval_frz = 0;
910
911	m_cpt_cc_broadcast = 0;
912
913	m_cost_updt_data_frz = 0;
914	m_cost_inval_ins_frz = 0;
915	m_cost_inval_data_frz = 0;
916	m_cost_broadcast_frz = 0;
917
918	m_cpt_cc_cleanup_data = 0;
919	m_cpt_cc_cleanup_ins = 0;
920
921	m_cpt_itlbmiss_transaction = 0;
922	m_cpt_itlb_ll_transaction = 0;
923	m_cpt_itlb_sc_transaction = 0;
924	m_cpt_dtlbmiss_transaction = 0;
925	m_cpt_dtlb_ll_transaction = 0;
926	m_cpt_dtlb_sc_transaction = 0;
927	m_cpt_dtlb_ll_dirty_transaction = 0;
928	m_cpt_dtlb_sc_dirty_transaction = 0;
929
930	m_cost_itlbmiss_transaction = 0;
931	m_cost_itlb_ll_transaction = 0;
932	m_cost_itlb_sc_transaction = 0;
933	m_cost_dtlbmiss_transaction = 0;
934	m_cost_dtlb_ll_transaction = 0;
935	m_cost_dtlb_sc_transaction = 0;
936	m_cost_dtlb_ll_dirty_transaction = 0;
937	m_cost_dtlb_sc_dirty_transaction = 0;
938	/*
939	m_cpt_dcache_frz_cycles = 0;
940	m_cpt_read = 0;
941	m_cpt_write = 0;
942	m_cpt_cc_update_data = 0;
943	m_cpt_cc_inval_ins = 0;
944	m_cpt_cc_inval_data = 0;
945	*/
946
947	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0;
948	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0;
949	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0;
950	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
951
952	// init the llsc reservation buffer
953	r_dcache_llsc_valid = false;
954	m_monitor_ok = false;
955
956	return;
957	}
958
959	// Response FIFOs default values
960	bool vci_rsp_fifo_icache_get = false;
961	bool vci_rsp_fifo_icache_put = false;
962	uint32_t vci_rsp_fifo_icache_data = 0;
963
964	bool vci_rsp_fifo_dcache_get = false;
965	bool vci_rsp_fifo_dcache_put = false;
966	uint32_t vci_rsp_fifo_dcache_data = 0;
967
968	// updt fifo
969	bool cc_receive_updt_fifo_get = false;
970	bool cc_receive_updt_fifo_put = false;
971	uint32_t cc_receive_updt_fifo_be = 0;
972	uint32_t cc_receive_updt_fifo_data = 0;
973	bool cc_receive_updt_fifo_eop = false;
974
975	#ifdef INSTRUMENTATION
976	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
977	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
978	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
979	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
980	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
981	m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()] ++;
982	#endif
983
984	m_cpt_total_cycles++;
985
986	m_debug_icache_fsm = m_debug_icache_fsm \|\|
987	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
988	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
989	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
990	m_debug_cmd_fsm = m_debug_cmd_fsm \|\|
991	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
992
993	/////////////////////////////////////////////////////////////////////
994	// Get data and instruction requests from processor
995	///////////////////////////////////////////////////////////////////////
996
997	r_iss.getRequests(m_ireq, m_dreq);
998
999	////////////////////////////////////////////////////////////////////////////////////
1000	// ICACHE_FSM
1001	//
1002	// 1/ Coherence operations
1003	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1004	// - There is a coherence request when r_tgt_icache_req is set.
1005	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
1006	// - There is a cleanup ack request when r_cleanup_icache_req is set.
1007	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
1008	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
1009	// - For both types of requests, actions associated to the pre-empted state
1010	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1011	// or CC_CLACK) to execute the requested coherence operation, and returns
1012	// to the pre-empted state.
1013	//
1014	// 2/ Processor requests
1015	// They are taken in IDLE state only. In case of cache miss, or uncacheable
1016	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
1017	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
1018	// flip-flops are reset when the transaction starts.
1019	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
1020	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
1021	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
1022	// The availability of the missing cache line is signaled by the response fifo,
1023	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
1024	// and ICACHE_MISS_DIR_UPDT states.
1025	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
1026	// to wait the response from the RSP FSM, through the response fifo.
1027	// The missing instruction is directly returned to processor in this state.
1028	//
1029	// 3/ TLB miss
1030	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
1031	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
1032	// register, and goes to the ICACHE_TLB_WAIT state.
1033	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
1034	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
1035	// to signal the completion.
1036	//
1037	// 4/ XTN requests
1038	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1039	// using the r_dcache_xtn_req flip-flop.
1040	// The request opcode and the address to be invalidated are transmitted
1041	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
1042	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1043	// is completed.
1044	//
1045	// 5/ Error Handling
1046	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1047	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1048	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1049	////////////////////////////////////////////////////////////////////////////////////////
1050
1051	// default value for m_irsp
1052	m_irsp.valid = false;
1053	m_irsp.error = false;
1054	m_irsp.instruction = 0;
1055
1056	switch (r_icache_fsm.read())
1057	{
1058	/////////////////
1059	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
1060	// and coherence requests with a fixed priority:
1061	// 1/ Coherence requests => ICACHE_CC_CHECK
1062	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
1063	// 3/ tlb miss => ICACHE_TLB_WAIT
1064	// 4/ cacheable read miss => ICACHE_MISS_SELECT
1065	// 5/ uncacheable read miss => ICACHE_UNC_REQ
1066	{
1067	// coherence clack interrupt
1068	if (r_icache_clack_req.read())
1069	{
1070	r_icache_fsm = ICACHE_CC_CHECK;
1071	r_icache_fsm_save = r_icache_fsm.read();
1072	break;
1073	}
1074
1075	// coherence interrupt
1076	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1077	{
1078	r_icache_fsm = ICACHE_CC_CHECK;
1079	r_icache_fsm_save = r_icache_fsm.read();
1080	break;
1081	}
1082
1083	// XTN requests sent by DCACHE FSM
1084	// These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT),
1085	// because they require access to icache or itlb, that are already accessed
1086	if (r_dcache_xtn_req.read())
1087	{
1088	if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR )
1089	{
1090	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1091	}
1092	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH)
1093	{
1094	r_icache_flush_count = 0;
1095	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1096	}
1097	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL)
1098	{
1099	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1100	}
1101	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL)
1102	{
1103	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1104	}
1105	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
1106	{
1107	if (sizeof(paddr_t) <= 32)
1108	{
1109	assert(r_mmu_word_hi.read() == 0 &&
1110	"illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
1111	r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read();
1112	}
1113	else
1114	{
1115	r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 \|
1116	(paddr_t) r_mmu_word_lo.read();
1117	}
1118	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1119	}
1120	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT)
1121	{
1122	r_icache_paddr_ext = r_dcache_save_wdata.read();
1123	r_dcache_xtn_req = false;
1124	}
1125	else
1126	{
1127	assert(false and
1128	"undefined XTN request received by ICACHE FSM");
1129	}
1130	break;
1131	} // end if xtn_req
1132
1133	// processor request
1134	if (m_ireq.valid )
1135	{
1136	bool cacheable;
1137	paddr_t paddr;
1138	bool tlb_hit = false;
1139	pte_info_t tlb_flags;
1140	size_t tlb_way;
1141	size_t tlb_set;
1142	paddr_t tlb_nline;
1143	uint32_t cache_inst = 0;
1144	size_t cache_way;
1145	size_t cache_set;
1146	size_t cache_word;
1147	int cache_state = CACHE_SLOT_STATE_EMPTY;
1148
1149	// We register processor request
1150	r_icache_vaddr_save = m_ireq.addr;
1151	paddr = (paddr_t) m_ireq.addr;
1152
1153	// sytematic itlb access (if activated)
1154	if (r_mmu_mode.read() & INS_TLB_MASK)
1155	{
1156
1157	#ifdef INSTRUMENTATION
1158	m_cpt_itlb_read++;
1159	#endif
1160	tlb_hit = r_itlb.translate(m_ireq.addr,
1161	&paddr,
1162	&tlb_flags,
1163	&tlb_nline, // unused
1164	&tlb_way, // unused
1165	&tlb_set); // unused
1166	}
1167	else if (vci_param::N > 32)
1168	{
1169	paddr = paddr \| ((paddr_t) r_icache_paddr_ext.read() << 32);
1170	}
1171
1172	// systematic icache access (if activated)
1173	if (r_mmu_mode.read() & INS_CACHE_MASK)
1174	{
1175
1176
1177	#ifdef INSTRUMENTATION
1178	m_cpt_icache_data_read++;
1179	m_cpt_icache_dir_read++;
1180	#endif
1181	r_icache.read(paddr,
1182	&cache_inst,
1183	&cache_way,
1184	&cache_set,
1185	&cache_word,
1186	&cache_state);
1187	}
1188
1189	// We compute cacheability and check access rights:
1190	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1191	// and the access rights are defined by the U and X bits in the PTE.
1192	// - If MMU not activated : cacheability is defined by the segment table,
1193	// and there is no access rights checking
1194
1195	if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated:
1196	{
1197	// cacheability
1198	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1199	else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr];
1200	}
1201	else // itlb activated
1202	{
1203	if (tlb_hit) // ITLB hit
1204	{
1205	// cacheability
1206	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1207	else cacheable = tlb_flags.c;
1208
1209	// access rights checking
1210	if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
1211	{
1212
1213	#if DEBUG_ICACHE
1214	if ( m_debug_icache_fsm )
1215	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation"
1216	<< " : PADDR = " << std::hex << paddr << std::endl;
1217	#endif
1218	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1219	r_mmu_ibvar = m_ireq.addr;
1220	m_irsp.valid = true;
1221	m_irsp.error = true;
1222	m_irsp.instruction = 0;
1223	break;
1224	}
1225	else if (not tlb_flags.x)
1226	{
1227
1228	#if DEBUG_ICACHE
1229	if ( m_debug_icache_fsm )
1230	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation"
1231	<< " : PADDR = " << std::hex << paddr << std::endl;
1232	#endif
1233	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1234	r_mmu_ibvar = m_ireq.addr;
1235	m_irsp.valid = true;
1236	m_irsp.error = true;
1237	m_irsp.instruction = 0;
1238	break;
1239	}
1240	}
1241	else // ITLB miss
1242	{
1243
1244	#ifdef INSTRUMENTATION
1245	m_cpt_itlb_miss++;
1246	#endif
1247	r_icache_fsm = ICACHE_TLB_WAIT;
1248	r_icache_tlb_miss_req = true;
1249	break;
1250	}
1251	} // end if itlb activated
1252
1253	// physical address registration
1254	r_icache_vci_paddr = paddr;
1255
1256	// Finally, we send the response to processor, and compute next state
1257	if (cacheable)
1258	{
1259	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1260	{
1261
1262	#ifdef INSTRUMENTATION
1263	m_cpt_icache_miss++;
1264	#endif
1265	// we request a VCI transaction
1266	r_icache_fsm = ICACHE_MISS_SELECT;
1267	#if DEBUG_ICACHE
1268	if (m_debug_icache_fsm)
1269	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1270	<< " : PADDR = " << std::hex << paddr << std::endl;
1271	#endif
1272	r_icache_miss_req = true;
1273	}
1274	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1275	{
1276	// stalled until cleanup is acknowledged
1277	r_icache_fsm = ICACHE_IDLE;
1278	}
1279	else // cache hit
1280	{
1281
1282	#ifdef INSTRUMENTATION
1283	m_cpt_ins_read++;
1284	#endif
1285	// return instruction to processor
1286	m_irsp.valid = true;
1287	m_irsp.instruction = cache_inst;
1288	r_icache_fsm = ICACHE_IDLE;
1289	#if DEBUG_ICACHE
1290	if (m_debug_icache_fsm)
1291	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1292	<< " : PADDR = " << std::hex << paddr
1293	<< " / INST = " << cache_inst << std::endl;
1294	#endif
1295	}
1296	}
1297	else // non cacheable read
1298	{
1299	r_icache_unc_req = true;
1300	r_icache_fsm = ICACHE_UNC_WAIT;
1301
1302	#if DEBUG_ICACHE
1303	if (m_debug_icache_fsm)
1304	{
1305	std::cout << " <PROC " << name()
1306	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1307	<< " : PADDR = " << std::hex << paddr << std::endl;
1308	}
1309	#endif
1310	}
1311	} // end if m_ireq.valid
1312	break;
1313	}
1314	/////////////////////
1315	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1316	// the itlb is udated by the DCACHE FSM, as well as the
1317	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1318	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1319	// reset the r_icache_tlb_miss_req flip-flop
1320	// external coherence request are accepted in this state.
1321	{
1322	// coherence clack interrupt
1323	if (r_icache_clack_req.read())
1324	{
1325	r_icache_fsm = ICACHE_CC_CHECK;
1326	r_icache_fsm_save = r_icache_fsm.read();
1327	break;
1328	}
1329
1330	// coherence interrupt
1331	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1332	{
1333	r_icache_fsm = ICACHE_CC_CHECK;
1334	r_icache_fsm_save = r_icache_fsm.read();
1335	break;
1336	}
1337
1338	if (m_ireq.valid) m_cost_ins_tlb_miss_frz++;
1339
1340	// DCACHE FSM signals response by reseting the request flip-flop
1341	if (not r_icache_tlb_miss_req.read())
1342	{
1343	if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated
1344	{
1345	r_icache_tlb_rsp_error = false;
1346	m_irsp.error = true;
1347	m_irsp.valid = true;
1348	r_icache_fsm = ICACHE_IDLE;
1349	}
1350	else // tlb updated : return to IDLE state
1351	{
1352	r_icache_fsm = ICACHE_IDLE;
1353	}
1354	}
1355	break;
1356	}
1357	//////////////////////////
1358	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1359	{
1360	r_itlb.flush();
1361	r_dcache_xtn_req = false;
1362	r_icache_fsm = ICACHE_IDLE;
1363	break;
1364	}
1365	////////////////////////////
1366	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1367	// r_icache_flush_count as a slot counter,
1368	// looping in this state until all slots are visited.
1369	// It can require two cycles per slot:
1370	// We test here the slot state, and make the actual inval
1371	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1372	// A cleanup request is generated for each valid line
1373	{
1374	// coherence clack interrupt
1375	if (r_icache_clack_req.read())
1376	{
1377	r_icache_fsm = ICACHE_CC_CHECK;
1378	r_icache_fsm_save = r_icache_fsm.read();
1379	break;
1380	}
1381
1382	// coherence request (from CC_RECEIVE FSM)
1383	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1384	{
1385	r_icache_fsm = ICACHE_CC_CHECK;
1386	r_icache_fsm_save = r_icache_fsm.read();
1387	break;
1388	}
1389
1390	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent
1391	{
1392	int state;
1393	paddr_t tag;
1394	size_t way = r_icache_flush_count.read() / m_icache_sets;
1395	size_t set = r_icache_flush_count.read() % m_icache_sets;
1396
1397	#ifdef INSTRUMENTATION
1398	m_cpt_icache_dir_read++;
1399	#endif
1400	r_icache.read_dir(way,
1401	set,
1402	&tag,
1403	&state);
1404
1405	if (state == CACHE_SLOT_STATE_VALID) // inval required
1406	{
1407	// request cleanup
1408	r_icache_cc_send_req = true;
1409	r_icache_cc_send_nline = tag * m_icache_sets + set;
1410	r_icache_cc_send_way = way;
1411	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1412
1413	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1414	r_icache_miss_way = way;
1415	r_icache_miss_set = set;
1416	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1417	}
1418	else if (r_icache_flush_count.read() ==
1419	(m_icache_sets*m_icache_ways - 1)) // last slot
1420	{
1421	r_dcache_xtn_req = false;
1422	m_drsp.valid = true;
1423	r_icache_fsm = ICACHE_IDLE;
1424	}
1425
1426	// saturation counter, to have the same last slot condition
1427	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1428	if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1))
1429	{
1430	r_icache_flush_count = r_icache_flush_count.read() + 1;
1431	}
1432	}
1433	break;
1434	}
1435	///////////////////////////////
1436	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1437	{
1438	size_t way = r_icache_miss_way.read();
1439	size_t set = r_icache_miss_set.read();
1440
1441	#ifdef INSTRUMENTATION
1442	m_cpt_icache_dir_write++;
1443	#endif
1444
1445	r_icache.write_dir(way,
1446	set,
1447	CACHE_SLOT_STATE_ZOMBI);
1448
1449	if (r_icache_flush_count.read() ==
1450	(m_icache_sets*m_icache_ways - 1)) // last slot
1451	{
1452	r_dcache_xtn_req = false;
1453	m_drsp.valid = true;
1454	r_icache_fsm = ICACHE_IDLE;
1455	}
1456	else
1457	{
1458	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1459	}
1460	break;
1461	}
1462
1463	//////////////////////////
1464	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1465	// stored in the r_dcache_save_wdata register
1466	{
1467	r_itlb.inval(r_dcache_save_wdata.read());
1468	r_dcache_xtn_req = false;
1469	r_icache_fsm = ICACHE_IDLE;
1470	break;
1471	}
1472	///////////////////////////////
1473	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1474	// requires 3 cycles (in case of hit on itlb and icache).
1475	// In this state, access TLB to translate virtual address
1476	// stored in the r_dcache_save_wdata register.
1477	{
1478	paddr_t paddr;
1479	bool hit;
1480
1481	// read physical address in TLB when MMU activated
1482	if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated
1483	{
1484
1485	#ifdef INSTRUMENTATION
1486	m_cpt_itlb_read++;
1487	#endif
1488	hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr);
1489	}
1490	else // itlb not activated
1491	{
1492	paddr = (paddr_t) r_dcache_save_wdata.read();
1493	hit = true;
1494	}
1495
1496	if (hit) // continue the selective inval process
1497	{
1498	r_icache_vci_paddr = paddr;
1499	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1500	}
1501	else // miss : send a request to DCACHE FSM
1502	{
1503
1504	#ifdef INSTRUMENTATION
1505	m_cpt_itlb_miss++;
1506	#endif
1507	r_icache_tlb_miss_req = true;
1508	r_icache_vaddr_save = r_dcache_save_wdata.read();
1509	r_icache_fsm = ICACHE_TLB_WAIT;
1510	}
1511	break;
1512	}
1513	///////////////////////////////
1514	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1515	// require 2 cycles. In this state, we read directory
1516	// with address stored in r_icache_vci_paddr register.
1517	{
1518	int state;
1519	size_t way;
1520	size_t set;
1521	size_t word;
1522
1523	#ifdef INSTRUMENTATION
1524	m_cpt_icache_dir_read++;
1525	#endif
1526	r_icache.read_dir(r_icache_vci_paddr.read(),
1527	&state,
1528	&way,
1529	&set,
1530	&word);
1531
1532	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
1533	{
1534	r_icache_miss_way = way;
1535	r_icache_miss_set = set;
1536	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1537	}
1538	else // miss : acknowlege the XTN request and return
1539	{
1540	r_dcache_xtn_req = false;
1541	r_icache_fsm = ICACHE_IDLE;
1542	}
1543	break;
1544	}
1545	///////////////////////////////
1546	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1547	{
1548	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request not sent
1549	{
1550
1551	#ifdef INSTRUMENTATION
1552	m_cpt_icache_dir_write++;
1553	#endif
1554	r_icache.write_dir(r_icache_miss_way.read(),
1555	r_icache_miss_set.read(),
1556	CACHE_SLOT_STATE_ZOMBI);
1557
1558	// request cleanup
1559	r_icache_cc_send_req = true;
1560	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1561	r_icache_cc_send_way = r_icache_miss_way.read();
1562	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1563
1564	// acknowledge the XTN request and return
1565	r_dcache_xtn_req = false;
1566	r_icache_fsm = ICACHE_IDLE;
1567	}
1568	break;
1569	}
1570	////////////////////////
1571	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1572	// Waiting in this state if no slot available.
1573	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
1574	// we send the cleanup request in this state.
1575	// If not, a r_icache_cleanup_victim_req flip-flop is
1576	// utilized for saving this cleanup request, and it will be sent later
1577	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
1578	// The r_icache_miss_clack flip-flop is set
1579	// when a cleanup is required
1580	{
1581	if (m_ireq.valid) m_cost_ins_miss_frz++;
1582
1583	// coherence clack interrupt
1584	if (r_icache_clack_req.read())
1585	{
1586	r_icache_fsm = ICACHE_CC_CHECK;
1587	r_icache_fsm_save = r_icache_fsm.read();
1588	break;
1589	}
1590
1591	// coherence interrupt
1592	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1593	{
1594	r_icache_fsm = ICACHE_CC_CHECK;
1595	r_icache_fsm_save = r_icache_fsm.read();
1596	break;
1597	}
1598
1599
1600	bool found;
1601	bool cleanup;
1602	size_t way;
1603	size_t set;
1604	paddr_t victim;
1605
1606	#ifdef INSTRUMENTATION
1607	m_cpt_icache_dir_read++;
1608	#endif
1609	r_icache.read_select(r_icache_vci_paddr.read(),
1610	&victim,
1611	&way,
1612	&set,
1613	&found,
1614	&cleanup);
1615	if (not found)
1616	{
1617	break;
1618	}
1619	else
1620	{
1621	r_icache_miss_way = way;
1622	r_icache_miss_set = set;
1623
1624	if (cleanup)
1625	{
1626	if (not r_icache_cc_send_req.read())
1627	{
1628	r_icache_cc_send_req = true;
1629	r_icache_cc_send_nline = victim;
1630	r_icache_cc_send_way = way;
1631	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1632	}
1633	else
1634	{
1635	r_icache_cleanup_victim_req = true;
1636	r_icache_cleanup_victim_nline = victim;
1637	}
1638
1639	r_icache_miss_clack = true;
1640	r_icache_fsm = ICACHE_MISS_CLEAN;
1641	}
1642	else
1643	{
1644	r_icache_fsm = ICACHE_MISS_WAIT;
1645	}
1646
1647	#if DEBUG_ICACHE
1648	if (m_debug_icache_fsm)
1649	{
1650	std::cout << " <PROC " << name()
1651	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1652	<< " / WAY = " << way
1653	<< " / SET = " << set;
1654	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1655	else std::cout << std::endl;
1656	}
1657	#endif
1658	}
1659	break;
1660	}
1661	///////////////////////
1662	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1663	{
1664	if (m_ireq.valid) m_cost_ins_miss_frz++;
1665
1666	#ifdef INSTRUMENTATION
1667	m_cpt_icache_dir_write++;
1668	#endif
1669	r_icache.write_dir(r_icache_miss_way.read(),
1670	r_icache_miss_set.read(),
1671	CACHE_SLOT_STATE_ZOMBI);
1672	#if DEBUG_ICACHE
1673	if (m_debug_icache_fsm)
1674	{
1675	std::cout << " <PROC " << name()
1676	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1677	<< " / WAY = " << r_icache_miss_way.read()
1678	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1679	}
1680	#endif
1681
1682	r_icache_fsm = ICACHE_MISS_WAIT;
1683	break;
1684	}
1685	//////////////////////
1686	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1687	{
1688	if (m_ireq.valid) m_cost_ins_miss_frz++;
1689
1690	// send cleanup victim request
1691	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1692	{
1693	r_icache_cc_send_req = true;
1694	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1695	r_icache_cc_send_way = r_icache_miss_way;
1696	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1697	r_icache_cleanup_victim_req = false;
1698	}
1699
1700	// coherence clack interrupt
1701	if (r_icache_clack_req.read())
1702	{
1703	r_icache_fsm = ICACHE_CC_CHECK;
1704	r_icache_fsm_save = r_icache_fsm.read();
1705	break;
1706	}
1707
1708	// coherence interrupt
1709	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1710	{
1711	r_icache_fsm = ICACHE_CC_CHECK;
1712	r_icache_fsm_save = r_icache_fsm.read();
1713	break;
1714	}
1715
1716	if (r_vci_rsp_ins_error.read()) // bus error
1717	{
1718	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1719	r_mmu_ibvar = r_icache_vaddr_save.read();
1720	m_irsp.valid = true;
1721	m_irsp.error = true;
1722	r_vci_rsp_ins_error = false;
1723	r_icache_fsm = ICACHE_IDLE;
1724	}
1725	else if (r_vci_rsp_fifo_icache.rok()) // response available
1726	{
1727	r_icache_miss_word = 0;
1728	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1729	}
1730	break;
1731	}
1732	///////////////////////////
1733	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1734	{
1735	if (m_ireq.valid) m_cost_ins_miss_frz++;
1736
1737	if (r_vci_rsp_fifo_icache.rok()) // response available
1738	{
1739
1740	#ifdef INSTRUMENTATION
1741	m_cpt_icache_data_write++;
1742	#endif
1743	r_icache.write(r_icache_miss_way.read(),
1744	r_icache_miss_set.read(),
1745	r_icache_miss_word.read(),
1746	r_vci_rsp_fifo_icache.read());
1747	#if DEBUG_ICACHE
1748	if (m_debug_icache_fsm)
1749	{
1750	std::cout << " <PROC " << name()
1751	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1752	<< " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
1753	<< " WAY = " << r_icache_miss_way.read()
1754	<< " SET = " << r_icache_miss_set.read()
1755	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1756	}
1757	#endif
1758	vci_rsp_fifo_icache_get = true;
1759	r_icache_miss_word = r_icache_miss_word.read() + 1;
1760
1761	if (r_icache_miss_word.read() == m_icache_words - 1) // last word
1762	{
1763	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1764	}
1765	}
1766	break;
1767	}
1768	//////////////////////////
1769	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1770	// and the cleanup ack has not been received,
1771	// as indicated by r_icache_miss_clack.
1772	// - If no matching coherence request (r_icache_miss_inval)
1773	// switch directory slot to VALID state.
1774	// - If matching coherence request, switch directory slot
1775	// to ZOMBI state, and send a cleanup request.
1776	{
1777	if (m_ireq.valid ) m_cost_ins_miss_frz++;
1778
1779	// send cleanup victim request
1780	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1781	{
1782	r_icache_cc_send_req = true;
1783	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1784	r_icache_cc_send_way = r_icache_miss_way;
1785	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1786	r_icache_cleanup_victim_req = false;
1787	}
1788
1789	// coherence clack interrupt
1790	if (r_icache_clack_req.read())
1791	{
1792	r_icache_fsm = ICACHE_CC_CHECK;
1793	r_icache_fsm_save = r_icache_fsm.read();
1794	break;
1795	}
1796
1797	// coherence interrupt
1798	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1799	{
1800	r_icache_fsm = ICACHE_CC_CHECK;
1801	r_icache_fsm_save = r_icache_fsm.read();
1802	break;
1803	}
1804
1805	if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line
1806	{
1807	if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup
1808	{
1809	if (not r_icache_cc_send_req.read())
1810	{
1811	r_icache_miss_inval = false;
1812	// request cleanup
1813	r_icache_cc_send_req = true;
1814	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1815	r_icache_cc_send_way = r_icache_miss_way.read();
1816	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1817
1818	#ifdef INSTRUMENTATION
1819	m_cpt_icache_dir_write++;
1820	#endif
1821	r_icache.write_dir(r_icache_vci_paddr.read(),
1822	r_icache_miss_way.read(),
1823	r_icache_miss_set.read(),
1824	CACHE_SLOT_STATE_ZOMBI);
1825	#if DEBUG_ICACHE
1826	if (m_debug_icache_fsm)
1827	{
1828	std::cout << " <PROC " << name()
1829	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1830	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1831	<< " WAY = " << std::dec << r_icache_miss_way.read()
1832	<< " SET = " << r_icache_miss_set.read() << std::endl;
1833	}
1834	#endif
1835	}
1836	else
1837	break;
1838	}
1839	else // Switch slot to VALID state
1840	{
1841
1842	#ifdef INSTRUMENTATION
1843	m_cpt_icache_dir_write++;
1844	#endif
1845	r_icache.write_dir(r_icache_vci_paddr.read(),
1846	r_icache_miss_way.read(),
1847	r_icache_miss_set.read(),
1848	CACHE_SLOT_STATE_VALID);
1849	#if DEBUG_ICACHE
1850	if (m_debug_icache_fsm)
1851	{
1852	std::cout << " <PROC " << name()
1853	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1854	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1855	<< " WAY = " << std::dec << r_icache_miss_way.read()
1856	<< " SET = " << r_icache_miss_set.read() << std::endl;
1857	}
1858	#endif
1859	}
1860
1861	r_icache_fsm = ICACHE_IDLE;
1862	}
1863	break;
1864	}
1865	////////////////////
1866	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1867	{
1868	// coherence clack interrupt
1869	if (r_icache_clack_req.read())
1870	{
1871	r_icache_fsm = ICACHE_CC_CHECK;
1872	r_icache_fsm_save = r_icache_fsm.read();
1873	break;
1874	}
1875
1876	// coherence interrupt
1877	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1878	{
1879	r_icache_fsm = ICACHE_CC_CHECK;
1880	r_icache_fsm_save = r_icache_fsm.read();
1881	break;
1882	}
1883
1884	if (r_vci_rsp_ins_error.read()) // bus error
1885	{
1886	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1887	r_mmu_ibvar = m_ireq.addr;
1888	r_vci_rsp_ins_error = false;
1889	m_irsp.valid = true;
1890	m_irsp.error = true;
1891	r_icache_fsm = ICACHE_IDLE;
1892	}
1893	else if (r_vci_rsp_fifo_icache.rok()) // instruction available
1894	{
1895	vci_rsp_fifo_icache_get = true;
1896	r_icache_fsm = ICACHE_IDLE;
1897	if (m_ireq.valid and
1898	(m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified
1899	{
1900	m_irsp.valid = true;
1901	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1902	}
1903	}
1904	break;
1905	}
1906	/////////////////////
1907	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1908	// handling coherence requests.
1909	// if there is a matching pending miss, it is
1910	// signaled in the r_icache_miss_inval flip-flop.
1911	// The return state is defined in r_icache_fsm_save.
1912	{
1913	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1914	paddr_t mask = ~((m_icache_words << 2) - 1);
1915
1916	// CLACK handler
1917	// We switch the directory slot to EMPTY state
1918	// and reset r_icache_miss_clack if the cleanup ack
1919	// is matching a pending miss.
1920	if (r_icache_clack_req.read())
1921	{
1922
1923	if (m_ireq.valid) m_cost_ins_miss_frz++;
1924
1925	#ifdef INSTRUMENTATION
1926	m_cpt_icache_dir_write++;
1927	#endif
1928	r_icache.write_dir(0,
1929	r_icache_clack_way.read(),
1930	r_icache_clack_set.read(),
1931	CACHE_SLOT_STATE_EMPTY);
1932
1933	if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and
1934	(r_icache_miss_way.read() == r_icache_clack_way.read()))
1935	{
1936	r_icache_miss_clack = false;
1937	}
1938
1939	r_icache_clack_req = false;
1940
1941	// return to cc_save state
1942	r_icache_fsm = r_icache_fsm_save.read();
1943
1944	#if DEBUG_ICACHE
1945	if (m_debug_icache_fsm)
1946	{
1947	std::cout << " <PROC " << name()
1948	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1949	<< " set = " << r_icache_clack_set.read()
1950	<< " / way = " << r_icache_clack_way.read() << std::endl;
1951	}
1952	#endif
1953
1954	break;
1955	}
1956
1957	assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
1958
1959	// Match between MISS address and CC address
1960	if (r_cc_receive_icache_req.read() and
1961	((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1962	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1963	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1964	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
1965	{
1966	// signaling the matching
1967	r_icache_miss_inval = true;
1968
1969	// in case of update, go to CC_UPDT
1970	// JUST TO POP THE FIFO
1971	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1972	{
1973	r_icache_fsm = ICACHE_CC_UPDT;
1974	r_icache_cc_word = r_cc_receive_word_idx.read();
1975
1976	// just pop the fifo , don't write in icache
1977	r_icache_cc_need_write = false;
1978	}
1979	// the request is dealt with
1980	else
1981	{
1982	r_cc_receive_icache_req = false;
1983	r_icache_fsm = r_icache_fsm_save.read();
1984	}
1985	#if DEBUG_ICACHE
1986	if (m_debug_icache_fsm)
1987	{
1988	std::cout << " <PROC " << name()
1989	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
1990	<< " PADDR = " << std::hex << paddr << std::endl;
1991	}
1992	#endif
1993	}
1994
1995	// CC request handler
1996
1997	int state = 0;
1998	size_t way = 0;
1999	size_t set = 0;
2000	size_t word = 0;
2001
2002	#ifdef INSTRUMENTATION
2003	m_cpt_icache_dir_read++;
2004	#endif
2005	r_icache.read_dir(paddr,
2006	&state,
2007	&way,
2008	&set,
2009	&word);
2010
2011	r_icache_cc_way = way;
2012	r_icache_cc_set = set;
2013
2014	if (state == CACHE_SLOT_STATE_VALID) // hit
2015	{
2016	// need to update the cache state
2017	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
2018	{
2019	r_icache_cc_need_write = true;
2020	r_icache_fsm = ICACHE_CC_UPDT;
2021	r_icache_cc_word = r_cc_receive_word_idx.read();
2022	}
2023	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
2024	{
2025	r_icache_fsm = ICACHE_CC_INVAL;
2026	}
2027	}
2028	else // miss
2029	{
2030	// multicast acknowledgement required in case of update
2031	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
2032	{
2033	r_icache_fsm = ICACHE_CC_UPDT;
2034	r_icache_cc_word = r_cc_receive_word_idx.read();
2035
2036	// just pop the fifo , don't write in icache
2037	r_icache_cc_need_write = false;
2038	}
2039	else // No response needed
2040	{
2041	r_cc_receive_icache_req = false;
2042	r_icache_fsm = r_icache_fsm_save.read();
2043	}
2044	}
2045	break;
2046	}
2047	/////////////////////
2048	case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state
2049	{
2050	assert (not r_icache_cc_send_req.read() &&
2051	"ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
2052	"must not be set");
2053
2054	#ifdef INSTRUMENTATION
2055	m_cpt_icache_dir_read++;
2056	#endif
2057
2058	// Switch slot state to ZOMBI and send CLEANUP command
2059	r_icache.write_dir(r_icache_cc_way.read(),
2060	r_icache_cc_set.read(),
2061	CACHE_SLOT_STATE_ZOMBI);
2062
2063	// coherence request completed
2064	r_icache_cc_send_req = true;
2065	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2066	r_icache_cc_send_way = r_icache_cc_way.read();
2067	r_icache_cc_send_type = CC_TYPE_CLEANUP;
2068
2069	r_icache_fsm = r_icache_fsm_save.read();
2070
2071	#if DEBUG_ICACHE
2072	if (m_debug_icache_fsm)
2073	{
2074	std::cout << " <PROC " << name()
2075	<< " ICACHE_CC_INVAL> slot returns to ZOMBI state"
2076	<< " set = " << r_icache_cc_set.read()
2077	<< " / way = " << r_icache_cc_way.read() << std::endl;
2078	}
2079	#endif
2080
2081	break;
2082	}
2083	////////////////////
2084	case ICACHE_CC_UPDT: // hit update : write one word per cycle
2085	{
2086	assert (not r_icache_cc_send_req.read() &&
2087	"ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
2088	"must not be set");
2089
2090	if (not r_cc_receive_updt_fifo_be.rok()) break;
2091
2092
2093	size_t word = r_icache_cc_word.read();
2094	size_t way = r_icache_cc_way.read();
2095	size_t set = r_icache_cc_set.read();
2096
2097	if (r_icache_cc_need_write.read())
2098	{
2099	r_icache.write(way,
2100	set,
2101	word,
2102	r_cc_receive_updt_fifo_data.read(),
2103	r_cc_receive_updt_fifo_be.read());
2104
2105	r_icache_cc_word = word + 1;
2106
2107	#ifdef INSTRUMENTATION
2108	m_cpt_icache_data_write++;
2109	#endif
2110
2111	#if DEBUG_ICACHE
2112	if (m_debug_icache_fsm)
2113	{
2114	std::cout << " <PROC " << name()
2115	<< " ICACHE_CC_UPDT> Write one word "
2116	<< " set = " << r_icache_cc_set.read()
2117	<< " / way = " << r_icache_cc_way.read()
2118	<< " / word = " << r_icache_cc_word.read() << std::endl;
2119	}
2120	#endif
2121	}
2122
2123	if (r_cc_receive_updt_fifo_eop.read()) // last word
2124	{
2125	// no need to write in the cache anymore
2126	r_icache_cc_need_write = false;
2127
2128	// coherence request completed
2129	r_cc_receive_icache_req = false;
2130
2131	// request multicast acknowledgement
2132	r_icache_cc_send_req = true;
2133	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2134	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
2135	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
2136
2137	r_icache_fsm = r_icache_fsm_save.read();
2138	}
2139	//consume fifo if not eop
2140	cc_receive_updt_fifo_get = true;
2141
2142	break;
2143	}
2144
2145	} // end switch r_icache_fsm
2146
2147	////////////////////////////////////////////////////////////////////////////////////
2148	// DCACHE FSM
2149	//
2150	// 1/ Coherence operations
2151	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2152	// - There is a coherence request when r_tgt_dcache_req is set.
2153	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2154	// and SC_WAIT states.
2155	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2156	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2157	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2158	// - For both types of requests, actions associated to the pre-empted state
2159	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2160	// or CC_CLACK) to execute the requested coherence operation, and returns
2161	// to the pre-empted state.
2162	//
2163	// 2/ TLB miss
2164	// The page tables are generally cacheable.
2165	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2166	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2167	// this sub-fsm implement the table-walk...
2168	//
2169	// 3/ processor requests
2170	// Processor requests are taken in IDLE state only.
2171	// The IDLE state implements a two stages pipe-line to handle write bursts:
2172	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2173	// - The registration in wbuf and the dcache update is done in stage P1
2174	// (if the processor request is a write).
2175	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2176	// the operations that must be done in P1 stage, and the access type
2177	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2178	// READ requests are delayed if a cache update is requested.
2179	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2180	// that is done (before handling the processor request) by a dedicated sub-fsm.
2181	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2182	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2183	//
2184	// 4/ Atomic instructions LL/SC
2185	// The LL/SC address are non cacheable (systematic access to memory).
2186	// The llsc buffer contains a registration for an active LL/SC operation
2187	// (with an address, a registration key, an aging counter and a valid bit).
2188	// - LL requests from the processor are transmitted as a one flit VCI command
2189	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2190	// be 8 as the response is 2 flits long (data and registration key)
2191	// - SC requests from the processor are systematically transmitted to the
2192	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2193	// as PKTID value). The first flit contains the registration key, the second
2194	// flit contains the data to write in case of success.
2195	// The cache is not updated, as this is done in case of success by the
2196	// coherence transaction.
2197	//
2198	// 5/ Non cacheable access:
2199	// This component implement a strong order between non cacheable access
2200	// (read or write) : A new non cacheable VCI transaction starts only when
2201	// the previous non cacheable transaction is completed. After send the VCI
2202	// transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
2203	// So the processor is blocked until the respone arrives in CACHE L1.
2204	//
2205	// 6/ Error handling:
2206	// When the MMU is not activated, Read Bus Errors are synchronous events,
2207	// Some Write Bus Errors are synchronous events when the request is a non cacheable access
2208	// but some Write Bus Errors are asynchronous events when the request is cacheable access
2209	// (processor is not frozen).
2210	// - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
2211	// r_vci_rsp_data_error flip-flop, without writing any data in the
2212	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2213	// by the DCACHE FSM.
2214	// - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
2215	// the asynchronous error using the setWriteBerr() method.
2216	// When the MMU is activated bus error are rare events, as the MMU
2217	// checks the physical address before the VCI transaction starts.
2218	////////////////////////////////////////////////////////////////////////////////////////
2219
2220	// default value for m_drsp
2221	m_drsp.valid = false;
2222	m_drsp.error = false;
2223	m_drsp.rdata = 0;
2224
2225	switch (r_dcache_fsm.read())
2226	{
2227	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2228	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2229	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2230	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2231	// 4) XTN request (processor) => DCACHE_XTN_*
2232	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2233	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2234	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2235	// 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT
2236	// 9) LL access (processor) => DCACHE_LL_WAIT
2237	// 10) SC access (processor) => DCACHE_SC_WAIT
2238	//
2239	// There is a fixed priority to handle requests to DCACHE:
2240	// 1/ the ITLB/DTLB invalidate requests
2241	// 2/ the coherence requests,
2242	// 3/ the processor requests (including DTLB miss),
2243	// 4/ the ITLB miss requests,
2244	// The address space processor request are handled as follows:
2245	// - WRITE request is blocked if the Dirty bit mus be set.
2246	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2247	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2248	// - READ request generate a simultaneouss access to DCACHE.DATA
2249	// and DCACHE.DIR, but is delayed if DCACHE update required.
2250	//
2251	// There is 4 configurations defining the access type to
2252	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2253	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2254	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2255	// 0 / 0 / NOP / NOP / NOP /
2256	// 0 / 1 / NOP / NOP / WRITE /
2257	// 1 / 0 / READ / READ / NOP /
2258	// 1 / 1 / READ / READ / WRITE /
2259	// Those two registers are set at each cycle from the 3 signals
2260	// updt_request, wbuf_request, wbuf_write_miss.
2261	{
2262	paddr_t paddr;
2263	pte_info_t tlb_flags;
2264	size_t tlb_way;
2265	size_t tlb_set;
2266	paddr_t tlb_nline = 0;
2267	size_t cache_way;
2268	size_t cache_set;
2269	size_t cache_word;
2270	uint32_t cache_rdata = 0;
2271	bool tlb_hit = false;
2272	int cache_state = CACHE_SLOT_STATE_EMPTY;
2273
2274	bool tlb_inval_required = false; // request TLB inval after cache update
2275	bool wbuf_write_miss = false; // miss a WBUF write request
2276	bool updt_request = false; // request DCACHE update in P1 stage
2277	bool wbuf_request = false; // request WBUF write in P1 stage
2278
2279	// physical address computation : systematic DTLB access if activated
2280	paddr = (paddr_t) m_dreq.addr;
2281	if (m_dreq.valid)
2282	{
2283	if (r_mmu_mode.read() & DATA_TLB_MASK) // DTLB activated
2284	{
2285	tlb_hit = r_dtlb.translate(m_dreq.addr,
2286	&paddr,
2287	&tlb_flags,
2288	&tlb_nline,
2289	&tlb_way,
2290	&tlb_set);
2291	#ifdef INSTRUMENTATION
2292	m_cpt_dtlb_read++;
2293	#endif
2294	}
2295	else // identity mapping
2296	{
2297	// we take into account the paddr extension
2298	if (vci_param::N > 32)
2299	paddr = paddr \| ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
2300	}
2301	} // end physical address computation
2302
2303	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2304	if (r_mmu_mode.read() & DATA_CACHE_MASK)
2305	{
2306
2307	if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA
2308	{
2309	r_dcache.read_dir(paddr,
2310	&cache_state,
2311	&cache_way,
2312	&cache_set,
2313	&cache_word);
2314
2315	r_dcache.write(r_dcache_save_cache_way.read(),
2316	r_dcache_save_cache_set.read(),
2317	r_dcache_save_cache_word.read(),
2318	r_dcache_save_wdata.read(),
2319	r_dcache_save_be.read());
2320	#ifdef INSTRUMENTATION
2321	m_cpt_dcache_dir_read++;
2322	m_cpt_dcache_data_write++;
2323	#endif
2324	}
2325	else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA
2326	{
2327	r_dcache.read(paddr,
2328	&cache_rdata,
2329	&cache_way,
2330	&cache_set,
2331	&cache_word,
2332	&cache_state);
2333
2334	#ifdef INSTRUMENTATION
2335	m_cpt_dcache_dir_read++;
2336	m_cpt_dcache_data_read++;
2337	#endif
2338	}
2339	else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA
2340	{
2341	r_dcache.write(r_dcache_save_cache_way.read(),
2342	r_dcache_save_cache_set.read(),
2343	r_dcache_save_cache_word.read(),
2344	r_dcache_save_wdata.read(),
2345	r_dcache_save_be.read());
2346	#ifdef INSTRUMENTATION
2347	m_cpt_dcache_data_write++;
2348	#endif
2349	}
2350	} // end dcache access
2351
2352	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2353	if (r_dcache_updt_req.read())
2354	{
2355	size_t way = r_dcache_save_cache_way.read();
2356	size_t set = r_dcache_save_cache_set.read();
2357
2358	if (r_dcache_in_tlb[way * m_dcache_sets + set])
2359	{
2360	tlb_inval_required = true;
2361	r_dcache_tlb_inval_set = 0;
2362	r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >>
2363	(uint32_log2(m_dcache_words << 2));
2364	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
2365	}
2366	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
2367	{
2368	r_itlb.reset();
2369	r_dtlb.reset();
2370	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
2371	}
2372
2373	#if DEBUG_DCACHE
2374	if (m_debug_dcache_fsm)
2375	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2376	<< " Cache update in P1 stage" << std::dec
2377	<< " / WAY = " << r_dcache_save_cache_way.read()
2378	<< " / SET = " << r_dcache_save_cache_set.read()
2379	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2380	<< " / WDATA = " << r_dcache_save_wdata.read()
2381	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2382	#endif
2383	} // end test TLB inval
2384
2385	// Try WBUF update in P1 stage
2386	// Miss if the write request is non cacheable, and there is a pending
2387	// non cacheable write, or if the write buffer is full.
2388	if (r_dcache_wbuf_req.read())
2389	{
2390	bool wok = r_wbuf.write(r_dcache_save_paddr.read(),
2391	r_dcache_save_be.read(),
2392	r_dcache_save_wdata.read(),
2393	true);
2394	#ifdef INSTRUMENTATION
2395	m_cpt_wbuf_write++;
2396	#endif
2397	if (not wok ) // miss if write buffer full
2398	{
2399	wbuf_write_miss = true;
2400	}
2401	} // end WBUF update
2402
2403	// Computing the response to processor,
2404	// and the next value for r_dcache_fsm
2405
2406	// itlb/dtlb invalidation self-request
2407	if (tlb_inval_required)
2408	{
2409	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2410	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2411	}
2412
2413	// coherence clack request (from DSPIN CLACK)
2414	else if (r_dcache_clack_req.read())
2415	{
2416	r_dcache_fsm = DCACHE_CC_CHECK;
2417	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2418	}
2419	// coherence request (from CC_RECEIVE FSM)
2420	else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
2421	{
2422	r_dcache_fsm = DCACHE_CC_CHECK;
2423	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2424	}
2425
2426	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2427	// we don't take the processor request, and registers
2428	// are frozen in case of wbuf_write_miss
2429	else if (m_dreq.valid and not wbuf_write_miss)
2430	{
2431	// register processor request and DCACHE response
2432	r_dcache_save_vaddr = m_dreq.addr;
2433	r_dcache_save_be = m_dreq.be;
2434	r_dcache_save_wdata = m_dreq.wdata;
2435	r_dcache_save_paddr = paddr;
2436	r_dcache_save_cache_way = cache_way;
2437	r_dcache_save_cache_set = cache_set;
2438	r_dcache_save_cache_word = cache_word;
2439
2440	// READ XTN requests from processor
2441	// They are executed in this DCACHE_IDLE state.
2442	// The processor must not be in user mode
2443	if (m_dreq.type == iss_t::XTN_READ)
2444	{
2445	int xtn_opcode = (int) m_dreq.addr / 4;
2446
2447	// checking processor mode:
2448	if (m_dreq.mode == iss_t::MODE_USER)
2449	{
2450	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2451	r_mmu_dbvar = m_dreq.addr;
2452	m_drsp.valid = true;
2453	m_drsp.error = true;
2454	m_drsp.rdata = 0;
2455	r_dcache_fsm = DCACHE_IDLE;
2456	}
2457	else
2458	{
2459	switch (xtn_opcode)
2460	{
2461	case iss_t::XTN_INS_ERROR_TYPE:
2462	m_drsp.rdata = r_mmu_ietr.read();
2463	m_drsp.valid = true;
2464	m_drsp.error = false;
2465	break;
2466
2467	case iss_t::XTN_DATA_ERROR_TYPE:
2468	m_drsp.rdata = r_mmu_detr.read();
2469	m_drsp.valid = true;
2470	m_drsp.error = false;
2471	break;
2472
2473	case iss_t::XTN_INS_BAD_VADDR:
2474	m_drsp.rdata = r_mmu_ibvar.read();
2475	m_drsp.valid = true;
2476	m_drsp.error = false;
2477	break;
2478
2479	case iss_t::XTN_DATA_BAD_VADDR:
2480	m_drsp.rdata = r_mmu_dbvar.read();
2481	m_drsp.valid = true;
2482	m_drsp.error = false;
2483	break;
2484
2485	case iss_t::XTN_PTPR:
2486	m_drsp.rdata = r_mmu_ptpr.read();
2487	m_drsp.valid = true;
2488	m_drsp.error = false;
2489	break;
2490
2491	case iss_t::XTN_TLB_MODE:
2492	m_drsp.rdata = r_mmu_mode.read();
2493	m_drsp.valid = true;
2494	m_drsp.error = false;
2495	break;
2496
2497	case iss_t::XTN_MMU_PARAMS:
2498	m_drsp.rdata = r_mmu_params;
2499	m_drsp.valid = true;
2500	m_drsp.error = false;
2501	break;
2502
2503	case iss_t::XTN_MMU_RELEASE:
2504	m_drsp.rdata = r_mmu_release;
2505	m_drsp.valid = true;
2506	m_drsp.error = false;
2507	break;
2508
2509	case iss_t::XTN_MMU_WORD_LO:
2510	m_drsp.rdata = r_mmu_word_lo.read();
2511	m_drsp.valid = true;
2512	m_drsp.error = false;
2513	break;
2514
2515	case iss_t::XTN_MMU_WORD_HI:
2516	m_drsp.rdata = r_mmu_word_hi.read();
2517	m_drsp.valid = true;
2518	m_drsp.error = false;
2519	break;
2520
2521	case iss_t::XTN_DATA_PADDR_EXT:
2522	m_drsp.rdata = r_dcache_paddr_ext.read();
2523	m_drsp.valid = true;
2524	m_drsp.error = false;
2525	break;
2526
2527	case iss_t::XTN_INST_PADDR_EXT:
2528	m_drsp.rdata = r_icache_paddr_ext.read();
2529	m_drsp.valid = true;
2530	m_drsp.error = false;
2531	break;
2532
2533	case XTN_WDT_MAX:
2534	m_drsp.rdata = r_dcache_miss_wdt_max.read();
2535	m_drsp.valid = true;
2536	m_drsp.error = false;
2537	break;
2538
2539	default:
2540	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2541	r_mmu_dbvar = m_dreq.addr;
2542	m_drsp.valid = true;
2543	m_drsp.error = true;
2544	m_drsp.rdata = 0;
2545	break;
2546	} // end switch xtn_opcode
2547	} // end else
2548	} // end if XTN_READ
2549
2550	// Handling WRITE XTN requests from processor.
2551	// They are not executed in this DCACHE_IDLE state
2552	// if they require access to the caches or the TLBs
2553	// that are already accessed.
2554	// Caches can be invalidated or flushed in user mode,
2555	// and the sync instruction can be executed in user mode
2556	else if (m_dreq.type == iss_t::XTN_WRITE)
2557	{
2558	int xtn_opcode = (int)m_dreq.addr / 4;
2559	r_dcache_xtn_opcode = xtn_opcode;
2560
2561	// checking processor mode:
2562	if ((m_dreq.mode == iss_t::MODE_USER) &&
2563	(xtn_opcode != iss_t::XTN_SYNC) &&
2564	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2565	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2566	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2567	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH))
2568	{
2569	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2570	r_mmu_dbvar = m_dreq.addr;
2571	m_drsp.valid = true;
2572	m_drsp.error = true;
2573	m_drsp.rdata = 0;
2574	r_dcache_fsm = DCACHE_IDLE;
2575	}
2576	else
2577	{
2578	switch (xtn_opcode)
2579	{
2580	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2581	r_dcache_xtn_req = true;
2582	r_dcache_fsm = DCACHE_XTN_SWITCH;
2583	break;
2584
2585	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2586	r_mmu_mode = m_dreq.wdata;
2587	m_drsp.valid = true;
2588	r_dcache_fsm = DCACHE_IDLE;
2589	break;
2590
2591	case iss_t::XTN_DTLB_INVAL: // dtlb access
2592	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2593	break;
2594
2595	case iss_t::XTN_ITLB_INVAL: // itlb access
2596	r_dcache_xtn_req = true;
2597	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2598	break;
2599
2600	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2601	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2602	break;
2603
2604	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2605	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2606	if (sizeof(paddr_t) <= 32)
2607	{
2608	assert(r_mmu_word_hi.read() == 0 &&
2609	"high bits should be 0 for 32bit paddr");
2610	r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read();
2611	}
2612	else
2613	{
2614	r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 \|
2615	(paddr_t)r_mmu_word_lo.read();
2616	}
2617	break;
2618
2619	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2620	r_dcache_flush_count = 0;
2621	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2622	break;
2623
2624	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2625	r_dcache_xtn_req = true;
2626	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2627	break;
2628
2629	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2630	r_dcache_xtn_req = true;
2631	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2632	break;
2633
2634	case iss_t::XTN_ICACHE_FLUSH: // icache access
2635	r_dcache_xtn_req = true;
2636	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2637	break;
2638
2639	case iss_t::XTN_SYNC: // wait until write buffer empty
2640	r_dcache_fsm = DCACHE_XTN_SYNC;
2641	break;
2642
2643	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2644	r_mmu_word_lo = m_dreq.wdata;
2645	m_drsp.valid = true;
2646	r_dcache_fsm = DCACHE_IDLE;
2647	break;
2648
2649	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2650	r_mmu_word_hi = m_dreq.wdata;
2651	m_drsp.valid = true;
2652	r_dcache_fsm = DCACHE_IDLE;
2653	break;
2654
2655	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2656	r_dcache_llsc_valid = false;
2657	m_drsp.valid = true;
2658	r_dcache_fsm = DCACHE_IDLE;
2659	break;
2660
2661	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
2662	r_dcache_paddr_ext = m_dreq.wdata;
2663	m_drsp.valid = true;
2664	r_dcache_fsm = DCACHE_IDLE;
2665	break;
2666
2667	case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access
2668	r_dcache_xtn_req = true;
2669	r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT;
2670	break;
2671
2672	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2673	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2674	m_drsp.valid = true;
2675	r_dcache_fsm = DCACHE_IDLE;
2676	break;
2677
2678	case XTN_WDT_MAX:
2679	r_dcache_miss_wdt_max = m_dreq.wdata;
2680	m_drsp.valid = true;
2681	r_dcache_fsm = DCACHE_IDLE;
2682	break;
2683
2684	case iss_t::XTN_DEBUG_MASK: // debug mask
2685	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
2686	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
2687	m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0);
2688	m_drsp.valid = true;
2689	r_dcache_fsm = DCACHE_IDLE;
2690	break;
2691
2692	default:
2693	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2694	r_mmu_dbvar = m_dreq.addr;
2695	m_drsp.valid = true;
2696	m_drsp.error = true;
2697	r_dcache_fsm = DCACHE_IDLE;
2698	break;
2699	} // end switch xtn_opcode
2700	} // end else
2701	} // end if XTN_WRITE
2702
2703	// Handling processor requests to address space (READ/WRITE/LL/SC)
2704	// The dtlb and dcache can be activated or not.
2705	// We compute the cacheability, and check processor request validity:
2706	// - If DTLB not activated : cacheability is defined by the segment table,
2707	// and there is no access rights checking.
2708	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2709	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2710	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2711	else
2712	{
2713	bool valid_req;
2714	bool cacheable;
2715
2716	if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated
2717	{
2718	valid_req = true;
2719
2720	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2721	else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
2722	}
2723	else // dtlb activated
2724	{
2725	if (tlb_hit) // tlb hit
2726	{
2727	// cacheability
2728	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2729	else cacheable = tlb_flags.c;
2730
2731	// access rights checking
2732	if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2733	{
2734	if ((m_dreq.type == iss_t::DATA_READ) or
2735	(m_dreq.type == iss_t::DATA_LL))
2736	{
2737	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2738	}
2739	else
2740	{
2741	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2742	}
2743	valid_req = false;
2744	r_mmu_dbvar = m_dreq.addr;
2745	m_drsp.valid = true;
2746	m_drsp.error = true;
2747	m_drsp.rdata = 0;
2748	#if DEBUG_DCACHE
2749	if (m_debug_dcache_fsm)
2750	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2751	<< " HIT in dtlb, but privilege violation" << std::endl;
2752	#endif
2753	}
2754	else if (not tlb_flags.w and
2755	((m_dreq.type == iss_t::DATA_WRITE) or
2756	(m_dreq.type == iss_t::DATA_SC)))
2757	{
2758	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2759	valid_req = false;
2760	r_mmu_dbvar = m_dreq.addr;
2761	m_drsp.valid = true;
2762	m_drsp.error = true;
2763	m_drsp.rdata = 0;
2764	#if DEBUG_DCACHE
2765	if (m_debug_dcache_fsm)
2766	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2767	<< " HIT in dtlb, but writable violation" << std::endl;
2768	#endif
2769	}
2770	else
2771	{
2772	valid_req = true;
2773	}
2774	}
2775	else // tlb miss
2776	{
2777	valid_req = false;
2778	r_dcache_tlb_vaddr = m_dreq.addr;
2779	r_dcache_tlb_ins = false;
2780	r_dcache_fsm = DCACHE_TLB_MISS;
2781	}
2782	} // end DTLB activated
2783
2784	if (valid_req) // processor request is valid (after MMU check)
2785	{
2786	// READ request
2787	// The read requests are taken only if there is no cache update.
2788	// We request a VCI transaction to CMD FSM if miss or uncachable
2789
2790	if (((m_dreq.type == iss_t::DATA_READ))
2791	and not r_dcache_updt_req.read())
2792	{
2793	if (cacheable) // cacheable read
2794	{
2795	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
2796	{
2797	#ifdef INSTRUMENTATION
2798	m_cpt_dcache_miss++;
2799	#endif
2800	// request a VCI DMISS transaction
2801	r_dcache_vci_paddr = paddr;
2802	r_dcache_vci_miss_req = true;
2803	r_dcache_miss_type = PROC_MISS;
2804	r_dcache_fsm = DCACHE_MISS_SELECT;
2805	#if DEBUG_DCACHE
2806	if (m_debug_dcache_fsm)
2807	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2808	<< " READ MISS in dcache"
2809	<< " / PADDR = " << std::hex << paddr << std::endl;
2810	#endif
2811	}
2812	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
2813	{
2814	// stalled until cleanup is acknowledged
2815	r_dcache_fsm = DCACHE_IDLE;
2816	#if DEBUG_DCACHE
2817	if (m_debug_dcache_fsm)
2818	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2819	<< " Pending cleanup, stalled until cleanup acknowledge"
2820	<< " / PADDR = " << std::hex << paddr << std::endl;
2821	#endif
2822	}
2823	else // cache hit
2824	{
2825	#ifdef INSTRUMENTATION
2826	m_cpt_data_read++;
2827	#endif
2828	// returns data to processor
2829	m_drsp.valid = true;
2830	m_drsp.error = false;
2831	m_drsp.rdata = cache_rdata;
2832	#if DEBUG_DCACHE
2833	if (m_debug_dcache_fsm)
2834	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2835	<< " READ HIT in dcache"
2836	<< " : PADDR = " << std::hex << paddr
2837	<< " / DATA = " << std::hex << cache_rdata << std::endl;
2838	#endif
2839	}
2840	}
2841	else // uncacheable read
2842	{
2843	r_dcache_vci_paddr = paddr;
2844	r_dcache_vci_unc_be = m_dreq.be;
2845	r_dcache_vci_unc_write = false;
2846	r_dcache_vci_unc_req = true;
2847	r_dcache_fsm = DCACHE_UNC_WAIT;
2848	#if DEBUG_DCACHE
2849	if (m_debug_dcache_fsm)
2850	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2851	<< " READ UNCACHEABLE in dcache"
2852	<< " / PADDR = " << std::hex << paddr << std::endl;
2853	#endif
2854	}
2855	} // end READ
2856
2857	// LL request (non cachable)
2858	// We request a VCI LL transaction to CMD FSM and register
2859	// the LL/SC operation in llsc buffer.
2860	else if (m_dreq.type == iss_t::DATA_LL)
2861	{
2862	// register paddr in LLSC buffer
2863	r_dcache_llsc_paddr = paddr;
2864	r_dcache_llsc_count = LLSC_TIMEOUT;
2865	r_dcache_llsc_valid = true;
2866
2867	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2868	r_dcache_vci_ll_req = true;
2869	r_dcache_vci_paddr = paddr;
2870	r_dcache_ll_rsp_count = 0;
2871	r_dcache_fsm = DCACHE_LL_WAIT;
2872
2873	}// end LL
2874
2875	// WRITE request:
2876	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2877	// the processor and set the Dirty bit before handling the write request,
2878	// going to the DCACHE_DIRTY_GT_PTE state.
2879	// If we don't need to set the Dirty bit, we can acknowledge
2880	// the processor request, as the write arguments (including the
2881	// physical address) are registered in r_dcache_save registers,
2882	// and the write will be done in the P1 pipeline stage.
2883	else if (m_dreq.type == iss_t::DATA_WRITE)
2884	{
2885	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2886	and not tlb_flags.d) // Dirty bit must be set
2887	{
2888	// The PTE physical address is obtained from the nline value (dtlb),
2889	// and from the virtual address (word index)
2890	if (tlb_flags.b ) // PTE1
2891	{
2892	r_dcache_dirty_paddr = (paddr_t)(tlb_nline * (m_dcache_words << 2)) \|
2893	(paddr_t)((m_dreq.addr >> 19) & 0x3c);
2894	}
2895	else // PTE2
2896	{
2897	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2898	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2899	}
2900	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2901	}
2902	else // Write request accepted
2903	{
2904	#ifdef INSTRUMENTATION
2905	m_cpt_data_write++;
2906	#endif
2907	// cleaning llsc buffer if address matching
2908	if (paddr == r_dcache_llsc_paddr.read())
2909	r_dcache_llsc_valid = false;
2910
2911	if (not cacheable) // uncacheable write
2912	{
2913	r_dcache_vci_paddr = paddr;
2914	r_dcache_vci_wdata = m_dreq.wdata;
2915	r_dcache_vci_unc_write = true;
2916	r_dcache_vci_unc_be = m_dreq.be;
2917	r_dcache_vci_unc_req = true;
2918	r_dcache_fsm = DCACHE_UNC_WAIT;
2919	}
2920	else
2921	{
2922	// response to processor
2923	m_drsp.valid = true;
2924	// activating P1 stage
2925	wbuf_request = true;
2926	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2927	}
2928	}
2929	} // end WRITE
2930
2931	// SC request:
2932	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2933	// the processor and set the Dirty bit before handling the write request,
2934	// going to the DCACHE_DIRTY_GT_PTE state.
2935	// If we don't need to set the Dirty bit, we test the llsc buffer:
2936	// If failure, we send a negative response to processor.
2937	// If success, we request a SC transaction to CMD FSM and go
2938	// to DCACHE_SC_WAIT state.
2939	// We don't check a possible write hit in dcache, as the cache update
2940	// is done by the coherence transaction induced by the SC...
2941	else if (m_dreq.type == iss_t::DATA_SC)
2942	{
2943	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2944	and not tlb_flags.d) // Dirty bit must be set
2945	{
2946	// The PTE physical address is obtained from the nline value (dtlb),
2947	// and the word index (virtual address)
2948	if (tlb_flags.b) // PTE1
2949	{
2950	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2951	(paddr_t) ((m_dreq.addr >> 19) & 0x3c);
2952	}
2953	else // PTE2
2954	{
2955	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2956	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2957	}
2958	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2959	m_drsp.valid = false;
2960	m_drsp.error = false;
2961	m_drsp.rdata = 0;
2962	}
2963	else // SC request accepted
2964	{
2965	#ifdef INSTRUMENTATION
2966	m_cpt_data_sc++;
2967	#endif
2968	// checking local success
2969	if (r_dcache_llsc_valid.read() and
2970	(r_dcache_llsc_paddr.read() == paddr)) // local success
2971	{
2972	// request an SC CMD and go to DCACHE_SC_WAIT state
2973	r_dcache_vci_paddr = paddr;
2974	r_dcache_vci_sc_req = true;
2975	r_dcache_vci_sc_data = m_dreq.wdata;
2976	r_dcache_fsm = DCACHE_SC_WAIT;
2977	}
2978	else // local fail
2979	{
2980	m_drsp.valid = true;
2981	m_drsp.error = false;
2982	m_drsp.rdata = 0x1;
2983	}
2984	}
2985	} // end SC
2986	} // end valid_req
2987	} // end if read/write/ll/sc request
2988	} // end processor request
2989
2990	// itlb miss request
2991	else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
2992	{
2993	r_dcache_tlb_ins = true;
2994	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
2995	r_dcache_fsm = DCACHE_TLB_MISS;
2996	}
2997
2998	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
2999	r_dcache_updt_req = updt_request;
3000	r_dcache_wbuf_req = wbuf_request or
3001	(r_dcache_wbuf_req.read() and wbuf_write_miss);
3002	break;
3003	}
3004	/////////////////////
3005	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
3006	// Input arguments are:
3007	// - r_dcache_tlb_vaddr
3008	// - r_dcache_tlb_ins (true when itlb miss)
3009	// The sub-fsm access the dcache to find the missing TLB entry,
3010	// and activates the cache miss procedure in case of miss.
3011	// It bypass the first level page table access if possible.
3012	// It uses atomic access to update the R/L access bits
3013	// in the page table if required.
3014	// It directly updates the itlb or dtlb, and writes into the
3015	// r_mmu_ins_* or r_mmu_data* error reporting registers.
3016	{
3017	uint32_t ptba = 0;
3018	bool bypass;
3019	paddr_t pte_paddr;
3020
3021	// evaluate bypass in order to skip first level page table access
3022	if (r_dcache_tlb_ins.read()) // itlb miss
3023	{
3024	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3025	}
3026	else // dtlb miss
3027	{
3028	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3029	}
3030
3031	if (not bypass) // Try to read PTE1/PTD1 in dcache
3032	{
3033	pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) \|
3034	((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
3035	r_dcache_tlb_paddr = pte_paddr;
3036	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3037	}
3038	else // Try to read PTE2 in dcache
3039	{
3040	pte_paddr = (paddr_t) ptba << PAGE_K_NBITS \|
3041	(paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3);
3042	r_dcache_tlb_paddr = pte_paddr;
3043	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3044	}
3045
3046	#if DEBUG_DCACHE
3047	if (m_debug_dcache_fsm)
3048	{
3049	if (r_dcache_tlb_ins.read())
3050	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
3051	else
3052	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
3053	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
3054	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
3055	<< " / BYPASS = " << bypass
3056	<< " / PTE_ADR = " << pte_paddr << std::endl;
3057	}
3058	#endif
3059
3060	break;
3061	}
3062	/////////////////////////
3063	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
3064	{
3065	// coherence clack request (from DSPIN CLACK)
3066	if (r_dcache_clack_req.read())
3067	{
3068	r_dcache_fsm = DCACHE_CC_CHECK;
3069	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3070	break;
3071	}
3072
3073	// coherence request (from CC_RECEIVE FSM)
3074	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3075	{
3076	r_dcache_fsm = DCACHE_CC_CHECK;
3077	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3078	break;
3079	}
3080
3081	uint32_t entry;
3082	size_t way;
3083	size_t set;
3084	size_t word;
3085	int cache_state;
3086	r_dcache.read(r_dcache_tlb_paddr.read(),
3087	&entry,
3088	&way,
3089	&set,
3090	&word,
3091	&cache_state);
3092	#ifdef INSTRUMENTATION
3093	m_cpt_dcache_data_read++;
3094	m_cpt_dcache_dir_read++;
3095	#endif
3096	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3097	{
3098	if (not (entry & PTE_V_MASK)) // unmapped
3099	{
3100	if (r_dcache_tlb_ins.read())
3101	{
3102	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
3103	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3104	r_icache_tlb_miss_req = false;
3105	r_icache_tlb_rsp_error = true;
3106	}
3107	else
3108	{
3109	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
3110	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3111	m_drsp.valid = true;
3112	m_drsp.error = true;
3113	}
3114	r_dcache_fsm = DCACHE_IDLE;
3115
3116	#if DEBUG_DCACHE
3117	if (m_debug_dcache_fsm)
3118	{
3119	std::cout << " <PROC " << name()
3120	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
3121	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3122	<< std::dec << " / way = " << way
3123	<< std::dec << " / set = " << set
3124	<< std::dec << " / word = " << word
3125	<< std::hex << " / PTE1 = " << entry << std::endl;
3126	}
3127	#endif
3128
3129	}
3130	else if (entry & PTE_T_MASK) // PTD : me must access PT2
3131	{
3132	// mark the cache line ac containing a PTD
3133	r_dcache_contains_ptd[m_dcache_sets * way + set] = true;
3134
3135	// register bypass
3136	if (r_dcache_tlb_ins.read()) // itlb
3137	{
3138	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
3139	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3140	r_dcache_tlb_paddr.read() / (m_icache_words << 2));
3141	}
3142	else // dtlb
3143	{
3144	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
3145	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3146	r_dcache_tlb_paddr.read() / (m_dcache_words << 2));
3147	}
3148	r_dcache_tlb_paddr =
3149	(paddr_t)(entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS \|
3150	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3151	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3152
3153	#if DEBUG_DCACHE
3154	if (m_debug_dcache_fsm)
3155	{
3156	std::cout << " <PROC " << name()
3157	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3158	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3159	<< std::dec << " / way = " << way
3160	<< std::dec << " / set = " << set
3161	<< std::dec << " / word = " << word
3162	<< std::hex << " / PTD = " << entry << std::endl;
3163	}
3164	#endif
3165	}
3166	else // PTE1 : we must update the TLB
3167	{
3168	r_dcache_in_tlb[m_icache_sets * way + set] = true;
3169	r_dcache_tlb_pte_flags = entry;
3170	r_dcache_tlb_cache_way = way;
3171	r_dcache_tlb_cache_set = set;
3172	r_dcache_tlb_cache_word = word;
3173	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
3174
3175	#if DEBUG_DCACHE
3176	if (m_debug_dcache_fsm)
3177	{
3178	std::cout << " <PROC " << name()
3179	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3180	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3181	<< std::dec << " / way = " << way
3182	<< std::dec << " / set = " << set
3183	<< std::dec << " / word = " << word
3184	<< std::hex << " / PTE1 = " << entry << std::endl;
3185	}
3186	#endif
3187	}
3188	}
3189	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3190	{
3191	// stalled until cleanup is acknowledged
3192	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3193	}
3194	else // we must load the missing cache line in dcache
3195	{
3196	r_dcache_vci_miss_req = true;
3197	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3198	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3199	r_dcache_miss_type = PTE1_MISS;
3200	r_dcache_fsm = DCACHE_MISS_SELECT;
3201
3202	#if DEBUG_DCACHE
3203	if (m_debug_dcache_fsm)
3204	{
3205	std::cout << " <PROC " << name()
3206	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
3207	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3208	}
3209	#endif
3210	}
3211	break;
3212	}
3213	////////////////////////////
3214	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3215	{
3216	size_t way;
3217	size_t set;
3218
3219	if (r_dcache_tlb_ins.read())
3220	{
3221	r_itlb.select(r_dcache_tlb_vaddr.read(),
3222	true, // PTE1
3223	&way,
3224	&set);
3225	#ifdef INSTRUMENTATION
3226	m_cpt_itlb_read++;
3227	#endif
3228	}
3229	else
3230	{
3231	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3232	true, // PTE1
3233	&way,
3234	&set);
3235	#ifdef INSTRUMENTATION
3236	m_cpt_dtlb_read++;
3237	#endif
3238	}
3239	r_dcache_tlb_way = way;
3240	r_dcache_tlb_set = set;
3241	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3242
3243	#if DEBUG_DCACHE
3244	if (m_debug_dcache_fsm)
3245	{
3246	if (r_dcache_tlb_ins.read())
3247	std::cout << " <PROC " << name()
3248	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3249	else
3250	std::cout << " <PROC " << name()
3251	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3252	std::cout << " way = " << std::dec << way
3253	<< " / set = " << set << std::endl;
3254	}
3255	#endif
3256	break;
3257	}
3258	//////////////////////////
3259	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3260	// - if L/R bit already set, exit the sub-fsm.
3261	// - if not, we update the page table but we dont write
3262	// neither in DCACHE, nor in TLB, as this will be done by
3263	// the coherence mechanism.
3264	{
3265	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3266	uint32_t pte = r_dcache_tlb_pte_flags.read();
3267	bool pt_updt = false;
3268	bool local = true;
3269
3270	// We should compute the access locality:
3271	// The PPN MSB bits define the destination cluster index.
3272	// The m_srcid MSB bits define the source cluster index.
3273	// The number of bits to compare depends on the number of clusters,
3274	// and can be obtained in the mapping table.
3275	// As long as this computation is not done, all access are local.
3276
3277	if (local) // local access
3278	{
3279	if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3280	{
3281	pt_updt = true;
3282	r_dcache_vci_cas_old = pte;
3283	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3284	pte = pte \| PTE_L_MASK;
3285	r_dcache_tlb_pte_flags = pte;
3286	}
3287	}
3288	else // remote access
3289	{
3290	if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3291	{
3292	pt_updt = true;
3293	r_dcache_vci_cas_old = pte;
3294	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3295	pte = pte \| PTE_R_MASK;
3296	r_dcache_tlb_pte_flags = pte;
3297	}
3298	}
3299
3300	if (not pt_updt) // update TLB and return
3301	{
3302	if (r_dcache_tlb_ins.read())
3303	{
3304	r_itlb.write(true, // 2M page
3305	pte,
3306	0, // argument unused for a PTE1
3307	r_dcache_tlb_vaddr.read(),
3308	r_dcache_tlb_way.read(),
3309	r_dcache_tlb_set.read(),
3310	nline);
3311	#ifdef INSTRUMENTATION
3312	m_cpt_itlb_write++;
3313	#endif
3314
3315	#if DEBUG_DCACHE
3316	if (m_debug_dcache_fsm)
3317	{
3318	std::cout << " <PROC " << name()
3319	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
3320	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3321	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3322	r_itlb.printTrace();
3323	}
3324	#endif
3325	}
3326	else
3327	{
3328	r_dtlb.write(true, // 2M page
3329	pte,
3330	0, // argument unused for a PTE1
3331	r_dcache_tlb_vaddr.read(),
3332	r_dcache_tlb_way.read(),
3333	r_dcache_tlb_set.read(),
3334	nline);
3335	#ifdef INSTRUMENTATION
3336	m_cpt_dtlb_write++;
3337	#endif
3338
3339	#if DEBUG_DCACHE
3340	if (m_debug_dcache_fsm)
3341	{
3342	std::cout << " <PROC " << name()
3343	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
3344	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3345	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3346	r_dtlb.printTrace();
3347	}
3348	#endif
3349	}
3350	r_dcache_fsm = DCACHE_TLB_RETURN;
3351	}
3352	else // update page table but not TLB
3353	{
3354	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3355
3356	#if DEBUG_DCACHE
3357	if (m_debug_dcache_fsm)
3358	{
3359	std::cout << " <PROC " << name()
3360	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3361	<< std::endl;
3362	}
3363	#endif
3364	}
3365	break;
3366	}
3367	/////////////////////////
3368	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3369	{
3370	// coherence clack request (from DSPIN CLACK)
3371	if (r_dcache_clack_req.read())
3372	{
3373	r_dcache_fsm = DCACHE_CC_CHECK;
3374	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3375	break;
3376	}
3377
3378	// coherence request (from CC_RECEIVE FSM)
3379	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3380	{
3381	r_dcache_fsm = DCACHE_CC_CHECK;
3382	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3383	break;
3384	}
3385
3386	uint32_t pte_flags;
3387	uint32_t pte_ppn;
3388	size_t way;
3389	size_t set;
3390	size_t word;
3391	int cache_state;
3392
3393	r_dcache.read(r_dcache_tlb_paddr.read(),
3394	&pte_flags,
3395	&pte_ppn,
3396	&way,
3397	&set,
3398	&word,
3399	&cache_state);
3400	#ifdef INSTRUMENTATION
3401	m_cpt_dcache_data_read++;
3402	m_cpt_dcache_dir_read++;
3403	#endif
3404	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3405	{
3406	if (not (pte_flags & PTE_V_MASK)) // unmapped
3407	{
3408	if (r_dcache_tlb_ins.read())
3409	{
3410	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3411	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3412	r_icache_tlb_miss_req = false;
3413	r_icache_tlb_rsp_error = true;
3414	}
3415	else
3416	{
3417	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3418	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3419	m_drsp.valid = true;
3420	m_drsp.error = true;
3421	}
3422	r_dcache_fsm = DCACHE_IDLE;
3423
3424	#if DEBUG_DCACHE
3425	if (m_debug_dcache_fsm)
3426	{
3427	std::cout << " <PROC " << name()
3428	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3429	<< " PTE_FLAGS = " << std::hex << pte_flags
3430	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3431	}
3432	#endif
3433	}
3434	else // mapped : we must update the TLB
3435	{
3436	r_dcache_in_tlb[m_dcache_sets * way + set] = true;
3437	r_dcache_tlb_pte_flags = pte_flags;
3438	r_dcache_tlb_pte_ppn = pte_ppn;
3439	r_dcache_tlb_cache_way = way;
3440	r_dcache_tlb_cache_set = set;
3441	r_dcache_tlb_cache_word = word;
3442	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3443
3444	#if DEBUG_DCACHE
3445	if (m_debug_dcache_fsm)
3446	{
3447	std::cout << " <PROC " << name()
3448	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3449	<< " PTE_FLAGS = " << std::hex << pte_flags
3450	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3451	}
3452	#endif
3453	}
3454	}
3455	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3456	{
3457	// stalled until cleanup is acknowledged
3458	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3459
3460	#if DEBUG_DCACHE
3461	if (m_debug_dcache_fsm)
3462	{
3463	std::cout << " <PROC " << name()
3464	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3465	<< std::endl;
3466	}
3467	#endif
3468	}
3469	else // we must load the missing cache line in dcache
3470	{
3471	r_dcache_fsm = DCACHE_MISS_SELECT;
3472	r_dcache_vci_miss_req = true;
3473	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3474	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3475	r_dcache_miss_type = PTE2_MISS;
3476
3477	#if DEBUG_DCACHE
3478	if (m_debug_dcache_fsm)
3479	{
3480	std::cout << " <PROC " << name()
3481	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3482	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3483	}
3484	#endif
3485	}
3486	break;
3487	}
3488	////////////////////////////
3489	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3490	{
3491	size_t way;
3492	size_t set;
3493
3494	if (r_dcache_tlb_ins.read())
3495	{
3496	r_itlb.select(r_dcache_tlb_vaddr.read(),
3497	false, // PTE2
3498	&way,
3499	&set);
3500	#ifdef INSTRUMENTATION
3501	m_cpt_itlb_read++;
3502	#endif
3503	}
3504	else
3505	{
3506	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3507	false, // PTE2
3508	&way,
3509	&set);
3510	#ifdef INSTRUMENTATION
3511	m_cpt_dtlb_read++;
3512	#endif
3513	}
3514
3515	#if DEBUG_DCACHE
3516	if (m_debug_dcache_fsm)
3517	{
3518	if (r_dcache_tlb_ins.read())
3519	std::cout << " <PROC " << name()
3520	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3521	else
3522	std::cout << " <PROC " << name()
3523	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3524	std::cout << " way = " << std::dec << way
3525	<< " / set = " << set << std::endl;
3526	}
3527	#endif
3528	r_dcache_tlb_way = way;
3529	r_dcache_tlb_set = set;
3530	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3531	break;
3532	}
3533	//////////////////////////
3534	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3535	// - if L/R bit already set, exit the sub-fsm.
3536	// - if not, we update the page table but we dont write
3537	// neither in DCACHE, nor in TLB, as this will be done by
3538	// the coherence mechanism.
3539	{
3540	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3541	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3542	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3543	bool pt_updt = false;
3544	bool local = true;
3545
3546	// We should compute the access locality:
3547	// The PPN MSB bits define the destination cluster index.
3548	// The m_srcid MSB bits define the source cluster index.
3549	// The number of bits to compare depends on the number of clusters,
3550	// and can be obtained in the mapping table.
3551	// As long as this computation is not done, all access are local.
3552
3553	if (local) // local access
3554	{
3555	if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3556	{
3557	pt_updt = true;
3558	r_dcache_vci_cas_old = pte_flags;
3559	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3560	pte_flags = pte_flags \| PTE_L_MASK;
3561	r_dcache_tlb_pte_flags = pte_flags;
3562	}
3563	}
3564	else // remote access
3565	{
3566	if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3567	{
3568	pt_updt = true;
3569	r_dcache_vci_cas_old = pte_flags;
3570	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3571	pte_flags = pte_flags \| PTE_R_MASK;
3572	r_dcache_tlb_pte_flags = pte_flags;
3573	}
3574	}
3575
3576	if (not pt_updt) // update TLB
3577	{
3578	if (r_dcache_tlb_ins.read())
3579	{
3580	r_itlb.write( false, // 4K page
3581	pte_flags,
3582	pte_ppn,
3583	r_dcache_tlb_vaddr.read(),
3584	r_dcache_tlb_way.read(),
3585	r_dcache_tlb_set.read(),
3586	nline );
3587	#ifdef INSTRUMENTATION
3588	m_cpt_itlb_write++;
3589	#endif
3590
3591	#if DEBUG_DCACHE
3592	if (m_debug_dcache_fsm)
3593	{
3594	std::cout << " <PROC " << name()
3595	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3596	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3597	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3598	r_itlb.printTrace();
3599	}
3600	#endif
3601	}
3602	else
3603	{
3604	r_dtlb.write(false, // 4K page
3605	pte_flags,
3606	pte_ppn,
3607	r_dcache_tlb_vaddr.read(),
3608	r_dcache_tlb_way.read(),
3609	r_dcache_tlb_set.read(),
3610	nline);
3611	#ifdef INSTRUMENTATION
3612	m_cpt_dtlb_write++;
3613	#endif
3614
3615	#if DEBUG_DCACHE
3616	if (m_debug_dcache_fsm)
3617	{
3618	std::cout << " <PROC " << name()
3619	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3620	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3621	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3622	r_dtlb.printTrace();
3623	}
3624	#endif
3625
3626	}
3627	r_dcache_fsm = DCACHE_TLB_RETURN;
3628	}
3629	else // update page table but not TLB
3630	{
3631	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3632
3633	#if DEBUG_DCACHE
3634	if (m_debug_dcache_fsm)
3635	{
3636	std::cout << " <PROC " << name()
3637	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3638	}
3639	#endif
3640	}
3641	break;
3642	}
3643	////////////////////////
3644	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3645	{
3646	#if DEBUG_DCACHE
3647	if (m_debug_dcache_fsm)
3648	{
3649	std::cout << " <PROC " << name()
3650	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3651	}
3652	#endif
3653	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3654	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3655
3656	// checking llsc reservation buffer
3657	if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read())
3658	r_dcache_llsc_valid = false;
3659
3660	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3661	r_dcache_vci_cas_req = true;
3662	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3663	break;
3664	}
3665	////////////////////////
3666	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3667	// We consume the response in rsp FIFO,
3668	// and exit the sub-fsm, but we don't
3669	// analyse the response, because we don't
3670	// care if the L/R bit update is not done.
3671	// We must take the coherence requests because
3672	// there is a risk of dead-lock
3673
3674	{
3675	// coherence clack request (from DSPIN CLACK)
3676	if (r_dcache_clack_req.read())
3677	{
3678	r_dcache_fsm = DCACHE_CC_CHECK;
3679	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3680	break;
3681	}
3682
3683	// coherence request (from CC_RECEIVE FSM)
3684	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3685	{
3686	r_dcache_fsm = DCACHE_CC_CHECK;
3687	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3688	break;
3689	}
3690
3691	if (r_vci_rsp_data_error.read()) // bus error
3692	{
3693	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3694	std::cout << "This should not happen in this state" << std::endl;
3695	exit(0);
3696	}
3697	else if (r_vci_rsp_fifo_dcache.rok()) // response available
3698	{
3699	#if DEBUG_DCACHE
3700	if (m_debug_dcache_fsm)
3701	{
3702	std::cout << " <PROC " << name()
3703	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3704	}
3705	#endif
3706	vci_rsp_fifo_dcache_get = true;
3707	r_dcache_fsm = DCACHE_TLB_RETURN;
3708	}
3709	break;
3710	}
3711	///////////////////////
3712	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3713	{
3714	#if DEBUG_DCACHE
3715	if (m_debug_dcache_fsm)
3716	{
3717	std::cout << " <PROC " << name()
3718	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3719	}
3720	#endif
3721	if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false;
3722	r_dcache_fsm = DCACHE_IDLE;
3723	break;
3724	}
3725	///////////////////////
3726	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3727	// and both itlb and dtlb must be flushed.
3728	// Caution : the itlb miss requests must be taken
3729	// to avoid dead-lock in case of simultaneous ITLB miss
3730	// Caution : the clack and cc requests must be taken
3731	// to avoid dead-lock
3732	{
3733	// coherence clack request (from DSPIN CLACK)
3734	if (r_dcache_clack_req.read())
3735	{
3736	r_dcache_fsm = DCACHE_CC_CHECK;
3737	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3738	break;
3739	}
3740
3741	// coherence request (from CC_RECEIVE FSM)
3742	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3743	{
3744	r_dcache_fsm = DCACHE_CC_CHECK;
3745	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3746	break;
3747	}
3748
3749	// itlb miss request
3750	if (r_icache_tlb_miss_req.read())
3751	{
3752	r_dcache_tlb_ins = true;
3753	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3754	r_dcache_fsm = DCACHE_TLB_MISS;
3755	break;
3756	}
3757
3758	if (not r_dcache_xtn_req.read())
3759	{
3760	r_dtlb.flush();
3761	r_mmu_ptpr = m_dreq.wdata;
3762	r_dcache_fsm = DCACHE_IDLE;
3763	m_drsp.valid = true;
3764	}
3765	break;
3766	}
3767	/////////////////////
3768	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3769	// The coherence request must be taken
3770	// as there is a risk of dead-lock
3771	{
3772	// coherence clack request (from DSPIN CLACK)
3773	if (r_dcache_clack_req.read())
3774	{
3775	r_dcache_fsm = DCACHE_CC_CHECK;
3776	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3777	break;
3778	}
3779
3780	// coherence request (from CC_RECEIVE FSM)
3781	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3782	{
3783	r_dcache_fsm = DCACHE_CC_CHECK;
3784	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3785	break;
3786	}
3787
3788	if (r_wbuf.empty())
3789	{
3790	m_drsp.valid = true;
3791	r_dcache_fsm = DCACHE_IDLE;
3792	}
3793	break;
3794	}
3795	////////////////////////
3796	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3797	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3798	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3799	case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss,
3800	case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss
3801
3802	{
3803	// coherence clack request (from DSPIN CLACK)
3804	if (r_dcache_clack_req.read())
3805	{
3806	r_dcache_fsm = DCACHE_CC_CHECK;
3807	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3808	break;
3809	}
3810
3811	// coherence request (from CC_RECEIVE FSM)
3812	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3813	{
3814	r_dcache_fsm = DCACHE_CC_CHECK;
3815	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3816	break;
3817	}
3818
3819	// itlb miss request
3820	if (r_icache_tlb_miss_req.read())
3821	{
3822	r_dcache_tlb_ins = true;
3823	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3824	r_dcache_fsm = DCACHE_TLB_MISS;
3825	break;
3826	}
3827
3828	// test if XTN request to icache completed
3829	if (not r_dcache_xtn_req.read())
3830	{
3831	r_dcache_fsm = DCACHE_IDLE;
3832	m_drsp.valid = true;
3833	}
3834	break;
3835	}
3836	/////////////////////////
3837	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3838	// r_dcache_flush_count as a slot counter,
3839	// looping in this state until all slots have been visited.
3840	// It can require two cycles per slot:
3841	// We test here the slot state, and make the actual inval
3842	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3843	// A cleanup request is generated for each valid line.
3844	// returns to IDLE and flush TLBs when last slot
3845	{
3846	// coherence clack request (from DSPIN CLACK)
3847	if (r_dcache_clack_req.read())
3848	{
3849	r_dcache_fsm = DCACHE_CC_CHECK;
3850	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3851	break;
3852	}
3853
3854	// coherence request (from CC_RECEIVE FSM)
3855	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3856	{
3857	r_dcache_fsm = DCACHE_CC_CHECK;
3858	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3859	break;
3860	}
3861
3862	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
3863	{
3864	int state;
3865	paddr_t tag;
3866	size_t way = r_dcache_flush_count.read() / m_dcache_sets;
3867	size_t set = r_dcache_flush_count.read() % m_dcache_sets;
3868
3869	#ifdef INSTRUMENTATION
3870	m_cpt_dcache_dir_read++;
3871	#endif
3872	r_dcache.read_dir(way,
3873	set,
3874	&tag,
3875	&state);
3876
3877	if (state == CACHE_SLOT_STATE_VALID) // inval required
3878	{
3879	// request cleanup
3880	r_dcache_cc_send_req = true;
3881	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3882	r_dcache_cc_send_way = way;
3883	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3884
3885	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3886	r_dcache_miss_way = way;
3887	r_dcache_miss_set = set;
3888	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3889	}
3890	else if (r_dcache_flush_count.read() ==
3891	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3892	{
3893	r_dtlb.reset();
3894	r_itlb.reset();
3895	r_dcache_fsm = DCACHE_IDLE;
3896	m_drsp.valid = true;
3897	}
3898
3899	// saturation counter
3900	if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1))
3901	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3902	}
3903	break;
3904	}
3905	////////////////////////////
3906	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3907	// and reset directory extension.
3908	// returns to IDLE and flush TLBs when last slot
3909	{
3910	size_t way = r_dcache_miss_way.read();
3911	size_t set = r_dcache_miss_set.read();
3912
3913	r_dcache_in_tlb[m_dcache_sets * way + set] = false;
3914	r_dcache_contains_ptd[m_dcache_sets * way + set] = false;
3915
3916	#ifdef INSTRUMENTATION
3917	m_cpt_dcache_dir_write++;
3918	#endif
3919	r_dcache.write_dir(way,
3920	set,
3921	CACHE_SLOT_STATE_ZOMBI);
3922
3923	if (r_dcache_flush_count.read() ==
3924	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3925	{
3926	r_dtlb.reset();
3927	r_itlb.reset();
3928	r_dcache_fsm = DCACHE_IDLE;
3929	m_drsp.valid = true;
3930	}
3931	else
3932	{
3933	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3934	}
3935	break;
3936	}
3937	/////////////////////////
3938	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3939	{
3940	r_dtlb.inval(r_dcache_save_wdata.read());
3941	r_dcache_fsm = DCACHE_IDLE;
3942	m_drsp.valid = true;
3943	break;
3944	}
3945	////////////////////////////
3946	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3947	// requires 3 cycles: access tlb, read cache, inval cache
3948	// we compute the physical address in this state
3949	{
3950	paddr_t paddr;
3951	bool hit;
3952
3953	if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated
3954	{
3955
3956	#ifdef INSTRUMENTATION
3957	m_cpt_dtlb_read++;
3958	#endif
3959	hit = r_dtlb.translate(r_dcache_save_wdata.read(),
3960	&paddr);
3961	}
3962	else // dtlb not activated
3963	{
3964	paddr = (paddr_t)r_dcache_save_wdata.read();
3965	if (vci_param::N > 32)
3966	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
3967	hit = true;
3968	}
3969
3970	if (hit) // tlb hit
3971	{
3972	r_dcache_save_paddr = paddr;
3973	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
3974	}
3975	else // tlb miss
3976	{
3977
3978	#ifdef INSTRUMENTATION
3979	m_cpt_dtlb_miss++;
3980	#endif
3981	r_dcache_tlb_ins = false; // dtlb
3982	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
3983	r_dcache_fsm = DCACHE_TLB_MISS;
3984	}
3985
3986	#if DEBUG_DCACHE
3987	if (m_debug_dcache_fsm)
3988	{
3989	std::cout << " <PROC " << name()
3990	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
3991	<< " / VADDR = " << r_dcache_save_wdata.read()
3992	<< " / PADDR = " << paddr << std::endl;
3993	}
3994	#endif
3995
3996	break;
3997	}
3998	////////////////////////////
3999	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
4000	// requires 2 cycles: read cache / inval cache
4001	// In this state we read dcache.
4002	{
4003	size_t way;
4004	size_t set;
4005	size_t word;
4006	int state;
4007
4008	#ifdef INSTRUMENTATION
4009	m_cpt_dcache_dir_read++;
4010	#endif
4011	r_dcache.read_dir(r_dcache_save_paddr.read(),
4012	&state,
4013	&way,
4014	&set,
4015	&word);
4016
4017	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
4018	{
4019	r_dcache_xtn_way = way;
4020	r_dcache_xtn_set = set;
4021	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
4022	}
4023	else // miss : nothing to do
4024	{
4025	r_dcache_fsm = DCACHE_IDLE;
4026	m_drsp.valid = true;
4027	}
4028
4029	#if DEBUG_DCACHE
4030	if (m_debug_dcache_fsm)
4031	{
4032	std::cout << " <PROC " << name()
4033	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
4034	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
4035	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
4036	<< " / SET = " << set
4037	<< " / WAY = " << way << std::endl;
4038	}
4039	#endif
4040	break;
4041	}
4042	////////////////////////////
4043	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
4044	// Blocked if previous cleanup not completed
4045	// Test if itlb or dtlb inval is required
4046	{
4047	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
4048	{
4049	size_t way = r_dcache_xtn_way.read();
4050	size_t set = r_dcache_xtn_set.read();
4051	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4052
4053	#ifdef INSTRUMENTATION
4054	m_cpt_dcache_dir_write++;
4055	#endif
4056	r_dcache.write_dir(way,
4057	set,
4058	CACHE_SLOT_STATE_ZOMBI);
4059
4060	// request cleanup
4061	r_dcache_cc_send_req = true;
4062	r_dcache_cc_send_nline = nline;
4063	r_dcache_cc_send_way = way;
4064	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4065
4066	// possible itlb & dtlb invalidate
4067	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4068	{
4069	r_dcache_tlb_inval_line = nline;
4070	r_dcache_tlb_inval_set = 0;
4071	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
4072	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4073	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4074	}
4075	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4076	{
4077	r_itlb.reset();
4078	r_dtlb.reset();
4079	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4080	r_dcache_fsm = DCACHE_IDLE;
4081	m_drsp.valid = true;
4082	}
4083	else
4084	{
4085	r_dcache_fsm = DCACHE_IDLE;
4086	m_drsp.valid = true;
4087	}
4088
4089	#if DEBUG_DCACHE
4090	if (m_debug_dcache_fsm)
4091	{
4092	std::cout << " <PROC " << name()
4093	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
4094	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
4095	}
4096	#endif
4097	}
4098	break;
4099	}
4100	//////////////////////////////
4101	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
4102	{
4103	r_dcache_fsm = DCACHE_IDLE;
4104	m_drsp.valid = true;
4105	break;
4106	}
4107	////////////////////////
4108	case DCACHE_MISS_SELECT: // Try to select a slot in associative set,
4109	// Waiting in this state if no slot available.
4110	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
4111	// we send the cleanup request in this state.
4112	// If not, a r_icache_cleanup_victim_req flip-flop is
4113	// utilized for saving this cleanup request, and it will be sent later
4114	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
4115	// The r_icache_miss_clack flip-flop is set
4116	// when a cleanup is required
4117	{
4118	if (m_dreq.valid) m_cost_data_miss_frz++;
4119
4120	// coherence clack request (from DSPIN CLACK)
4121	if (r_dcache_clack_req.read())
4122	{
4123	r_dcache_fsm = DCACHE_CC_CHECK;
4124	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4125	break;
4126	}
4127
4128	// coherence request (from CC_RECEIVE FSM)
4129	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4130	{
4131	r_dcache_fsm = DCACHE_CC_CHECK;
4132	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4133	break;
4134	}
4135
4136	bool found = false;
4137	bool cleanup = false;
4138	size_t way = 0;
4139	size_t set = 0;
4140	paddr_t victim = 0;
4141
4142	#ifdef INSTRUMENTATION
4143	m_cpt_dcache_dir_read++;
4144	#endif
4145	r_dcache.read_select(r_dcache_save_paddr.read(),
4146	&victim,
4147	&way,
4148	&set,
4149	&found,
4150	&cleanup);
4151
4152	if (not found)
4153	{
4154	break;
4155	}
4156	else
4157	{
4158	r_dcache_miss_way = way;
4159	r_dcache_miss_set = set;
4160
4161	// reset to 0 the miss watchdog timer
4162	r_dcache_miss_wdt = 0;
4163
4164	if (cleanup)
4165	{
4166	if (not r_dcache_cc_send_req.read())
4167	{
4168	r_dcache_cc_send_req = true;
4169	r_dcache_cc_send_nline = victim;
4170	r_dcache_cc_send_way = way;
4171	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4172
4173	}
4174	else
4175	{
4176	r_dcache_cleanup_victim_req = true;
4177	r_dcache_cleanup_victim_nline = victim;
4178	}
4179
4180	r_dcache_miss_clack = true;
4181	r_dcache_fsm = DCACHE_MISS_CLEAN;
4182	}
4183	else
4184	{
4185	r_dcache_fsm = DCACHE_MISS_WAIT;
4186	}
4187
4188	#if DEBUG_DCACHE
4189	if (m_debug_dcache_fsm)
4190	{
4191	std::cout << " <PROC " << name()
4192	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
4193	<< " / WAY = " << way
4194	<< " / SET = " << set
4195	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
4196	if (cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
4197	else std::cout << std::endl;
4198	}
4199	#endif
4200	} // end found
4201	break;
4202	}
4203	///////////////////////
4204	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
4205	// and possibly request itlb or dtlb invalidate
4206	{
4207	if (m_dreq.valid) m_cost_data_miss_frz++;
4208
4209	size_t way = r_dcache_miss_way.read();
4210	size_t set = r_dcache_miss_set.read();
4211
4212	#ifdef INSTRUMENTATION
4213	m_cpt_dcache_dir_read++;
4214	#endif
4215	r_dcache.write_dir(way,
4216	set,
4217	CACHE_SLOT_STATE_ZOMBI);
4218	#if DEBUG_DCACHE
4219	if (m_debug_dcache_fsm)
4220	{
4221	std::cout << " <PROC " << name()
4222	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
4223	<< " / way = " << way
4224	<< " / set = " << set << std::endl;
4225	}
4226	#endif
4227	// if selective itlb & dtlb invalidate are required
4228	// the miss response is not handled before invalidate completed
4229	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4230	{
4231	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4232
4233	if (not r_dcache_cleanup_victim_req.read())
4234	r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
4235	else
4236	r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
4237
4238	r_dcache_tlb_inval_set = 0;
4239	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
4240	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4241	}
4242	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4243	{
4244	r_itlb.reset();
4245	r_dtlb.reset();
4246	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4247	r_dcache_fsm = DCACHE_MISS_WAIT;
4248	}
4249	else
4250	{
4251	r_dcache_fsm = DCACHE_MISS_WAIT;
4252	}
4253	break;
4254	}
4255	//////////////////////
4256	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
4257	// This state is in charge of error signaling
4258	// There is 5 types of error depending on the requester
4259	{
4260	if (m_dreq.valid) m_cost_data_miss_frz++;
4261
4262	// send cleanup victim request
4263	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4264	{
4265	r_dcache_cc_send_req = true;
4266	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4267	r_dcache_cc_send_way = r_dcache_miss_way;
4268	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4269	r_dcache_cleanup_victim_req = false;
4270	}
4271
4272	// coherence clack request (from DSPIN CLACK)
4273	if (r_dcache_clack_req.read())
4274	{
4275	r_dcache_fsm = DCACHE_CC_CHECK;
4276	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4277	break;
4278	}
4279
4280	// coherence request (from CC_RECEIVE FSM)
4281	if (r_cc_receive_dcache_req.read() and
4282	not r_dcache_cc_send_req.read() and
4283	not r_dcache_cleanup_victim_req.read())
4284	{
4285	r_dcache_fsm = DCACHE_CC_CHECK;
4286	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4287	break;
4288	}
4289
4290	// increment MISS watchdog timer for black-hole detection
4291	r_dcache_miss_wdt = r_dcache_miss_wdt.read() + 1;
4292	if (r_dcache_miss_wdt.read() == r_dcache_miss_wdt_max.read()) {
4293	r_mmu_detr = MMU_READ_DATA_TIMEOUT;
4294	r_mmu_dbvar = r_dcache_save_vaddr.read();
4295	m_drsp.valid = true;
4296	m_drsp.error = true;
4297	r_dcache_fsm = DCACHE_IDLE;
4298	break;
4299	}
4300
4301	if (r_vci_rsp_data_error.read()) // bus error
4302	{
4303	switch (r_dcache_miss_type.read())
4304	{
4305	case PROC_MISS:
4306	{
4307	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4308	r_mmu_dbvar = r_dcache_save_vaddr.read();
4309	m_drsp.valid = true;
4310	m_drsp.error = true;
4311	r_dcache_fsm = DCACHE_IDLE;
4312	break;
4313	}
4314	case PTE1_MISS:
4315	{
4316	if (r_dcache_tlb_ins.read())
4317	{
4318	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
4319	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4320	r_icache_tlb_miss_req = false;
4321	r_icache_tlb_rsp_error = true;
4322	}
4323	else
4324	{
4325	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4326	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4327	m_drsp.valid = true;
4328	m_drsp.error = true;
4329	}
4330	r_dcache_fsm = DCACHE_IDLE;
4331	break;
4332	}
4333	case PTE2_MISS:
4334	{
4335	if (r_dcache_tlb_ins.read())
4336	{
4337	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4338	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4339	r_icache_tlb_miss_req = false;
4340	r_icache_tlb_rsp_error = true;
4341	}
4342	else
4343	{
4344	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4345	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4346	m_drsp.valid = true;
4347	m_drsp.error = true;
4348	}
4349	r_dcache_fsm = DCACHE_IDLE;
4350	break;
4351	}
4352	} // end switch type
4353	r_vci_rsp_data_error = false;
4354	}
4355	else if (r_vci_rsp_fifo_dcache.rok()) // valid response available
4356	{
4357	r_dcache_miss_word = 0;
4358	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4359	}
4360	break;
4361	}
4362	//////////////////////////
4363	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4364	{
4365	if (m_dreq.valid) m_cost_data_miss_frz++;
4366
4367	if (r_vci_rsp_fifo_dcache.rok()) // one word available
4368	{
4369	#ifdef INSTRUMENTATION
4370	m_cpt_dcache_data_write++;
4371	#endif
4372	r_dcache.write(r_dcache_miss_way.read(),
4373	r_dcache_miss_set.read(),
4374	r_dcache_miss_word.read(),
4375	r_vci_rsp_fifo_dcache.read());
4376	#if DEBUG_DCACHE
4377	if (m_debug_dcache_fsm)
4378	{
4379	std::cout << " <PROC " << name()
4380	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4381	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4382	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4383	<< " / SET = " << r_dcache_miss_set.read()
4384	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4385	}
4386	#endif
4387	vci_rsp_fifo_dcache_get = true;
4388	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4389
4390	if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word
4391	{
4392	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4393	}
4394	}
4395	break;
4396	}
4397	//////////////////////////
4398	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4399	// and the cleanup ack has not been received,
4400	// as indicated by the r_dcache_miss clack.
4401	// - If no matching coherence request (r_dcache_inval_miss)
4402	// switch directory slot to VALID state.
4403	// - If matching coherence request, switch directory slot
4404	// to ZOMBI state, and send a cleanup request.
4405	{
4406	if (m_dreq.valid) m_cost_data_miss_frz++;
4407
4408	// send cleanup victim request
4409	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4410	{
4411	r_dcache_cc_send_req = true;
4412	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4413	r_dcache_cc_send_way = r_dcache_miss_way;
4414	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4415	r_dcache_cleanup_victim_req = false;
4416	}
4417
4418	// coherence clack request (from DSPIN CLACK)
4419	if (r_dcache_clack_req.read())
4420	{
4421	r_dcache_fsm = DCACHE_CC_CHECK;
4422	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4423	break;
4424	}
4425
4426	// coherence request (from CC_RECEIVE FSM)
4427	if (r_cc_receive_dcache_req.read() and
4428	not r_dcache_cc_send_req.read() and
4429	not r_dcache_cleanup_victim_req.read())
4430	{
4431	r_dcache_fsm = DCACHE_CC_CHECK;
4432	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4433	break;
4434	}
4435
4436	if (not r_dcache_miss_clack.read()) // waiting cleanup acknowledge
4437	{
4438	if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup
4439	{
4440	if (not r_dcache_cc_send_req.read()) // blocked until previous request sent
4441	{
4442	r_dcache_miss_inval = false;
4443	// request cleanup
4444	r_dcache_cc_send_req = true;
4445	r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4446	r_dcache_cc_send_way = r_dcache_miss_way.read();
4447	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4448
4449	#ifdef INSTRUMENTATION
4450	m_cpt_dcache_dir_write++;
4451	#endif
4452	r_dcache.write_dir( r_dcache_save_paddr.read(),
4453	r_dcache_miss_way.read(),
4454	r_dcache_miss_set.read(),
4455	CACHE_SLOT_STATE_ZOMBI );
4456	#if DEBUG_DCACHE
4457	if (m_debug_dcache_fsm)
4458	std::cout << " <PROC " << name()
4459	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4460	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4461	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4462	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4463	#endif
4464	}
4465	else
4466	break;
4467	}
4468	else // switch slot to VALID state
4469	{
4470
4471	#ifdef INSTRUMENTATION
4472	m_cpt_dcache_dir_write++;
4473	#endif
4474	r_dcache.write_dir(r_dcache_save_paddr.read(),
4475	r_dcache_miss_way.read(),
4476	r_dcache_miss_set.read(),
4477	CACHE_SLOT_STATE_VALID);
4478
4479	#if DEBUG_DCACHE
4480	if (m_debug_dcache_fsm)
4481	std::cout << " <PROC " << name()
4482	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4483	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4484	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4485	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4486	#endif
4487	// reset directory extension
4488	size_t way = r_dcache_miss_way.read();
4489	size_t set = r_dcache_miss_set.read();
4490	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4491	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4492	}
4493	if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4494	else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4495	else r_dcache_fsm = DCACHE_IDLE;
4496	}
4497	break;
4498	}
4499	/////////////////////
4500	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write
4501	{
4502	// coherence clack request (from DSPIN CLACK)
4503	if (r_dcache_clack_req.read())
4504	{
4505	r_dcache_fsm = DCACHE_CC_CHECK;
4506	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4507	break;
4508	}
4509
4510	// coherence request (from CC_RECEIVE FSM)
4511	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4512	{
4513	r_dcache_fsm = DCACHE_CC_CHECK;
4514	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4515	break;
4516	}
4517
4518	if (r_vci_rsp_data_error.read()) // bus error
4519	{
4520	if (r_dcache_vci_unc_write.read())
4521	r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
4522	else
4523	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4524
4525	r_mmu_dbvar = m_dreq.addr;
4526	r_vci_rsp_data_error = false;
4527	m_drsp.error = true;
4528	m_drsp.valid = true;
4529	r_dcache_fsm = DCACHE_IDLE;
4530	break;
4531	}
4532	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4533	{
4534	// consume data
4535	vci_rsp_fifo_dcache_get = true;
4536	r_dcache_fsm = DCACHE_IDLE;
4537
4538	// acknowledge the processor request if it has not been modified
4539	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4540	{
4541	m_drsp.valid = true;
4542	m_drsp.error = false;
4543	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4544	}
4545	}
4546	break;
4547	}
4548	/////////////////////
4549	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4550	{
4551	// coherence clack request (from DSPIN CLACK)
4552	if (r_dcache_clack_req.read())
4553	{
4554	r_dcache_fsm = DCACHE_CC_CHECK;
4555	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4556	break;
4557	}
4558
4559	// coherence request (from CC_RECEIVE FSM)
4560	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4561	{
4562	r_dcache_fsm = DCACHE_CC_CHECK;
4563	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4564	break;
4565	}
4566
4567	if (r_vci_rsp_data_error.read()) // bus error
4568	{
4569	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4570	r_mmu_dbvar = m_dreq.addr;
4571	r_vci_rsp_data_error = false;
4572	m_drsp.error = true;
4573	m_drsp.valid = true;
4574	r_dcache_fsm = DCACHE_IDLE;
4575	break;
4576	}
4577	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4578	{
4579	// consume data
4580	vci_rsp_fifo_dcache_get = true;
4581
4582	if (r_dcache_ll_rsp_count.read() == 0) // first flit
4583	{
4584	// set key value in llsc reservation buffer
4585	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4586	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
4587	}
4588	else // last flit
4589	{
4590	// acknowledge the processor request if it has not been modified
4591	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4592	{
4593	m_drsp.valid = true;
4594	m_drsp.error = false;
4595	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4596	}
4597	r_dcache_fsm = DCACHE_IDLE;
4598	}
4599	}
4600	break;
4601	}
4602	////////////////////
4603	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4604	{
4605	// coherence clack request (from DSPIN CLACK)
4606	if (r_dcache_clack_req.read())
4607	{
4608	r_dcache_fsm = DCACHE_CC_CHECK;
4609	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4610	break;
4611	}
4612
4613	// coherence request (from CC_RECEIVE FSM)
4614	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4615	{
4616	r_dcache_fsm = DCACHE_CC_CHECK;
4617	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4618	break;
4619	}
4620
4621	if (r_vci_rsp_data_error.read()) // bus error
4622	{
4623	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4624	r_mmu_dbvar = m_dreq.addr;
4625	r_vci_rsp_data_error = false;
4626	m_drsp.error = true;
4627	m_drsp.valid = true;
4628	r_dcache_fsm = DCACHE_IDLE;
4629	break;
4630	}
4631	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4632	{
4633	// consume response
4634	vci_rsp_fifo_dcache_get = true;
4635	m_drsp.valid = true;
4636	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4637	r_dcache_fsm = DCACHE_IDLE;
4638	}
4639	break;
4640	}
4641	//////////////////////////
4642	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4643	// before handling a processor WRITE or SC request
4644	// Input argument is r_dcache_dirty_paddr
4645	// In this first state, we get PTE value in dcache
4646	// and post a CAS request to CMD FSM
4647	{
4648	// get PTE in dcache
4649	uint32_t pte;
4650	size_t way;
4651	size_t set;
4652	size_t word; // unused
4653	int state;
4654
4655	#ifdef INSTRUMENTATION
4656	m_cpt_dcache_data_read++;
4657	m_cpt_dcache_dir_read++;
4658	#endif
4659	r_dcache.read(r_dcache_dirty_paddr.read(),
4660	&pte,
4661	&way,
4662	&set,
4663	&word,
4664	&state);
4665
4666	assert( (state == CACHE_SLOT_STATE_VALID) and
4667	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4668
4669	// request CAS transaction to CMD_FSM
4670	r_dcache_dirty_way = way;
4671	r_dcache_dirty_set = set;
4672
4673	// check llsc reservation buffer
4674	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read())
4675	r_dcache_llsc_valid = false;
4676
4677	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4678	r_dcache_vci_cas_req = true;
4679	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4680	r_dcache_vci_cas_old = pte;
4681	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4682	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4683
4684	#if DEBUG_DCACHE
4685	if (m_debug_dcache_fsm)
4686	{
4687	std::cout << " <PROC " << name()
4688	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4689	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4690	<< " / PTE_VALUE = " << pte << std::dec
4691	<< " / SET = " << set
4692	<< " / WAY = " << way << std::endl;
4693	}
4694	#endif
4695	break;
4696	}
4697	///////////////////////
4698	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4699	// and return to IDLE state when response is received.
4700	// we don't care if the CAS is a failure:
4701	// - if the CAS is a success, the coherence mechanism
4702	// updates the local copy.
4703	// - if the CAS is a failure, we just retry the write.
4704	{
4705	// coherence clack request (from DSPIN CLACK)
4706	if (r_dcache_clack_req.read())
4707	{
4708	r_dcache_fsm = DCACHE_CC_CHECK;
4709	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4710	break;
4711	}
4712
4713	// coherence request (from CC_RECEIVE FSM)
4714	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4715	{
4716	r_dcache_fsm = DCACHE_CC_CHECK;
4717	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4718	break;
4719	}
4720
4721	if (r_vci_rsp_data_error.read()) // bus error
4722	{
4723	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4724	std::cout << "This should not happen in this state" << std::endl;
4725	exit(0);
4726	}
4727	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4728	{
4729	vci_rsp_fifo_dcache_get = true;
4730	r_dcache_fsm = DCACHE_IDLE;
4731
4732	#if DEBUG_DCACHE
4733	if (m_debug_dcache_fsm)
4734	{
4735	std::cout << " <PROC " << name()
4736	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4737	}
4738	#endif
4739	}
4740	break;
4741	}
4742	/////////////////////
4743	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4744	// handling coherence requests for DCACHE.
4745	// If there is a matching pending miss on the modified cache
4746	// line this is signaled in the r_dcache_miss inval flip-flop.
4747	// If the updated (or invalidated) cache line has copies in TLBs
4748	// these TLB copies are invalidated.
4749	// The return state is defined in r_dcache_fsm_cc_save
4750	{
4751	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4752	paddr_t mask = ~((m_dcache_words << 2) - 1);
4753
4754	// CLACK handler
4755	// We switch the directory slot to EMPTY state and reset
4756	// r_dcache_miss_clack if the cleanup ack is matching a pending miss.
4757	if (r_dcache_clack_req.read())
4758	{
4759	if (m_dreq.valid ) m_cost_data_miss_frz++;
4760
4761	#ifdef INSTRUMENTATION
4762	m_cpt_dcache_dir_write++;
4763	#endif
4764	r_dcache.write_dir(0,
4765	r_dcache_clack_way.read(),
4766	r_dcache_clack_set.read(),
4767	CACHE_SLOT_STATE_EMPTY);
4768
4769	if ((r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
4770	(r_dcache_miss_way.read() == r_dcache_clack_way.read()))
4771	{
4772	r_dcache_miss_clack = false;
4773	}
4774
4775	r_dcache_clack_req = false;
4776
4777	// return to cc_save state
4778	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4779
4780	#if DEBUG_DCACHE
4781	if (m_debug_dcache_fsm)
4782	{
4783	std::cout << " <PROC " << name()
4784	<< " DCACHE_CC_CHECK> CLACK for PADDR " << paddr
4785	<< " Switch slot to EMPTY state : "
4786	<< " set = " << r_dcache_clack_set.read()
4787	<< " / way = " << r_dcache_clack_way.read() << std::endl;
4788	}
4789	#endif
4790	break;
4791	}
4792
4793	assert(not r_dcache_cc_send_req.read() and
4794	"CC_SEND must be available in DCACHE_CC_CHECK");
4795
4796	// Match between MISS address and CC address
4797	if (r_cc_receive_dcache_req.read() and
4798	((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4799	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4800	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4801	((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
4802	{
4803	// signaling matching
4804	r_dcache_miss_inval = true;
4805
4806	// in case of update, go to CC_UPDT
4807	// JUST TO POP THE FIFO
4808	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4809	{
4810	r_dcache_fsm = DCACHE_CC_UPDT;
4811	r_dcache_cc_word = r_cc_receive_word_idx.read();
4812
4813	// just pop the fifo , don't write in icache
4814	r_dcache_cc_need_write = false;
4815	}
4816	// the request is dealt with
4817	else
4818	{
4819	r_cc_receive_dcache_req = false;
4820	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4821	}
4822
4823	#if DEBUG_DCACHE
4824	if (m_debug_dcache_fsm)
4825	{
4826	std::cout << " <PROC " << name()
4827	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4828	<< " PADDR = " << std::hex << paddr << std::endl;
4829	}
4830	#endif
4831	}
4832
4833	// CC request handler
4834
4835	int state = 0;
4836	size_t way = 0;
4837	size_t set = 0;
4838	size_t word = 0;
4839
4840	#ifdef INSTRUMENTATION
4841	m_cpt_dcache_dir_read++;
4842	#endif
4843	r_dcache.read_dir(paddr,
4844	&state,
4845	&way,
4846	&set,
4847	&word); // unused
4848
4849	r_dcache_cc_way = way;
4850	r_dcache_cc_set = set;
4851
4852	if (state == CACHE_SLOT_STATE_VALID) // hit
4853	{
4854	// need to update the cache state
4855	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
4856	{
4857	r_dcache_cc_need_write = true;
4858	r_dcache_fsm = DCACHE_CC_UPDT;
4859	r_dcache_cc_word = r_cc_receive_word_idx.read();
4860	}
4861	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
4862	{
4863	r_dcache_fsm = DCACHE_CC_INVAL;
4864	}
4865	}
4866	else // miss
4867	{
4868	// multicast acknowledgement required in case of update
4869	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4870	{
4871	r_dcache_fsm = DCACHE_CC_UPDT;
4872	r_dcache_cc_word = r_cc_receive_word_idx.read();
4873
4874	// just pop the fifo , don't write in icache
4875	r_dcache_cc_need_write = false;
4876	}
4877	else // No response needed
4878	{
4879	r_cc_receive_dcache_req = false;
4880	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4881	}
4882	}
4883
4884	#if DEBUG_DCACHE
4885	if (m_debug_dcache_fsm)
4886	{
4887	std::cout << " <PROC " << name()
4888	<< " DCACHE_CC_CHECK> Coherence request received:"
4889	<< " PADDR = " << std::hex << paddr
4890	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
4891	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
4892	}
4893	#endif
4894
4895	break;
4896	}
4897	/////////////////////
4898	case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
4899	// CLEANUP after possible invalidation of copies in
4900	// TLBs
4901	{
4902	size_t way = r_dcache_cc_way.read();
4903	size_t set = r_dcache_cc_set.read();
4904
4905	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
4906	{
4907	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4908	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4909	r_dcache_tlb_inval_set = 0;
4910	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4911	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4912	break;
4913	}
4914
4915	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
4916	{
4917	r_itlb.reset();
4918	r_dtlb.reset();
4919	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4920
4921	#if DEBUG_DCACHE
4922	if (m_debug_dcache_fsm)
4923	{
4924	std::cout << " <PROC " << name()
4925	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
4926	}
4927	#endif
4928	}
4929
4930	assert(not r_dcache_cc_send_req.read() &&
4931	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
4932	"must not be set");
4933
4934	// Switch slot state to ZOMBI and send CLEANUP command
4935	r_dcache.write_dir(way,
4936	set,
4937	CACHE_SLOT_STATE_ZOMBI);
4938
4939	// coherence request completed
4940	r_cc_receive_dcache_req = false;
4941	r_dcache_cc_send_req = true;
4942	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
4943	r_dcache_cc_send_way = r_dcache_cc_way.read();
4944	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4945	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4946
4947	#if DEBUG_DCACHE
4948	if (m_debug_dcache_fsm)
4949	{
4950	std::cout << " <PROC " << name()
4951	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
4952	<< " / WAY = " << way
4953	<< " / SET = " << set << std::endl;
4954	}
4955	#endif
4956	break;
4957	}
4958	///////////////////
4959	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
4960	// after possible invalidation of copies in TLBs
4961	{
4962	size_t word = r_dcache_cc_word.read();
4963	size_t way = r_dcache_cc_way.read();
4964	size_t set = r_dcache_cc_set.read();
4965
4966	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
4967	{
4968	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4969	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
4970	r_dcache_tlb_inval_set = 0;
4971	r_dcache_fsm_scan_save = r_dcache_fsm.read();
4972	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4973
4974	break;
4975	}
4976
4977	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
4978	{
4979	r_itlb.reset();
4980	r_dtlb.reset();
4981	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4982
4983	#if DEBUG_DCACHE
4984	if (m_debug_dcache_fsm)
4985	{
4986	std::cout << " <PROC " << name()
4987	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
4988	}
4989	#endif
4990	}
4991
4992	assert (not r_dcache_cc_send_req.read() &&
4993	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
4994	"must not be set");
4995
4996	if (not r_cc_receive_updt_fifo_be.rok()) break;
4997
4998	if (r_dcache_cc_need_write.read())
4999	{
5000
5001	#ifdef INSTRUMENTATION
5002	m_cpt_dcache_data_write++;
5003	#endif
5004	r_dcache.write(way,
5005	set,
5006	word,
5007	r_cc_receive_updt_fifo_data.read(),
5008	r_cc_receive_updt_fifo_be.read());
5009
5010	r_dcache_cc_word = word + 1;
5011
5012	#if DEBUG_DCACHE
5013	if (m_debug_dcache_fsm)
5014	{
5015	std::cout << " <PROC " << name()
5016	<< " DCACHE_CC_UPDT> Write one word" << std::dec
5017	<< " / WAY = " << way
5018	<< " / SET = " << set
5019	<< " / WORD = " << word
5020	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
5021	}
5022	#endif
5023	}
5024
5025	if (r_cc_receive_updt_fifo_eop.read()) // last word
5026	{
5027	// no need to write in the cache anymore
5028	r_dcache_cc_need_write = false;
5029
5030	// coherence request completed
5031	r_cc_receive_dcache_req = false;
5032
5033	// request multicast acknowledgement
5034	r_dcache_cc_send_req = true;
5035	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
5036	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
5037	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
5038	r_dcache_fsm = r_dcache_fsm_cc_save.read();
5039	}
5040
5041	//consume fifo if not eop
5042	cc_receive_updt_fifo_get = true;
5043
5044	break;
5045	}
5046	///////////////////////////
5047	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
5048	// It makes assumption: m_itlb_sets == m_dtlb_sets
5049	// All ways are handled in parallel.
5050	// We enter this state when a DCACHE line is modified,
5051	// and there is a copy in itlb or dtlb.
5052	// It can be caused by:
5053	// - a coherence inval or updt transaction,
5054	// - a line inval caused by a cache miss
5055	// - a processor XTN inval request,
5056	// - a WRITE hit,
5057	// - a Dirty bit update
5058	// Input arguments are:
5059	// - r_dcache_tlb_inval_line
5060	// - r_dcache_tlb_inval_set
5061	// - r_dcache_fsm_scan_save
5062	{
5063	paddr_t line = r_dcache_tlb_inval_line.read();
5064	size_t set = r_dcache_tlb_inval_set.read();
5065	size_t way;
5066	bool ok;
5067
5068	for (way = 0; way < m_itlb_ways; way++)
5069	{
5070	ok = r_itlb.inval(line, way, set);
5071
5072	#if DEBUG_DCACHE
5073	if (m_debug_dcache_fsm and ok)
5074	{
5075	std::cout << " <PROC " << name()
5076	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
5077	<< " line = " << line << std::dec
5078	<< " / set = " << set
5079	<< " / way = " << way << std::endl;
5080	}
5081	#endif
5082	}
5083
5084	for (way = 0; way < m_dtlb_ways; way++)
5085	{
5086	ok = r_dtlb.inval( line, way, set);
5087
5088	#if DEBUG_DCACHE
5089	if (m_debug_dcache_fsm and ok)
5090	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
5091	<< " Invalidate DTLB entry" << std::hex
5092	<< " / line = " << line << std::dec
5093	<< " / set = " << set
5094	<< " / way = " << way << std::endl;
5095	#endif
5096	}
5097
5098	// return to the calling state when TLB inval completed
5099	if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1))
5100	{
5101	r_dcache_fsm = r_dcache_fsm_scan_save.read();
5102	}
5103	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
5104	break;
5105	}
5106	} // end switch r_dcache_fsm
5107
5108	///////////////// wbuf update ///////////////////////////////////////////////////////
5109	r_wbuf.update();
5110
5111	///////////////// llsc update ///////////////////////////////////////////////////////
5112	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
5113	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
5114
5115	//////////////// test processor frozen //////////////////////////////////////////////
5116	// The simulation exit if the number of consecutive frozen cycles
5117	// is larger than the m_max_frozen_cycles (constructor parameter)
5118	if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid))
5119	{
5120	m_cpt_frz_cycles++; // used for instrumentation
5121	m_cpt_stop_simulation++; // used for debug
5122	if (m_cpt_stop_simulation > m_max_frozen_cycles)
5123	{
5124	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
5125	<< " stop at cycle " << m_cpt_total_cycles << std::endl
5126	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
5127	<< std::endl;
5128	r_iss.dump();
5129	exit(1);
5130	}
5131	}
5132	else
5133	{
5134	m_cpt_stop_simulation = 0;
5135	}
5136
5137	/////////// execute one iss cycle /////////////////////////////////
5138	{
5139	uint32_t it = 0;
5140	for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) if (p_irq[i].read()) it \|= (1 << i);
5141	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
5142	}
5143
5144	////////////////////////////////////////////////////////////////////////////
5145	// The VCI_CMD FSM controls the following ressources:
5146	// - r_vci_cmd_fsm
5147	// - r_vci_cmd_min
5148	// - r_vci_cmd_max
5149	// - r_vci_cmd_cpt
5150	// - r_vci_cmd_imiss_prio
5151	// - wbuf (reset)
5152	// - r_icache_miss_req (reset)
5153	// - r_icache_unc_req (reset)
5154	// - r_dcache_vci_miss_req (reset)
5155	// - r_dcache_vci_unc_req (reset)
5156	// - r_dcache_vci_ll_req (reset)
5157	// - r_dcache_vci_sc_req (reset in case of local sc fail)
5158	// - r_dcache_vci_cas_req (reset)
5159	//
5160	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
5161	// There are 8 request types, with the following priorities :
5162	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
5163	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
5164	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
5165	// 4 - Instruction Uncachable : r_icache_unc_req
5166	// 5 - Data Write : r_wbuf.rok()
5167	// 6 - Data Linked Load : r_dcache_vci_ll_req
5168	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
5169	// 8 - Compare And Swap : r_dcache_vci_cas_req
5170	//
5171	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
5172	// and the VCI_RSP_FSM are fully desynchronized.
5173	//
5174	// VCI formats:
5175	// According to the VCI advanced specification, all read requests packets
5176	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
5177	// are one word packets.
5178	// For write burst packets, all words are in the same cache line,
5179	// and addresses must be contiguous (the BE field is 0 in case of "holes").
5180	// The sc command packet implements actually a compare-and-swap mechanism
5181	// and the packet contains two flits.
5182	////////////////////////////////////////////////////////////////////////////////////
5183
5184
5185	switch (r_vci_cmd_fsm.read())
5186	{
5187	//////////////
5188	case CMD_IDLE:
5189	{
5190	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
5191	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
5192	// to check a possible pending write on the same cache line.
5193	// As there is only one possible access per cycle to write buffer, we implement
5194	// a round-robin priority between DCACHE and ICACHE for this access,
5195	// using the r_vci_cmd_imiss_prio flip-flop.
5196
5197	size_t wbuf_min;
5198	size_t wbuf_max;
5199
5200	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
5201	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5202
5203	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
5204	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5205
5206	bool dcache_sc_req = r_dcache_vci_sc_req.read() and
5207	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5208
5209	bool dcache_cas_req = r_dcache_vci_cas_req.read() and
5210	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5211
5212	bool icache_miss_req = r_icache_miss_req.read() and
5213	(not (r_dcache_vci_miss_req.read() or
5214	r_dcache_vci_ll_req.read() or
5215	r_dcache_vci_cas_req.read() or
5216	r_dcache_vci_sc_req.read()) or
5217	r_vci_cmd_imiss_prio.read());
5218
5219	// 1 - Data unc write
5220	if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
5221	{
5222	r_vci_cmd_fsm = CMD_DATA_UNC_WRITE;
5223	r_dcache_vci_unc_req = false;
5224	}
5225	// 2 data read miss
5226	else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5227	{
5228	r_vci_cmd_fsm = CMD_DATA_MISS;
5229	r_dcache_vci_miss_req = false;
5230	r_vci_cmd_imiss_prio = true;
5231	}
5232	// 3 - Data Read Uncachable
5233	else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read())
5234	{
5235	r_vci_cmd_fsm = CMD_DATA_UNC_READ;
5236	r_dcache_vci_unc_req = false;
5237	}
5238	// 4 - Data Linked Load
5239	else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5240	{
5241	r_vci_cmd_fsm = CMD_DATA_LL;
5242	r_dcache_vci_ll_req = false;
5243	r_vci_cmd_imiss_prio = true;
5244	}
5245	// 5 - Instruction Miss
5246	else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()))
5247	{
5248	r_vci_cmd_fsm = CMD_INS_MISS;
5249	r_icache_miss_req = false;
5250	r_vci_cmd_imiss_prio = false;
5251	}
5252	// 6 - Instruction Uncachable
5253	else if (r_icache_unc_req.read())
5254	{
5255	r_vci_cmd_fsm = CMD_INS_UNC;
5256	r_icache_unc_req = false;
5257	}
5258	// 7 - Data Write
5259	else if (r_wbuf.rok(&wbuf_min, &wbuf_max))
5260	{
5261	r_vci_cmd_fsm = CMD_DATA_WRITE;
5262	r_vci_cmd_cpt = wbuf_min;
5263	r_vci_cmd_min = wbuf_min;
5264	r_vci_cmd_max = wbuf_max;
5265	}
5266	// 8 - Data Store Conditionnal
5267	else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5268	{
5269	r_vci_cmd_fsm = CMD_DATA_SC;
5270	r_dcache_vci_sc_req = false;
5271	r_vci_cmd_imiss_prio = true;
5272	r_vci_cmd_cpt = 0;
5273	}
5274	// 9 - Compare And Swap
5275	else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5276	{
5277	r_vci_cmd_fsm = CMD_DATA_CAS;
5278	r_dcache_vci_cas_req = false;
5279	r_vci_cmd_imiss_prio = true;
5280	r_vci_cmd_cpt = 0;
5281	}
5282
5283	#if DEBUG_CMD
5284	if (m_debug_cmd_fsm )
5285	{
5286	std::cout << " <PROC " << name() << " CMD_IDLE>"
5287	<< " / dmiss_req = " << dcache_miss_req
5288	<< " / imiss_req = " << icache_miss_req
5289	<< std::endl;
5290	}
5291	#endif
5292	break;
5293	}
5294	////////////////////
5295	case CMD_DATA_WRITE:
5296	{
5297	if (p_vci.cmdack.read())
5298	{
5299	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5300	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5301	{
5302	r_vci_cmd_fsm = CMD_IDLE;
5303	r_wbuf.sent();
5304	}
5305	}
5306	break;
5307	}
5308	/////////////////
5309	case CMD_DATA_SC:
5310	case CMD_DATA_CAS:
5311	{
5312	// The CAS and SC VCI commands contain two flits
5313	if (p_vci.cmdack.read())
5314	{
5315	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5316	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5317	}
5318	break;
5319	}
5320	//////////////////
5321	case CMD_INS_MISS:
5322	case CMD_INS_UNC:
5323	case CMD_DATA_MISS:
5324	case CMD_DATA_UNC_READ:
5325	case CMD_DATA_UNC_WRITE:
5326	case CMD_DATA_LL:
5327	{
5328	// all read VCI commands contain one single flit
5329	if (p_vci.cmdack.read()) {
5330	r_vci_cmd_fsm = CMD_IDLE;
5331	}
5332	break;
5333	}
5334
5335	} // end switch r_vci_cmd_fsm
5336
5337	//////////////////////////////////////////////////////////////////////////
5338	// The VCI_RSP FSM controls the following ressources:
5339	// - r_vci_rsp_fsm:
5340	// - r_vci_rsp_fifo_icache (push)
5341	// - r_vci_rsp_fifo_dcache (push)
5342	// - r_vci_rsp_data_error (set)
5343	// - r_vci_rsp_ins_error (set)
5344	// - r_vci_rsp_cpt
5345	// - r_dcache_vci_sc_req (reset when SC response recieved)
5346	//
5347	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5348	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5349	// to identify the transactions.
5350	//
5351	// VCI vormat:
5352	// This component checks the response packet length and accepts only
5353	// single word packets for write response packets.
5354	//
5355	// Error handling:
5356	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5357	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5358	// flip_flop and the error is signaled by the DCACHE FSM.
5359	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5360	// flip_flop and the error is signaled by the ICACHE FSM.
5361	// In case of Cleanup Error, the simulation stops with an error message...
5362	//////////////////////////////////////////////////////////////////////////
5363
5364	switch (r_vci_rsp_fsm.read())
5365	{
5366	//////////////
5367	case RSP_IDLE:
5368	{
5369	if (p_vci.rspval.read())
5370	{
5371	r_vci_rsp_cpt = 0;
5372
5373	if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC)
5374	{
5375	r_vci_rsp_fsm = RSP_DATA_UNC;
5376	}
5377	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS)
5378	{
5379	r_vci_rsp_fsm = RSP_DATA_MISS;
5380	}
5381	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC)
5382	{
5383	r_vci_rsp_fsm = RSP_INS_UNC;
5384	}
5385	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS)
5386	{
5387	r_vci_rsp_fsm = RSP_INS_MISS;
5388	}
5389	else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE)
5390	{
5391	r_vci_rsp_fsm = RSP_DATA_WRITE;
5392	}
5393	else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS)
5394	{
5395	r_vci_rsp_fsm = RSP_DATA_UNC;
5396	}
5397	else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL)
5398	{
5399	r_vci_rsp_fsm = RSP_DATA_LL;
5400	}
5401	else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC)
5402	{
5403	r_vci_rsp_fsm = RSP_DATA_UNC;
5404	}
5405	else
5406	{
5407	assert(false and "Unexpected VCI response");
5408	}
5409	}
5410	break;
5411	}
5412	//////////////////
5413	case RSP_INS_MISS:
5414	{
5415	if (p_vci.rspval.read())
5416	{
5417	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5418	{
5419	r_vci_rsp_ins_error = true;
5420	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5421	}
5422	else // no error reported
5423	{
5424	if (r_vci_rsp_fifo_icache.wok())
5425	{
5426	if (r_vci_rsp_cpt.read() >= m_icache_words)
5427	{
5428	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5429	<< " VCI response packet too long "
5430	<< " for instruction miss" << std::endl;
5431	exit(0);
5432	}
5433	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5434	vci_rsp_fifo_icache_put = true,
5435	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5436	if (p_vci.reop.read())
5437	{
5438	if (r_vci_rsp_cpt.read() != (m_icache_words - 1))
5439	{
5440	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5441	<< " VCI response packet too short"
5442	<< " for instruction miss" << std::endl;
5443	exit(0);
5444	}
5445	r_vci_rsp_fsm = RSP_IDLE;
5446	}
5447	}
5448	}
5449	}
5450	break;
5451	}
5452	/////////////////
5453	case RSP_INS_UNC:
5454	{
5455	if (p_vci.rspval.read())
5456	{
5457	assert(p_vci.reop.read() and
5458	"illegal VCI response packet for uncachable instruction");
5459
5460	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5461	{
5462	r_vci_rsp_ins_error = true;
5463	r_vci_rsp_fsm = RSP_IDLE;
5464	}
5465	else // no error reported
5466	{
5467	if (r_vci_rsp_fifo_icache.wok())
5468	{
5469	vci_rsp_fifo_icache_put = true;
5470	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5471	r_vci_rsp_fsm = RSP_IDLE;
5472	}
5473	}
5474	}
5475	break;
5476	}
5477	///////////////////
5478	case RSP_DATA_MISS:
5479	{
5480	if (p_vci.rspval.read())
5481	{
5482	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5483	{
5484	r_vci_rsp_data_error = true;
5485	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5486	}
5487	else // no error reported
5488	{
5489	if (r_vci_rsp_fifo_dcache.wok())
5490	{
5491	assert((r_vci_rsp_cpt.read() < m_dcache_words) and
5492	"The VCI response packet for data miss is too long");
5493
5494	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5495	vci_rsp_fifo_dcache_put = true,
5496	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5497	if (p_vci.reop.read())
5498	{
5499	assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5500	"The VCI response packet for data miss is too short");
5501
5502	r_vci_rsp_fsm = RSP_IDLE;
5503	}
5504	}
5505	}
5506	}
5507	break;
5508	}
5509	//////////////////
5510	case RSP_DATA_UNC:
5511	{
5512	if (p_vci.rspval.read())
5513	{
5514	assert(p_vci.reop.read() and
5515	"illegal VCI response packet for uncachable read data");
5516
5517	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5518	{
5519	r_vci_rsp_data_error = true;
5520	r_vci_rsp_fsm = RSP_IDLE;
5521	}
5522	else // no error reported
5523	{
5524	if (r_vci_rsp_fifo_dcache.wok())
5525	{
5526	vci_rsp_fifo_dcache_put = true;
5527	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5528	r_vci_rsp_fsm = RSP_IDLE;
5529	}
5530	}
5531	}
5532	break;
5533	}
5534	/////////////////
5535	case RSP_DATA_LL:
5536	{
5537	if (p_vci.rspval.read())
5538	{
5539	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5540	{
5541	r_vci_rsp_data_error = true;
5542	r_vci_rsp_fsm = RSP_IDLE;
5543	break;
5544	}
5545	if (r_vci_rsp_cpt.read() == 0) //first flit
5546	{
5547	if (r_vci_rsp_fifo_dcache.wok())
5548	{
5549	assert(!p_vci.reop.read() &&
5550	"illegal VCI response packet for LL");
5551	vci_rsp_fifo_dcache_put = true;
5552	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5553	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5554	}
5555	break;
5556	}
5557	else // last flit
5558	{
5559	if (r_vci_rsp_fifo_dcache.wok())
5560	{
5561	assert(p_vci.reop.read() &&
5562	"illegal VCI response packet for LL");
5563	vci_rsp_fifo_dcache_put = true;
5564	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5565	r_vci_rsp_fsm = RSP_IDLE;
5566	}
5567	break;
5568	}
5569	}
5570	break;
5571	}
5572	////////////////////
5573	case RSP_DATA_WRITE:
5574	{
5575	if (p_vci.rspval.read())
5576	{
5577	assert(p_vci.reop.read() and
5578	"a VCI response packet must contain one flit for a write transaction");
5579
5580	r_vci_rsp_fsm = RSP_IDLE;
5581	uint32_t wbuf_index = p_vci.rtrdid.read();
5582	r_wbuf.completed(wbuf_index);
5583	if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr();
5584	}
5585	break;
5586	}
5587	} // end switch r_vci_rsp_fsm
5588
5589	/////////////////////////////////////////////////////////////////////////////////////
5590	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5591	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5592	// and ICACHE FSM) that are served with a round-robin priority.
5593	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5594	// soon as the request has been sent.
5595	/////////////////////////////////////////////////////////////////////////////////////
5596	switch (r_cc_send_fsm.read())
5597	{
5598	///////////////////////////
5599	case CC_SEND_IDLE:
5600	{
5601	///////////////////////////////////////////////////////
5602	// handling round robin between icache and dcache : //
5603	// we first check for the last client and listen for //
5604	// a request of the other, then update the client //
5605	// r_cc_send_last_client : 0 dcache / 1 icache
5606	///////////////////////////////////////////////////////
5607	bool update_last_client = r_cc_send_last_client.read();
5608	if (r_cc_send_last_client.read() == 0) // last client was dcache
5609	{
5610	if (r_icache_cc_send_req.read()) // request from icache
5611	update_last_client = 1; // update last client to icache
5612	}
5613	else // last client was icache
5614	{
5615	if (r_dcache_cc_send_req.read()) // request from dcache
5616	update_last_client = 0; // update last client to dcache
5617	}
5618	r_cc_send_last_client = update_last_client;
5619
5620	// if there is an actual request
5621	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5622	{
5623	// the new client is dcache and has a cleanup request
5624	if ((update_last_client == 0) and
5625	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5626	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5627	// the new client is dcache and has a multi acknowledgement request
5628	else if ((update_last_client == 0) and
5629	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5630	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5631	// the new client is icache and has a cleanup request
5632	else if ((update_last_client == 1) and
5633	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5634	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5635	// the new client is icache and has a multi acknowledgement request
5636	else if ((update_last_client == 1) and
5637	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5638	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5639	}
5640	break;
5641	}
5642	///////////////////////////
5643	case CC_SEND_CLEANUP_1:
5644	{
5645	// wait for the first flit to be consumed
5646	if (p_dspin_p2m.read.read())
5647	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5648
5649	break;
5650	}
5651	///////////////////////////
5652	case CC_SEND_CLEANUP_2:
5653	{
5654	// wait for the second flit to be consumed
5655	if (p_dspin_p2m.read.read())
5656	{
5657	if (r_cc_send_last_client.read() == 0) // dcache active request
5658	r_dcache_cc_send_req = false; // reset dcache request
5659	else // icache active request
5660	r_icache_cc_send_req = false; // reset icache request
5661
5662	// go back to idle state
5663	r_cc_send_fsm = CC_SEND_IDLE;
5664	}
5665	break;
5666	}
5667	///////////////////////////
5668	case CC_SEND_MULTI_ACK:
5669	{
5670	// wait for the flit to be consumed
5671	if (p_dspin_p2m.read.read())
5672	{
5673	if (r_cc_send_last_client.read() == 0) // dcache active request
5674	r_dcache_cc_send_req = false; // reset dcache request
5675	else // icache active request
5676	r_icache_cc_send_req = false; // reset icache request
5677	// go back to idle state
5678	r_cc_send_fsm = CC_SEND_IDLE;
5679	}
5680	break;
5681	}
5682	} // end switch CC_SEND FSM
5683
5684	///////////////////////////////////////////////////////////////////////////////
5685	// CC_RECEIVE FSM
5686	// This FSM receive all coherence packets on a DSPIN40 port.
5687	// There is 5 packet types:
5688	// - CC_DATA_INVAL : DCACHE invalidate request
5689	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5690	// - CC_INST_INVAL : ICACHE invalidate request
5691	// - CC_INST_UPDT : ICACHE update request (multi-words)
5692	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5693	//////////////////////////////////////////////////////////////////////////////
5694	switch (r_cc_receive_fsm.read())
5695	{
5696	/////////////////////
5697	case CC_RECEIVE_IDLE:
5698	{
5699	// a coherence request has arrived
5700	if (p_dspin_m2p.write.read())
5701	{
5702	// initialize dspin received data
5703	uint64_t receive_data = p_dspin_m2p.data.read();
5704	// initialize coherence packet type
5705	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5706	DspinDhccpParam::M2P_TYPE);
5707	// test for a broadcast
5708	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
5709	{
5710	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5711	}
5712	// test for a multi updt
5713	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA)
5714	{
5715	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
5716	}
5717	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
5718	{
5719	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
5720	}
5721	// test for a multi inval
5722	else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
5723	{
5724	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
5725	}
5726	else
5727	{
5728	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
5729	}
5730	}
5731	break;
5732	}
5733	///////////////////////////////
5734	case CC_RECEIVE_BRDCAST_HEADER:
5735	{
5736	// no actual data in the HEADER, just skip to second flit
5737	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5738	break;
5739	}
5740	//////////////////////////////
5741	case CC_RECEIVE_BRDCAST_NLINE:
5742	{
5743	// initialize dspin received data
5744	uint64_t receive_data = p_dspin_m2p.data.read();
5745	// wait for both dcache and icache to take the request
5746	// TODO maybe we need to wait for both only to leave the state, but
5747	// not to actually post a request to an available cache => need a
5748	// flip_flop to check that ?
5749	if (not (r_cc_receive_icache_req.read()) and
5750	not (r_cc_receive_dcache_req.read()) and
5751	(p_dspin_m2p.write.read()))
5752	{
5753	// request dcache to handle the BROADCAST
5754	r_cc_receive_dcache_req = true;
5755	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5756	DspinDhccpParam::BROADCAST_NLINE);
5757	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5758	// request icache to handle the BROADCAST
5759	r_cc_receive_icache_req = true;
5760	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5761	DspinDhccpParam::BROADCAST_NLINE);
5762	r_cc_receive_icache_type = CC_TYPE_INVAL;
5763	// get back to idle state
5764	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5765	break;
5766	}
5767	// keep waiting for the caches to accept the request
5768	break;
5769	}
5770	/////////////////////////////
5771	case CC_RECEIVE_DATA_INVAL_HEADER:
5772	{
5773	// sample updt tab index in the HEADER, then skip to second flit
5774	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
5775	break;
5776	}
5777	/////////////////////////////
5778	case CC_RECEIVE_INS_INVAL_HEADER:
5779	{
5780	// sample updt tab index in the HEADER, then skip to second flit
5781	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
5782	break;
5783	}
5784	////////////////////////////
5785	case CC_RECEIVE_DATA_INVAL_NLINE:
5786	{
5787	// sample nline in the second flit
5788	uint64_t receive_data = p_dspin_m2p.data.read();
5789	// for data INVAL, wait for dcache to take the request
5790	if (p_dspin_m2p.write.read() and
5791	not r_cc_receive_dcache_req.read())
5792	{
5793	// request dcache to handle the INVAL
5794	r_cc_receive_dcache_req = true;
5795	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5796	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5797	// get back to idle state
5798	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5799	break;
5800	}
5801	break;
5802	}
5803	//////////////////////////////
5804	case CC_RECEIVE_INS_INVAL_NLINE:
5805	{
5806	// sample nline in the second flit
5807	uint64_t receive_data = p_dspin_m2p.data.read();
5808	// for ins INVAL, wait for icache to take the request
5809	if (p_dspin_m2p.write.read() and
5810	not r_cc_receive_icache_req.read())
5811	{
5812	// request icache to handle the INVAL
5813	r_cc_receive_icache_req = true;
5814	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
5815	r_cc_receive_icache_type = CC_TYPE_INVAL;
5816	// get back to idle state
5817	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5818	break;
5819	}
5820	break;
5821	}
5822	////////////////////////////
5823	case CC_RECEIVE_DATA_UPDT_HEADER:
5824	{
5825	// sample updt tab index in the HEADER, than skip to second flit
5826	uint64_t receive_data = p_dspin_m2p.data.read();
5827	// for data INVAL, wait for dcache to take the request and fifo to
5828	// be empty
5829	if (not r_cc_receive_dcache_req.read())
5830	{
5831	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5832	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
5833	break;
5834	}
5835	break;
5836	}
5837	////////////////////////////
5838	case CC_RECEIVE_INS_UPDT_HEADER:
5839	{
5840	// sample updt tab index in the HEADER, than skip to second flit
5841	uint64_t receive_data = p_dspin_m2p.data.read();
5842	// for ins INVAL, wait for icache to take the request and fifo to be
5843	// empty
5844	if (not r_cc_receive_icache_req.read())
5845	{
5846	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
5847	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
5848	break;
5849	}
5850	// keep waiting for the correct cache to accept the request
5851	break;
5852	}
5853	///////////////////////////
5854	case CC_RECEIVE_DATA_UPDT_NLINE:
5855	{
5856	// sample nline and word index in the second flit
5857	uint64_t receive_data = p_dspin_m2p.data.read();
5858	// for data INVAL, wait for dcache to take the request and fifo to
5859	// be empty
5860	if (r_cc_receive_updt_fifo_be.empty() and
5861	p_dspin_m2p.write.read())
5862	{
5863	r_cc_receive_dcache_req = true;
5864	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5865	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5866	r_cc_receive_dcache_type = CC_TYPE_UPDT;
5867	// get back to idle state
5868	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
5869	break;
5870	}
5871	break;
5872	}
5873	////////////////////////////
5874	case CC_RECEIVE_INS_UPDT_NLINE:
5875	{
5876	// sample nline and word index in the second flit
5877	uint64_t receive_data = p_dspin_m2p.data.read();
5878	// for ins INVAL, wait for icache to take the request and fifo to be
5879	// empty
5880	if (r_cc_receive_updt_fifo_be.empty() and
5881	p_dspin_m2p.write.read())
5882	{
5883	r_cc_receive_icache_req = true;
5884	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
5885	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
5886	r_cc_receive_icache_type = CC_TYPE_UPDT;
5887	// get back to idle state
5888	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
5889	break;
5890	}
5891	break;
5892	}
5893	//////////////////////////
5894	case CC_RECEIVE_DATA_UPDT_DATA:
5895	{
5896	// wait for the fifo
5897	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5898	{
5899	uint64_t receive_data = p_dspin_m2p.data.read();
5900	bool receive_eop = p_dspin_m2p.eop.read();
5901	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5902	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5903	cc_receive_updt_fifo_eop = receive_eop;
5904	cc_receive_updt_fifo_put = true;
5905	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5906	}
5907	break;
5908	}
5909	//////////////////////////
5910	case CC_RECEIVE_INS_UPDT_DATA:
5911	{
5912	// wait for the fifo
5913	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
5914	{
5915	uint64_t receive_data = p_dspin_m2p.data.read();
5916	bool receive_eop = p_dspin_m2p.eop.read();
5917	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
5918	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
5919	cc_receive_updt_fifo_eop = receive_eop;
5920	cc_receive_updt_fifo_put = true;
5921	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
5922	}
5923	break;
5924	}
5925
5926	} // end switch CC_RECEIVE FSM
5927
5928	///////////////// DSPIN CLACK interface ///////////////
5929
5930	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5931	DspinDhccpParam::CLACK_TYPE);
5932
5933	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5934	DspinDhccpParam::CLACK_WAY);
5935
5936	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
5937	DspinDhccpParam::CLACK_SET);
5938
5939	bool dspin_clack_get = false;
5940	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
5941	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
5942
5943	if (r_dspin_clack_req.read())
5944	{
5945	// CLACK DATA: Send request to DCACHE FSM
5946	if (dcache_clack_request and not r_dcache_clack_req.read())
5947	{
5948	r_dcache_clack_req = true;
5949	r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1);
5950	r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1);
5951	dspin_clack_get = true;
5952	}
5953
5954	// CLACK INST: Send request to ICACHE FSM
5955	else if (icache_clack_request and not r_icache_clack_req.read())
5956	{
5957	r_icache_clack_req = true;
5958	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
5959	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
5960	dspin_clack_get = true;
5961	}
5962	}
5963	else
5964	{
5965	dspin_clack_get = true;
5966	}
5967
5968	if (dspin_clack_get)
5969	{
5970	r_dspin_clack_req = p_dspin_clack.write.read();
5971	r_dspin_clack_flit = p_dspin_clack.data.read();
5972	}
5973
5974	///////////////// Response FIFOs update //////////////////////
5975	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
5976	vci_rsp_fifo_icache_put,
5977	vci_rsp_fifo_icache_data);
5978
5979	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
5980	vci_rsp_fifo_dcache_put,
5981	vci_rsp_fifo_dcache_data);
5982
5983	///////////////// updt FIFO update //////////////////////
5984	//TODO check this
5985	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
5986	cc_receive_updt_fifo_put,
5987	cc_receive_updt_fifo_be);
5988	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
5989	cc_receive_updt_fifo_put,
5990	cc_receive_updt_fifo_data);
5991	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
5992	cc_receive_updt_fifo_put,
5993	cc_receive_updt_fifo_eop);
5994
5995	} // end transition()
5996
5997	///////////////////////
5998	tmpl(void)::genMoore()
5999	///////////////////////
6000	{
6001
6002	// VCI initiator command on the direct network
6003	// it depends on the CMD FSM state
6004
6005	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
6006	(r_vci_cmd_fsm.read() == CMD_DATA_SC);
6007
6008	p_vci.pktid = 0;
6009	p_vci.srcid = m_srcid;
6010	p_vci.cons = is_sc_or_cas;
6011	p_vci.contig = not is_sc_or_cas;
6012	p_vci.wrap = false;
6013	p_vci.clen = 0;
6014	p_vci.cfixed = false;
6015
6016	if (m_monitor_ok) {
6017	if (p_vci.cmdack.read() == true and p_vci.cmdval == true) {
6018	if (((p_vci.address.read()) >= m_monitor_base) and
6019	((p_vci.address.read()) < m_monitor_base + m_monitor_length)) {
6020	std::cout << "CC_VCACHE Monitor " << name() << std::hex
6021	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
6022	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
6023	<< " : address = " << p_vci.address.read()
6024	<< " / be = " << p_vci.be.read();
6025	if (p_vci.cmd.read() == vci_param::CMD_WRITE ) {
6026	std::cout << " / data = " << p_vci.wdata.read();
6027	}
6028	std::cout << std::dec << std::endl;
6029	}
6030	}
6031	}
6032
6033	switch (r_vci_cmd_fsm.read()) {
6034
6035	case CMD_IDLE:
6036	p_vci.cmdval = false;
6037	p_vci.address = 0;
6038	p_vci.wdata = 0;
6039	p_vci.be = 0;
6040	p_vci.trdid = 0;
6041	p_vci.pktid = 0;
6042	p_vci.plen = 0;
6043	p_vci.cmd = vci_param::CMD_NOP;
6044	p_vci.eop = false;
6045	break;
6046
6047	case CMD_INS_MISS:
6048	p_vci.cmdval = true;
6049	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
6050	p_vci.wdata = 0;
6051	p_vci.be = 0xF;
6052	p_vci.trdid = 0;
6053	p_vci.pktid = TYPE_READ_INS_MISS;
6054	p_vci.plen = m_icache_words << 2;
6055	p_vci.cmd = vci_param::CMD_READ;
6056	p_vci.eop = true;
6057	break;
6058
6059	case CMD_INS_UNC:
6060	p_vci.cmdval = true;
6061	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
6062	p_vci.wdata = 0;
6063	p_vci.be = 0xF;
6064	p_vci.trdid = 0;
6065	p_vci.pktid = TYPE_READ_INS_UNC;
6066	p_vci.plen = 4;
6067	p_vci.cmd = vci_param::CMD_READ;
6068	p_vci.eop = true;
6069	break;
6070
6071	case CMD_DATA_MISS:
6072	p_vci.cmdval = true;
6073	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
6074	p_vci.wdata = 0;
6075	p_vci.be = 0xF;
6076	p_vci.trdid = 0;
6077	p_vci.pktid = TYPE_READ_DATA_MISS;
6078	p_vci.plen = m_dcache_words << 2;
6079	p_vci.cmd = vci_param::CMD_READ;
6080	p_vci.eop = true;
6081	break;
6082
6083	case CMD_DATA_UNC_READ:
6084	p_vci.cmdval = true;
6085	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6086	p_vci.wdata = 0;
6087	p_vci.be = r_dcache_vci_unc_be.read();
6088	p_vci.trdid = 0;
6089	p_vci.pktid = TYPE_DATA_UNC;
6090	p_vci.plen = 4;
6091	p_vci.cmd = vci_param::CMD_READ;
6092	p_vci.eop = true;
6093	break;
6094
6095	case CMD_DATA_UNC_WRITE:
6096	p_vci.cmdval = true;
6097	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6098	p_vci.wdata = r_dcache_vci_wdata.read();
6099	p_vci.be = r_dcache_vci_unc_be.read();
6100	p_vci.trdid = 0;
6101	p_vci.pktid = TYPE_DATA_UNC;
6102	p_vci.plen = 4;
6103	p_vci.cmd = vci_param::CMD_WRITE;
6104	p_vci.eop = true;
6105	break;
6106
6107	case CMD_DATA_WRITE:
6108	p_vci.cmdval = true;
6109	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
6110	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
6111	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
6112	p_vci.trdid = r_wbuf.getIndex();
6113	p_vci.pktid = TYPE_WRITE;
6114	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
6115	p_vci.cmd = vci_param::CMD_WRITE;
6116	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
6117	break;
6118
6119	case CMD_DATA_LL:
6120	p_vci.cmdval = true;
6121	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6122	p_vci.wdata = 0;
6123	p_vci.be = 0xF;
6124	p_vci.trdid = 0;
6125	p_vci.pktid = TYPE_LL;
6126	p_vci.plen = 8;
6127	p_vci.cmd = vci_param::CMD_LOCKED_READ;
6128	p_vci.eop = true;
6129	break;
6130
6131	case CMD_DATA_SC:
6132	p_vci.cmdval = true;
6133	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6134	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
6135	else p_vci.wdata = r_dcache_vci_sc_data.read();
6136	p_vci.be = 0xF;
6137	p_vci.trdid = 0;
6138	p_vci.pktid = TYPE_SC;
6139	p_vci.plen = 8;
6140	p_vci.cmd = vci_param::CMD_NOP;
6141	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6142	break;
6143
6144	case CMD_DATA_CAS:
6145	p_vci.cmdval = true;
6146	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6147	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read();
6148	else p_vci.wdata = r_dcache_vci_cas_new.read();
6149	p_vci.be = 0xF;
6150	p_vci.trdid = 0;
6151	p_vci.pktid = TYPE_CAS;
6152	p_vci.plen = 8;
6153	p_vci.cmd = vci_param::CMD_NOP;
6154	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6155	break;
6156	} // end switch r_vci_cmd_fsm
6157
6158	// VCI initiator response on the direct network
6159	// it depends on the VCI_RSP FSM
6160
6161	switch (r_vci_rsp_fsm.read())
6162	{
6163	case RSP_DATA_WRITE : p_vci.rspack = true; break;
6164	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6165	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6166	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6167	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6168	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6169	case RSP_IDLE : p_vci.rspack = false; break;
6170	} // end switch r_vci_rsp_fsm
6171
6172
6173	// Send coherence packets on DSPIN P2M
6174	// it depends on the CC_SEND FSM
6175
6176	uint64_t dspin_send_data = 0;
6177	switch (r_cc_send_fsm.read())
6178	{
6179	//////////////////
6180	case CC_SEND_IDLE:
6181	{
6182	p_dspin_p2m.write = false;
6183	break;
6184	}
6185	///////////////////////
6186	case CC_SEND_CLEANUP_1:
6187	{
6188	// initialize dspin send data
6189	DspinDhccpParam::dspin_set(dspin_send_data,
6190	m_cc_global_id,
6191	DspinDhccpParam::CLEANUP_SRCID);
6192	DspinDhccpParam::dspin_set(dspin_send_data,
6193	0,
6194	DspinDhccpParam::P2M_BC);
6195
6196	if (r_cc_send_last_client.read() == 0) // dcache active request
6197	{
6198	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6199	>> (m_nline_width - m_x_width - m_y_width)
6200	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6201
6202	DspinDhccpParam::dspin_set(dspin_send_data,
6203	dest,
6204	DspinDhccpParam::CLEANUP_DEST);
6205
6206	DspinDhccpParam::dspin_set(dspin_send_data,
6207	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
6208	DspinDhccpParam::CLEANUP_NLINE_MSB);
6209
6210	DspinDhccpParam::dspin_set(dspin_send_data,
6211	r_dcache_cc_send_way.read(),
6212	DspinDhccpParam::CLEANUP_WAY_INDEX);
6213
6214	DspinDhccpParam::dspin_set(dspin_send_data,
6215	DspinDhccpParam::TYPE_CLEANUP_DATA,
6216	DspinDhccpParam::P2M_TYPE);
6217	}
6218	else // icache active request
6219	{
6220	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6221	>> (m_nline_width - m_x_width - m_y_width)
6222	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6223
6224	DspinDhccpParam::dspin_set(dspin_send_data,
6225	dest,
6226	DspinDhccpParam::CLEANUP_DEST);
6227
6228	DspinDhccpParam::dspin_set(dspin_send_data,
6229	(r_icache_cc_send_nline.read() & 0x300000000ULL) >> 32,
6230	DspinDhccpParam::CLEANUP_NLINE_MSB);
6231
6232	DspinDhccpParam::dspin_set(dspin_send_data,
6233	r_icache_cc_send_way.read(),
6234	DspinDhccpParam::CLEANUP_WAY_INDEX);
6235
6236	DspinDhccpParam::dspin_set(dspin_send_data,
6237	DspinDhccpParam::TYPE_CLEANUP_INST,
6238	DspinDhccpParam::P2M_TYPE);
6239	}
6240	// send flit
6241	p_dspin_p2m.data = dspin_send_data;
6242	p_dspin_p2m.write = true;
6243	p_dspin_p2m.eop = false;
6244	break;
6245	}
6246	///////////////////////
6247	case CC_SEND_CLEANUP_2:
6248	{
6249	// initialize dspin send data
6250
6251	if (r_cc_send_last_client.read() == 0) // dcache active request
6252	{
6253	DspinDhccpParam::dspin_set(dspin_send_data,
6254	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
6255	DspinDhccpParam::CLEANUP_NLINE_LSB);
6256	}
6257	else // icache active request
6258	{
6259	DspinDhccpParam::dspin_set(dspin_send_data,
6260	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
6261	DspinDhccpParam::CLEANUP_NLINE_LSB);
6262	}
6263	// send flit
6264	p_dspin_p2m.data = dspin_send_data;
6265	p_dspin_p2m.write = true;
6266	p_dspin_p2m.eop = true;
6267	break;
6268	}
6269	///////////////////////
6270	case CC_SEND_MULTI_ACK:
6271	{
6272	// initialize dspin send data
6273	DspinDhccpParam::dspin_set(dspin_send_data,
6274	0,
6275	DspinDhccpParam::P2M_BC);
6276	DspinDhccpParam::dspin_set(dspin_send_data,
6277	DspinDhccpParam::TYPE_MULTI_ACK,
6278	DspinDhccpParam::P2M_TYPE);
6279
6280	if (r_cc_send_last_client.read() == 0) // dcache active request
6281	{
6282	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6283	>> (m_nline_width - m_x_width - m_y_width)
6284	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6285
6286	DspinDhccpParam::dspin_set(dspin_send_data,
6287	dest,
6288	DspinDhccpParam::MULTI_ACK_DEST);
6289
6290	DspinDhccpParam::dspin_set(dspin_send_data,
6291	r_dcache_cc_send_updt_tab_idx.read(),
6292	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6293	}
6294	else // icache active request
6295	{
6296	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6297	>> (m_nline_width - m_x_width - m_y_width)
6298	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6299
6300
6301	DspinDhccpParam::dspin_set(dspin_send_data,
6302	dest,
6303	DspinDhccpParam::MULTI_ACK_DEST);
6304
6305	DspinDhccpParam::dspin_set(dspin_send_data,
6306	r_icache_cc_send_updt_tab_idx.read(),
6307	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6308	}
6309	// send flit
6310	p_dspin_p2m.data = dspin_send_data;
6311	p_dspin_p2m.write = true;
6312	p_dspin_p2m.eop = true;
6313
6314	break;
6315	}
6316	} // end switch CC_SEND FSM
6317
6318	// Receive coherence packets
6319	// It depends on the CC_RECEIVE FSM
6320	switch (r_cc_receive_fsm.read())
6321	{
6322	/////////////////////
6323	case CC_RECEIVE_IDLE:
6324	{
6325	p_dspin_m2p.read = false;
6326	break;
6327	}
6328	///////////////////////////////
6329	case CC_RECEIVE_BRDCAST_HEADER:
6330	{
6331	p_dspin_m2p.read = true;
6332	break;
6333	}
6334	//////////////////////////////
6335	case CC_RECEIVE_BRDCAST_NLINE:
6336	{
6337	// TODO maybe we need to wait for both only to leave the state, but
6338	// not to actually post a request to an available cache => need a
6339	// flip_flop to check that ?
6340	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6341	p_dspin_m2p.read = true;
6342	else
6343	p_dspin_m2p.read = false;
6344	break;
6345	}
6346	/////////////////////////////
6347	case CC_RECEIVE_DATA_INVAL_HEADER:
6348	case CC_RECEIVE_INS_INVAL_HEADER:
6349	{
6350	p_dspin_m2p.read = true;
6351	break;
6352	}
6353	////////////////////////////
6354	case CC_RECEIVE_DATA_INVAL_NLINE:
6355	{
6356	p_dspin_m2p.read = not r_cc_receive_dcache_req.read();
6357	break;
6358	}
6359	case CC_RECEIVE_INS_INVAL_NLINE:
6360	{
6361	p_dspin_m2p.read = not r_cc_receive_icache_req.read();
6362	break;
6363	}
6364	///////////////////////////
6365	case CC_RECEIVE_DATA_UPDT_HEADER:
6366	{
6367	if (not r_cc_receive_dcache_req.read())
6368	p_dspin_m2p.read = true;
6369	else
6370	p_dspin_m2p.read = false;
6371	break;
6372	}
6373	////////////////////////////
6374	case CC_RECEIVE_INS_UPDT_HEADER:
6375	{
6376	if (not r_cc_receive_icache_req.read())
6377	p_dspin_m2p.read = true;
6378	else
6379	p_dspin_m2p.read = false;
6380	break;
6381	}
6382	///////////////////////////
6383	case CC_RECEIVE_DATA_UPDT_NLINE:
6384	case CC_RECEIVE_INS_UPDT_NLINE:
6385	{
6386	if (r_cc_receive_updt_fifo_be.empty())
6387	p_dspin_m2p.read = true;
6388	else
6389	p_dspin_m2p.read = false;
6390	break;
6391	}
6392	///////////////////////////
6393	case CC_RECEIVE_DATA_UPDT_DATA:
6394	case CC_RECEIVE_INS_UPDT_DATA:
6395	{
6396	if (r_cc_receive_updt_fifo_be.wok())
6397	p_dspin_m2p.read = true;
6398	else
6399	p_dspin_m2p.read = false;
6400	break;
6401	}
6402	} // end switch CC_RECEIVE FSM
6403
6404
6405	int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6406	DspinDhccpParam::CLACK_TYPE);
6407
6408	bool dspin_clack_get = false;
6409	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
6410	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
6411
6412	if (r_dspin_clack_req.read())
6413	{
6414	// CLACK DATA: wait if pending request to DCACHE FSM
6415	if (dcache_clack_request and not r_dcache_clack_req.read())
6416	{
6417	dspin_clack_get = true;
6418	}
6419
6420	// CLACK INST: wait if pending request to ICACHE FSM
6421	else if (icache_clack_request and not r_icache_clack_req.read())
6422	{
6423	dspin_clack_get = true;
6424	}
6425	}
6426	else
6427	{
6428	dspin_clack_get = true;
6429	}
6430
6431	p_dspin_clack.read = dspin_clack_get;
6432	} // end genMoore
6433
6434	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
6435	// This version of monitor print both Read and Write request
6436	{
6437	m_monitor_ok = true;
6438	m_monitor_base = base;
6439	m_monitor_length = length;
6440	}
6441
6442	tmpl(void)::stop_monitor()
6443	{
6444	m_monitor_ok = false;
6445	}
6446
6447	}}
6448
6449	// Local Variables:
6450	// tab-width: 4
6451	// c-basic-offset: 4
6452	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6453	// indent-tabs-mode: nil
6454	// End:
6455
6456	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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Project-Id-Version: Trac 0.12
Report-Msgid-Bugs-To: trac-dev@googlegroups.com
POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
Last-Translator: Jeroen Ruigrok van der Werven <asmodai@in-nomine.org>
Language: en_US
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