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source: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp @ 988

Last change on this file since 988 was 988, checked in by cfuguet, 9 years ago
reconf: introducing a mechanism to deactivate the watchdog timer on the vci_cc_vcache_wrapper component.
File size: 256.0 KB

Line
1	/* -- c++ --
2	* File : vci_cc_vcache_wrapper.cpp
3	* Copyright (c) UPMC, Lip6, SoC
4	* Authors : Alain GREINER, Yang GAO
5	*
6	* SOCLIB_LGPL_HEADER_BEGIN
7	*
8	* This file is part of SoCLib, GNU LGPLv2.1.
9	*
10	* SoCLib is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU Lesser General Public License as published
12	* by the Free Software Foundation; version 2.1 of the License.
13	*
14	* SoCLib is distributed in the hope that it will be useful, but
15	* WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17	* Lesser General Public License for more details.
18	*
19	* You should have received a copy of the GNU Lesser General Public
20	* License along with SoCLib; if not, write to the Free Software
21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22	* 02110-1301 USA
23	*
24	* SOCLIB_LGPL_HEADER_END
25	*
26	* Maintainers: cesar.fuguet-tortolero@lip6.fr
27	* alexandre.joannou@lip6.fr
28	*/
29
30	#include <cassert>
31	#include <signal.h>
32	#include <limits>
33
34	#include "arithmetics.h"
35	#include "../include/vci_cc_vcache_wrapper.h"
36
37	#define DEBUG_DCACHE 1
38	#define DEBUG_ICACHE 1
39	#define DEBUG_CMD 0
40
41	namespace soclib {
42	namespace caba {
43
44	namespace {
45	const char * icache_fsm_state_str[] = {
46	"ICACHE_IDLE",
47
48	"ICACHE_XTN_TLB_FLUSH",
49	"ICACHE_XTN_CACHE_FLUSH",
50	"ICACHE_XTN_CACHE_FLUSH_GO",
51	"ICACHE_XTN_TLB_INVAL",
52	"ICACHE_XTN_CACHE_INVAL_VA",
53	"ICACHE_XTN_CACHE_INVAL_PA",
54	"ICACHE_XTN_CACHE_INVAL_GO",
55
56	"ICACHE_TLB_WAIT",
57
58	"ICACHE_MISS_SELECT",
59	"ICACHE_MISS_CLEAN",
60	"ICACHE_MISS_WAIT",
61	"ICACHE_MISS_DATA_UPDT",
62	"ICACHE_MISS_DIR_UPDT",
63
64	"ICACHE_UNC_WAIT",
65
66	"ICACHE_CC_CHECK",
67	"ICACHE_CC_UPDT",
68	"ICACHE_CC_INVAL",
69	};
70
71	const char * dcache_fsm_state_str[] = {
72	"DCACHE_IDLE",
73
74	"DCACHE_TLB_MISS",
75	"DCACHE_TLB_PTE1_GET",
76	"DCACHE_TLB_PTE1_SELECT",
77	"DCACHE_TLB_PTE1_UPDT",
78	"DCACHE_TLB_PTE2_GET",
79	"DCACHE_TLB_PTE2_SELECT",
80	"DCACHE_TLB_PTE2_UPDT",
81	"DCACHE_TLB_LR_UPDT",
82	"DCACHE_TLB_LR_WAIT",
83	"DCACHE_TLB_RETURN",
84
85	"DCACHE_XTN_SWITCH",
86	"DCACHE_XTN_SYNC",
87	"DCACHE_XTN_IC_INVAL_VA",
88	"DCACHE_XTN_IC_FLUSH",
89	"DCACHE_XTN_IC_INVAL_PA",
90	"DCACHE_XTN_IC_PADDR_EXT",
91	"DCACHE_XTN_IT_INVAL",
92	"DCACHE_XTN_DC_FLUSH",
93	"DCACHE_XTN_DC_FLUSH_GO",
94	"DCACHE_XTN_DC_INVAL_VA",
95	"DCACHE_XTN_DC_INVAL_PA",
96	"DCACHE_XTN_DC_INVAL_END",
97	"DCACHE_XTN_DC_INVAL_GO",
98	"DCACHE_XTN_DT_INVAL",
99	"DCACHE_XTN_CC_TEST",
100
101	"DCACHE_DIRTY_GET_PTE",
102	"DCACHE_DIRTY_WAIT",
103
104	"DCACHE_MISS_SELECT",
105	"DCACHE_MISS_CLEAN",
106	"DCACHE_MISS_WAIT",
107	"DCACHE_MISS_DATA_UPDT",
108	"DCACHE_MISS_DIR_UPDT",
109
110	"DCACHE_UNC_WAIT",
111	"DCACHE_LL_WAIT",
112	"DCACHE_SC_WAIT",
113
114	"DCACHE_CC_CHECK",
115	"DCACHE_CC_UPDT",
116	"DCACHE_CC_INVAL",
117
118	"DCACHE_INVAL_TLB_SCAN",
119	};
120
121	const char * cmd_fsm_state_str[] = {
122	"CMD_IDLE",
123	"CMD_INS_MISS",
124	"CMD_INS_UNC",
125	"CMD_DATA_MISS",
126	"CMD_DATA_UNC_READ",
127	"CMD_DATA_UNC_WRITE",
128	"CMD_DATA_WRITE",
129	"CMD_DATA_LL",
130	"CMD_DATA_SC",
131	"CMD_DATA_CAS",
132	};
133
134	const char * vci_pktid_type_str[] = {
135	"TYPE_DATA_UNC",
136	"TYPE_READ_DATA_MISS",
137	"TYPE_READ_INS_UNC",
138	"TYPE_READ_INS_MISS",
139	"TYPE_WRITE",
140	"TYPE_CAS",
141	"TYPE_LL",
142	"TYPE_SC",
143	};
144
145	const char * vci_cmd_type_str[] = {
146	"NOP or STORE_COND",
147	"READ",
148	"WRITE",
149	"LOCKED_READ"
150	};
151
152	const char * rsp_fsm_state_str[] = {
153	"RSP_IDLE",
154	"RSP_INS_MISS",
155	"RSP_INS_UNC",
156	"RSP_DATA_MISS",
157	"RSP_DATA_UNC",
158	"RSP_DATA_LL",
159	"RSP_DATA_WRITE",
160	};
161
162	const char * cc_receive_fsm_state_str[] = {
163	"CC_RECEIVE_IDLE",
164	"CC_RECEIVE_BRDCAST_HEADER",
165	"CC_RECEIVE_BRDCAST_NLINE",
166	"CC_RECEIVE_INS_INVAL_HEADER",
167	"CC_RECEIVE_INS_INVAL_NLINE",
168	"CC_RECEIVE_INS_UPDT_HEADER",
169	"CC_RECEIVE_INS_UPDT_NLINE",
170	"CC_RECEIVE_INS_UPDT_DATA",
171	"CC_RECEIVE_DATA_INVAL_HEADER",
172	"CC_RECEIVE_DATA_INVAL_NLINE",
173	"CC_RECEIVE_DATA_UPDT_HEADER",
174	"CC_RECEIVE_DATA_UPDT_NLINE",
175	"CC_RECEIVE_DATA_UPDT_DATA",
176	"CC_RECEIVE_TEST_HEADER",
177	"CC_RECEIVE_TEST_SIGNATURE",
178	};
179
180	const char * cc_send_fsm_state_str[] = {
181	"CC_SEND_IDLE",
182	"CC_SEND_CLEANUP_1",
183	"CC_SEND_CLEANUP_2",
184	"CC_SEND_MULTI_ACK",
185	"CC_SEND_TEST_HEADER",
186	"CC_SEND_TEST_SIGNATURE",
187	};
188
189	const char * cc_test_fsm_state_str[] = {
190	"CC_TEST_IDLE",
191	"CC_TEST_P2M_REQ",
192	"CC_TEST_P2M_WAIT",
193	"CC_TEST_ACK_WAIT",
194	};
195	}
196
197	#define tmpl(...) \
198	template<typename vci_param, \
199	size_t dspin_in_width, \
200	size_t dspin_out_width, \
201	typename iss_t> __VA_ARGS__ \
202	VciCcVCacheWrapper<vci_param, dspin_in_width, dspin_out_width, iss_t>
203
204	using namespace soclib::common;
205
206	/////////////////////////////////
207	tmpl(/**/)::VciCcVCacheWrapper(
208	sc_module_name name,
209	const int proc_id,
210	const MappingTable &mtd,
211	const IntTab &srcid,
212	const size_t cc_global_id,
213	const size_t itlb_ways,
214	const size_t itlb_sets,
215	const size_t dtlb_ways,
216	const size_t dtlb_sets,
217	const size_t icache_ways,
218	const size_t icache_sets,
219	const size_t icache_words,
220	const size_t dcache_ways,
221	const size_t dcache_sets,
222	const size_t dcache_words,
223	const size_t wbuf_nlines,
224	const size_t wbuf_nwords,
225	const size_t x_width,
226	const size_t y_width,
227	const uint32_t max_frozen_cycles,
228	const uint32_t debug_start_cycle,
229	const bool debug_ok)
230	: soclib::caba::BaseModule(name),
231
232	p_clk("p_clk"),
233	p_resetn("p_resetn"),
234	p_vci("p_vci"),
235	p_dspin_m2p("p_dspin_m2p"),
236	p_dspin_p2m("p_dspin_p2m"),
237	p_dspin_clack("p_dspin_clack"),
238
239	m_cacheability_table( mtd.getCacheabilityTable()),
240	m_srcid(mtd.indexForId(srcid)),
241	m_cc_global_id(cc_global_id),
242	m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2),
243	m_itlb_ways(itlb_ways),
244	m_itlb_sets(itlb_sets),
245	m_dtlb_ways(dtlb_ways),
246	m_dtlb_sets(dtlb_sets),
247	m_icache_ways(icache_ways),
248	m_icache_sets(icache_sets),
249	m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)),
250	m_icache_words(icache_words),
251	m_dcache_ways(dcache_ways),
252	m_dcache_sets(dcache_sets),
253	m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)),
254	m_dcache_words(dcache_words),
255	m_x_width(x_width),
256	m_y_width(y_width),
257	m_proc_id(proc_id),
258	m_max_frozen_cycles(max_frozen_cycles),
259	m_paddr_nbits(vci_param::N),
260	m_debug_start_cycle(debug_start_cycle),
261	m_debug_ok(debug_ok),
262	m_dcache_paddr_ext_reset(0),
263	m_icache_paddr_ext_reset(0),
264
265	r_mmu_ptpr("r_mmu_ptpr"),
266	r_mmu_mode("r_mmu_mode"),
267	r_mmu_word_lo("r_mmu_word_lo"),
268	r_mmu_word_hi("r_mmu_word_hi"),
269	r_mmu_ibvar("r_mmu_ibvar"),
270	r_mmu_dbvar("r_mmu_dbvar"),
271	r_mmu_ietr("r_mmu_ietr"),
272	r_mmu_detr("r_mmu_detr"),
273
274	r_icache_fsm("r_icache_fsm"),
275	r_icache_fsm_save("r_icache_fsm_save"),
276	r_icache_vci_paddr("r_icache_vci_paddr"),
277	r_icache_vaddr_save("r_icache_vaddr_save"),
278
279	r_icache_miss_way("r_icache_miss_way"),
280	r_icache_miss_set("r_icache_miss_set"),
281	r_icache_miss_word("r_icache_miss_word"),
282	r_icache_miss_inval("r_icache_miss_inval"),
283	r_icache_miss_clack("r_icache_miss_clack"),
284
285	r_icache_cc_way("r_icache_cc_way"),
286	r_icache_cc_set("r_icache_cc_set"),
287	r_icache_cc_word("r_icache_cc_word"),
288	r_icache_cc_need_write("r_icache_cc_need_write"),
289
290	r_icache_flush_count("r_icache_flush_count"),
291
292	r_icache_miss_req("r_icache_miss_req"),
293	r_icache_unc_req("r_icache_unc_req"),
294
295	r_icache_tlb_miss_req("r_icache_tlb_read_req"),
296	r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
297
298	r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),
299	r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),
300
301	r_icache_cc_send_req("r_icache_cc_send_req"),
302	r_icache_cc_send_type("r_icache_cc_send_type"),
303	r_icache_cc_send_nline("r_icache_cc_send_nline"),
304	r_icache_cc_send_way("r_icache_cc_send_way"),
305	r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
306
307	r_dcache_fsm("r_dcache_fsm"),
308	r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"),
309	r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"),
310
311	r_dcache_wbuf_req("r_dcache_wbuf_req"),
312	r_dcache_updt_req("r_dcache_updt_req"),
313	r_dcache_save_vaddr("r_dcache_save_vaddr"),
314	r_dcache_save_wdata("r_dcache_save_wdata"),
315	r_dcache_save_be("r_dcache_save_be"),
316	r_dcache_save_paddr("r_dcache_save_paddr"),
317	r_dcache_save_cache_way("r_dcache_save_cache_way"),
318	r_dcache_save_cache_set("r_dcache_save_cache_set"),
319	r_dcache_save_cache_word("r_dcache_save_cache_word"),
320
321	r_dcache_dirty_paddr("r_dcache_dirty_paddr"),
322	r_dcache_dirty_way("r_dcache_dirty_way"),
323	r_dcache_dirty_set("r_dcache_dirty_set"),
324
325	r_dcache_vci_paddr("r_dcache_vci_paddr"),
326	r_dcache_vci_wdata("r_dcache_vci_wdata"),
327	r_dcache_vci_miss_req("r_dcache_vci_miss_req"),
328	r_dcache_vci_unc_req("r_dcache_vci_unc_req"),
329	r_dcache_vci_unc_be("r_dcache_vci_unc_be"),
330	r_dcache_vci_unc_write("r_dcache_vci_unc_write"),
331	r_dcache_vci_cas_req("r_dcache_vci_cas_req"),
332	r_dcache_vci_cas_old("r_dcache_vci_cas_old"),
333	r_dcache_vci_cas_new("r_dcache_vci_cas_new"),
334	r_dcache_vci_ll_req("r_dcache_vci_ll_req"),
335	r_dcache_vci_sc_req("r_dcache_vci_sc_req"),
336	r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
337	r_dcache_vci_wdt_trdid("r_dcache_vci_wdt_trdid"),
338
339	r_dcache_xtn_way("r_dcache_xtn_way"),
340	r_dcache_xtn_set("r_dcache_xtn_set"),
341
342	r_dcache_miss_type("r_dcache_miss_type"),
343	r_dcache_miss_word("r_dcache_miss_word"),
344	r_dcache_miss_way("r_dcache_miss_way"),
345	r_dcache_miss_set("r_dcache_miss_set"),
346	r_dcache_miss_inval("r_dcache_miss_inval"),
347
348	r_dcache_wdt_max("r_dcache_wdt_max"),
349	r_dcache_wdt("r_dcache_wdt"),
350	r_dcache_wdt_timeout("r_dcache_wdt_timeout"),
351
352	r_dcache_cc_way("r_dcache_cc_way"),
353	r_dcache_cc_set("r_dcache_cc_set"),
354	r_dcache_cc_word("r_dcache_cc_word"),
355	r_dcache_cc_need_write("r_dcache_cc_need_write"),
356
357	r_dcache_flush_count("r_dcache_flush_count"),
358
359	r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"),
360
361	r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
362	r_dcache_tlb_ins("r_dcache_tlb_ins"),
363	r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
364	r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
365	r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
366	r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
367	r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
368	r_dcache_tlb_way("r_dcache_tlb_way"),
369	r_dcache_tlb_set("r_dcache_tlb_set"),
370
371	r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"),
372	r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"),
373
374	r_dcache_xtn_req("r_dcache_xtn_req"),
375	r_dcache_xtn_opcode("r_dcache_xtn_opcode"),
376
377	r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
378	r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
379
380	r_dcache_cc_send_req("r_dcache_cc_send_req"),
381	r_dcache_cc_send_type("r_dcache_cc_send_type"),
382	r_dcache_cc_send_nline("r_dcache_cc_send_nline"),
383	r_dcache_cc_send_way("r_dcache_cc_send_way"),
384	r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
385
386	r_dcache_to_cc_test_req("r_dcache_to_cc_test_req"),
387	r_dcache_to_cc_test_dest("r_dcache_to_cc_test_dest"),
388
389	r_vci_cmd_fsm("r_vci_cmd_fsm"),
390	r_vci_cmd_min("r_vci_cmd_min"),
391	r_vci_cmd_max("r_vci_cmd_max"),
392	r_vci_cmd_cpt("r_vci_cmd_cpt"),
393	r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"),
394
395	r_vci_rsp_fsm("r_vci_rsp_fsm"),
396	r_vci_rsp_cpt("r_vci_rsp_cpt"),
397	r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
398	r_vci_rsp_data_error("r_vci_rsp_data_error"),
399	r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
400	r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
401
402	r_cc_send_fsm("r_cc_send_fsm"),
403	r_cc_send_last_client("r_cc_send_last_client"),
404
405	r_cc_receive_fsm("r_cc_receive_fsm"),
406	r_cc_receive_data_ins("r_cc_receive_data_ins"),
407	r_cc_receive_word_idx("r_cc_receive_word_idx"),
408	r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth
409	r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
410	r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth
411
412	r_cc_receive_icache_req("r_cc_receive_icache_req"),
413	r_cc_receive_icache_type("r_cc_receive_icache_type"),
414	r_cc_receive_icache_way("r_cc_receive_icache_way"),
415	r_cc_receive_icache_set("r_cc_receive_icache_set"),
416	r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"),
417	r_cc_receive_icache_nline("r_cc_receive_icache_nline"),
418
419	r_cc_receive_dcache_req("r_cc_receive_dcache_req"),
420	r_cc_receive_dcache_type("r_cc_receive_dcache_type"),
421	r_cc_receive_dcache_way("r_cc_receive_dcache_way"),
422	r_cc_receive_dcache_set("r_cc_receive_dcache_set"),
423	r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
424	r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
425
426	r_cc_test_fsm("r_cc_test_fsm"),
427	r_cc_test_to_cc_send_req("r_cc_test_to_cc_send_req"),
428	r_cc_test_m2p_req("r_cc_test_m2p_req"),
429	r_cc_test_m2p_sign("r_cc_test_m2p_sign"),
430	r_cc_test_clack_req("r_cc_test_clack_req"),
431	r_cc_test_clack_sign("r_cc_test_clack_sign"),
432
433	r_iss(this->name(), proc_id),
434	r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ),
435	r_icache("icache", icache_ways, icache_sets, icache_words),
436	r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
437	r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
438	r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
439	{
440	std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl;
441
442	assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and
443	"Need more PLEN bits.");
444
445	assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and
446	"Need more TRDID bits.");
447
448	assert((icache_words == dcache_words) and
449	"icache_words and dcache_words parameters must be equal");
450
451	assert((itlb_sets == dtlb_sets) and
452	"itlb_sets and dtlb_sets parameters must be etqual");
453
454	assert((itlb_ways == dtlb_ways) and
455	"itlb_ways and dtlb_ways parameters must be etqual");
456
457	r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) \| (uint32_log2(m_dtlb_sets) << 25) \|
458	(uint32_log2(m_dcache_ways) << 22) \| (uint32_log2(m_dcache_sets) << 18) \|
459	(uint32_log2(m_itlb_ways) << 15) \| (uint32_log2(m_itlb_sets) << 11) \|
460	(uint32_log2(m_icache_ways) << 8) \| (uint32_log2(m_icache_sets) << 4) \|
461	(uint32_log2(m_icache_words << 2));
462
463	r_mmu_release = (uint32_t) (1 << 16) \| 0x1;
464
465	r_dcache_in_tlb = new bool[dcache_ways * dcache_sets];
466	r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets];
467
468	SC_METHOD(transition);
469	dont_initialize();
470	sensitive << p_clk.pos();
471
472	SC_METHOD(genMoore);
473	dont_initialize();
474	sensitive << p_clk.neg();
475
476	typename iss_t::CacheInfo cache_info;
477	cache_info.has_mmu = true;
478	cache_info.icache_line_size = icache_words * sizeof(uint32_t);
479	cache_info.icache_assoc = icache_ways;
480	cache_info.icache_n_lines = icache_sets;
481	cache_info.dcache_line_size = dcache_words * sizeof(uint32_t);
482	cache_info.dcache_assoc = dcache_ways;
483	cache_info.dcache_n_lines = dcache_sets;
484	r_iss.setCacheInfo(cache_info);
485	}
486
487	/////////////////////////////////////
488	tmpl(/**/)::~VciCcVCacheWrapper()
489	/////////////////////////////////////
490	{
491	delete [] r_dcache_in_tlb;
492	delete [] r_dcache_contains_ptd;
493	}
494
495	////////////////////////
496	tmpl(void)::print_cpi()
497	////////////////////////
498	{
499	std::cout << name() << " CPI = "
500	<< (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ;
501	}
502
503	////////////////////////////////////
504	tmpl(void)::print_trace(size_t mode)
505	////////////////////////////////////
506	{
507	// b0 : write buffer trace
508	// b1 : dump processor registers
509	// b2 : dcache trace
510	// b3 : icache trace
511	// b4 : dtlb trace
512	// b5 : itlb trace
513	// b6 : SR (ISS register 32)
514
515	std::cout << std::dec << "PROC " << name() << std::endl;
516
517	std::cout << " " << m_ireq << std::endl;
518	std::cout << " " << m_irsp << std::endl;
519	std::cout << " " << m_dreq << std::endl;
520	std::cout << " " << m_drsp << std::endl;
521
522	std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()]
523	<< " \| " << dcache_fsm_state_str[r_dcache_fsm.read()]
524	<< " \| " << cmd_fsm_state_str[r_vci_cmd_fsm.read()]
525	<< " \| " << rsp_fsm_state_str[r_vci_rsp_fsm.read()]
526	<< " \| " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()]
527	<< " \| " << cc_send_fsm_state_str[r_cc_send_fsm.read()]
528	<< " \| " << cc_test_fsm_state_str[r_cc_test_fsm.read()]
529	<< " \| MMU = " << r_mmu_mode.read();
530
531	if (r_dcache_updt_req.read()) std::cout << " \| P1_UPDT";
532	if (r_dcache_wbuf_req.read()) std::cout << " \| P1_WBUF";
533	std::cout << std::endl;
534
535	if (mode & 0x01)
536	{
537	if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl;
538	if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl;
539	if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl;
540	if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl;
541
542	r_wbuf.printTrace((mode >> 1) & 1);
543	}
544	if (mode & 0x02)
545	{
546	r_iss.dump();
547	}
548	if (mode & 0x04)
549	{
550	std::cout << " Data Cache" << std::endl;
551	r_dcache.printTrace();
552	}
553	if (mode & 0x08)
554	{
555	std::cout << " Instruction Cache" << std::endl;
556	r_icache.printTrace();
557	}
558	if (mode & 0x10)
559	{
560	std::cout << " Data TLB" << std::endl;
561	r_dtlb.printTrace();
562	}
563	if (mode & 0x20)
564	{
565	std::cout << " Instruction TLB" << std::endl;
566	r_itlb.printTrace();
567	}
568	if (mode & 0x40)
569	{
570	uint32_t status = r_iss.debugGetRegisterValue(32);
571	std::cout << name();
572	if (status != m_previous_status ) std::cout << " NEW ";
573	std::cout << " status = " << std::hex << status << " " << std::endl;
574	m_previous_status = status;
575	}
576	}
577
578	//////////////////////////////////////////
579	tmpl(void)::cache_monitor(paddr_t addr)
580	//////////////////////////////////////////
581	{
582	bool cache_hit;
583	size_t cache_way = 0;
584	size_t cache_set = 0;
585	size_t cache_word = 0;
586	uint32_t cache_rdata = 0;
587
588	cache_hit = r_dcache.read_neutral(addr,
589	&cache_rdata,
590	&cache_way,
591	&cache_set,
592	&cache_word);
593
594	if (cache_hit != m_debug_previous_d_hit)
595	{
596	std::cout << "Monitor PROC " << name()
597	<< " DCACHE at cycle " << std::dec << m_cpt_total_cycles
598	<< " / HIT = " << cache_hit
599	<< " / PADDR = " << std::hex << addr
600	<< " / DATA = " << cache_rdata
601	<< " / WAY = " << cache_way << std::endl;
602	m_debug_previous_d_hit = cache_hit;
603	}
604
605	cache_hit = r_icache.read_neutral(addr,
606	&cache_rdata,
607	&cache_way,
608	&cache_set,
609	&cache_word);
610
611	if (cache_hit != m_debug_previous_i_hit)
612	{
613	std::cout << "Monitor PROC " << name()
614	<< " ICACHE at cycle " << std::dec << m_cpt_total_cycles
615	<< " / HIT = " << cache_hit
616	<< " / PADDR = " << std::hex << addr
617	<< " / DATA = " << cache_rdata
618	<< " / WAY = " << cache_way << std::endl;
619	m_debug_previous_i_hit = cache_hit;
620	}
621	}
622
623	/*
624	////////////////////////
625	tmpl(void)::print_stats()
626	////////////////////////
627	{
628	float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
629	std::cout << name() << std::endl
630	<< "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl
631	<< "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl
632	<< "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl
633	<< "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
634	<< "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl
635	<< "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
636	<< "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
637	<< "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl
638	<< "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
639	<< "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl
640	<< "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl
641	<< "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
642	<< "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
643	<< "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
644	<< "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
645	<< "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
646	<< "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
647	<< "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
648	<< "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
649	<< "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
650	<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
651	<< "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
652	<< "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl
653	<< "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl
654	<< "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl
655	<< "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl
656	<< "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
657	<< "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl
658	<< "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl
659	<< "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl
660	<< "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl
661	<< "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl
662	<< "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
663	<< "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
664	<< "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
665	<< "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
666	<< "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
667	<< "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
668	<< "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl;
669	}
670
671	////////////////////////
672	tmpl(void)::clear_stats()
673	////////////////////////
674	{
675	m_cpt_dcache_data_read = 0;
676	m_cpt_dcache_data_write = 0;
677	m_cpt_dcache_dir_read = 0;
678	m_cpt_dcache_dir_write = 0;
679	m_cpt_icache_data_read = 0;
680	m_cpt_icache_data_write = 0;
681	m_cpt_icache_dir_read = 0;
682	m_cpt_icache_dir_write = 0;
683
684	m_cpt_frz_cycles = 0;
685	m_cpt_dcache_frz_cycles = 0;
686	m_cpt_total_cycles = 0;
687
688	m_cpt_read = 0;
689	m_cpt_write = 0;
690	m_cpt_data_miss = 0;
691	m_cpt_ins_miss = 0;
692	m_cpt_unc_read = 0;
693	m_cpt_write_cached = 0;
694	m_cpt_ins_read = 0;
695
696	m_cost_write_frz = 0;
697	m_cost_data_miss_frz = 0;
698	m_cost_unc_read_frz = 0;
699	m_cost_ins_miss_frz = 0;
700
701	m_cpt_imiss_transaction = 0;
702	m_cpt_dmiss_transaction = 0;
703	m_cpt_unc_transaction = 0;
704	m_cpt_write_transaction = 0;
705	m_cpt_icache_unc_transaction = 0;
706
707	m_cost_imiss_transaction = 0;
708	m_cost_dmiss_transaction = 0;
709	m_cost_unc_transaction = 0;
710	m_cost_write_transaction = 0;
711	m_cost_icache_unc_transaction = 0;
712	m_length_write_transaction = 0;
713
714	m_cpt_ins_tlb_read = 0;
715	m_cpt_ins_tlb_miss = 0;
716	m_cpt_ins_tlb_update_acc = 0;
717
718	m_cpt_data_tlb_read = 0;
719	m_cpt_data_tlb_miss = 0;
720	m_cpt_data_tlb_update_acc = 0;
721	m_cpt_data_tlb_update_dirty = 0;
722	m_cpt_ins_tlb_hit_dcache = 0;
723	m_cpt_data_tlb_hit_dcache = 0;
724	m_cpt_ins_tlb_occup_cache = 0;
725	m_cpt_data_tlb_occup_cache = 0;
726
727	m_cost_ins_tlb_miss_frz = 0;
728	m_cost_data_tlb_miss_frz = 0;
729	m_cost_ins_tlb_update_acc_frz = 0;
730	m_cost_data_tlb_update_acc_frz = 0;
731	m_cost_data_tlb_update_dirty_frz = 0;
732	m_cost_ins_tlb_occup_cache_frz = 0;
733	m_cost_data_tlb_occup_cache_frz = 0;
734
735	m_cpt_itlbmiss_transaction = 0;
736	m_cpt_itlb_ll_transaction = 0;
737	m_cpt_itlb_sc_transaction = 0;
738	m_cpt_dtlbmiss_transaction = 0;
739	m_cpt_dtlb_ll_transaction = 0;
740	m_cpt_dtlb_sc_transaction = 0;
741	m_cpt_dtlb_ll_dirty_transaction = 0;
742	m_cpt_dtlb_sc_dirty_transaction = 0;
743
744	m_cost_itlbmiss_transaction = 0;
745	m_cost_itlb_ll_transaction = 0;
746	m_cost_itlb_sc_transaction = 0;
747	m_cost_dtlbmiss_transaction = 0;
748	m_cost_dtlb_ll_transaction = 0;
749	m_cost_dtlb_sc_transaction = 0;
750	m_cost_dtlb_ll_dirty_transaction = 0;
751	m_cost_dtlb_sc_dirty_transaction = 0;
752
753	m_cpt_cc_update_data = 0;
754	m_cpt_cc_inval_ins = 0;
755	m_cpt_cc_inval_data = 0;
756	m_cpt_cc_broadcast = 0;
757
758	m_cost_updt_data_frz = 0;
759	m_cost_inval_ins_frz = 0;
760	m_cost_inval_data_frz = 0;
761	m_cost_broadcast_frz = 0;
762
763	m_cpt_cc_cleanup_data = 0;
764	m_cpt_cc_cleanup_ins = 0;
765	}
766
767	*/
768
769	/////////////////////////
770	tmpl(void)::transition()
771	/////////////////////////
772	{
773	if (not p_resetn.read())
774	{
775	r_iss.reset();
776	r_wbuf.reset();
777	r_icache.reset();
778	r_dcache.reset();
779	r_itlb.reset();
780	r_dtlb.reset();
781
782	r_dcache_fsm = DCACHE_IDLE;
783	r_icache_fsm = ICACHE_IDLE;
784	r_vci_cmd_fsm = CMD_IDLE;
785	r_vci_rsp_fsm = RSP_IDLE;
786	r_cc_receive_fsm = CC_RECEIVE_IDLE;
787	r_cc_send_fsm = CC_SEND_IDLE;
788	r_cc_test_fsm = CC_TEST_IDLE;
789
790	// reset data physical address extension
791	r_dcache_paddr_ext = m_dcache_paddr_ext_reset;
792
793	// reset inst physical address extension
794	r_icache_paddr_ext = m_icache_paddr_ext_reset;
795
796	// reset dcache directory extension
797	for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++)
798	{
799	r_dcache_in_tlb[i] = false;
800	r_dcache_contains_ptd[i] = false;
801	}
802
803	// Response FIFOs and cleanup buffer
804	r_vci_rsp_fifo_icache.init();
805	r_vci_rsp_fifo_dcache.init();
806
807	// ICACHE & DCACHE activated
808	// ITLB & DTLB desactivated
809	r_mmu_mode = 0x3;
810
811	// No request from ICACHE FSM to CMD FSM
812	r_icache_miss_req = false;
813	r_icache_unc_req = false;
814
815	// No request from ICACHE_FSM to DCACHE FSM
816	r_icache_tlb_miss_req = false;
817
818	// No request from ICACHE_FSM to CC_SEND FSM
819	r_icache_cc_send_req = false;
820	r_icache_cleanup_victim_req = false;
821
822	r_icache_clack_req = false;
823
824	// No pending write in pipeline
825	r_dcache_wbuf_req = false;
826	r_dcache_updt_req = false;
827
828	// No request from DCACHE_FSM to CMD_FSM
829	r_dcache_vci_miss_req = false;
830	r_dcache_vci_unc_req = false;
831	r_dcache_vci_cas_req = false;
832	r_dcache_vci_ll_req = false;
833	r_dcache_vci_sc_req = false;
834
835	// No processor XTN request pending
836	r_dcache_xtn_req = false;
837
838	// No request from DCACHE FSM to CC_SEND FSM
839	r_dcache_cc_send_req = false;
840	r_dcache_cleanup_victim_req = false;
841
842	r_dcache_clack_req = false;
843
844	// Reset watchdog timer (watchdog mechanism is deactivated)
845	r_dcache_wdt_max = 0;
846	r_dcache_wdt_timeout = 0;
847
848	// No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs
849	r_cc_receive_icache_req = false;
850	r_cc_receive_dcache_req = false;
851
852	// last cc_send client was dcache
853	r_cc_send_last_client = false;
854
855	// No pending cleanup after a replacement
856	r_icache_miss_clack = false;
857	r_dcache_miss_clack = false;
858
859	// No signalisation of a coherence request matching a pending miss
860	r_icache_miss_inval = false;
861	r_dcache_miss_inval = false;
862
863	r_dspin_clack_req = false;
864	r_dspin_clack_test = false;
865
866	r_cc_test_to_cc_send_req = false;
867	r_cc_test_m2p_req = false;
868	r_cc_test_clack_req = false;
869
870	// No signalisation of errors
871	r_vci_rsp_ins_error = false;
872	r_vci_rsp_data_error = false;
873
874	// Debug variables
875	m_debug_previous_i_hit = false;
876	m_debug_previous_d_hit = false;
877	m_debug_icache_fsm = false;
878	m_debug_dcache_fsm = false;
879	m_debug_cmd_fsm = false;
880
881	// activity counters
882	m_cpt_dcache_data_read = 0;
883	m_cpt_dcache_data_write = 0;
884	m_cpt_dcache_dir_read = 0;
885	m_cpt_dcache_dir_write = 0;
886	m_cpt_icache_data_read = 0;
887	m_cpt_icache_data_write = 0;
888	m_cpt_icache_dir_read = 0;
889	m_cpt_icache_dir_write = 0;
890
891	m_cpt_frz_cycles = 0;
892	m_cpt_total_cycles = 0;
893	m_cpt_stop_simulation = 0;
894
895	m_cpt_data_miss = 0;
896	m_cpt_ins_miss = 0;
897	m_cpt_unc_read = 0;
898	m_cpt_write_cached = 0;
899	m_cpt_ins_read = 0;
900
901	m_cost_write_frz = 0;
902	m_cost_data_miss_frz = 0;
903	m_cost_unc_read_frz = 0;
904	m_cost_ins_miss_frz = 0;
905
906	m_cpt_imiss_transaction = 0;
907	m_cpt_dmiss_transaction = 0;
908	m_cpt_unc_transaction = 0;
909	m_cpt_write_transaction = 0;
910	m_cpt_icache_unc_transaction = 0;
911
912	m_cost_imiss_transaction = 0;
913	m_cost_dmiss_transaction = 0;
914	m_cost_unc_transaction = 0;
915	m_cost_write_transaction = 0;
916	m_cost_icache_unc_transaction = 0;
917	m_length_write_transaction = 0;
918
919	m_cpt_ins_tlb_read = 0;
920	m_cpt_ins_tlb_miss = 0;
921	m_cpt_ins_tlb_update_acc = 0;
922
923	m_cpt_data_tlb_read = 0;
924	m_cpt_data_tlb_miss = 0;
925	m_cpt_data_tlb_update_acc = 0;
926	m_cpt_data_tlb_update_dirty = 0;
927	m_cpt_ins_tlb_hit_dcache = 0;
928	m_cpt_data_tlb_hit_dcache = 0;
929	m_cpt_ins_tlb_occup_cache = 0;
930	m_cpt_data_tlb_occup_cache = 0;
931
932	m_cost_ins_tlb_miss_frz = 0;
933	m_cost_data_tlb_miss_frz = 0;
934	m_cost_ins_tlb_update_acc_frz = 0;
935	m_cost_data_tlb_update_acc_frz = 0;
936	m_cost_data_tlb_update_dirty_frz = 0;
937	m_cost_ins_tlb_occup_cache_frz = 0;
938	m_cost_data_tlb_occup_cache_frz = 0;
939
940	m_cpt_ins_tlb_inval = 0;
941	m_cpt_data_tlb_inval = 0;
942	m_cost_ins_tlb_inval_frz = 0;
943	m_cost_data_tlb_inval_frz = 0;
944
945	m_cpt_cc_broadcast = 0;
946
947	m_cost_updt_data_frz = 0;
948	m_cost_inval_ins_frz = 0;
949	m_cost_inval_data_frz = 0;
950	m_cost_broadcast_frz = 0;
951
952	m_cpt_cc_cleanup_data = 0;
953	m_cpt_cc_cleanup_ins = 0;
954
955	m_cpt_itlbmiss_transaction = 0;
956	m_cpt_itlb_ll_transaction = 0;
957	m_cpt_itlb_sc_transaction = 0;
958	m_cpt_dtlbmiss_transaction = 0;
959	m_cpt_dtlb_ll_transaction = 0;
960	m_cpt_dtlb_sc_transaction = 0;
961	m_cpt_dtlb_ll_dirty_transaction = 0;
962	m_cpt_dtlb_sc_dirty_transaction = 0;
963
964	m_cost_itlbmiss_transaction = 0;
965	m_cost_itlb_ll_transaction = 0;
966	m_cost_itlb_sc_transaction = 0;
967	m_cost_dtlbmiss_transaction = 0;
968	m_cost_dtlb_ll_transaction = 0;
969	m_cost_dtlb_sc_transaction = 0;
970	m_cost_dtlb_ll_dirty_transaction = 0;
971	m_cost_dtlb_sc_dirty_transaction = 0;
972	/*
973	m_cpt_dcache_frz_cycles = 0;
974	m_cpt_read = 0;
975	m_cpt_write = 0;
976	m_cpt_cc_update_data = 0;
977	m_cpt_cc_inval_ins = 0;
978	m_cpt_cc_inval_data = 0;
979	*/
980
981	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0;
982	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0;
983	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0;
984	for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
985
986	// init the llsc reservation buffer
987	r_dcache_llsc_valid = false;
988	m_monitor_ok = false;
989
990	return;
991	}
992
993	// Response FIFOs default values
994	bool vci_rsp_fifo_icache_get = false;
995	bool vci_rsp_fifo_icache_put = false;
996	uint32_t vci_rsp_fifo_icache_data = 0;
997
998	bool vci_rsp_fifo_dcache_get = false;
999	bool vci_rsp_fifo_dcache_put = false;
1000	uint32_t vci_rsp_fifo_dcache_data = 0;
1001
1002	// updt fifo
1003	bool cc_receive_updt_fifo_get = false;
1004	bool cc_receive_updt_fifo_put = false;
1005	uint32_t cc_receive_updt_fifo_be = 0;
1006	uint32_t cc_receive_updt_fifo_data = 0;
1007	bool cc_receive_updt_fifo_eop = false;
1008
1009	#ifdef INSTRUMENTATION
1010	m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++;
1011	m_cpt_fsm_icache [r_icache_fsm.read() ] ++;
1012	m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++;
1013	m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++;
1014	m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++;
1015	m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()] ++;
1016	#endif
1017
1018	m_cpt_total_cycles++;
1019
1020	m_debug_icache_fsm = m_debug_icache_fsm \|\|
1021	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
1022	m_debug_dcache_fsm = m_debug_dcache_fsm \|\|
1023	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
1024	m_debug_cmd_fsm = m_debug_cmd_fsm \|\|
1025	((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok);
1026
1027	/////////////////////////////////////////////////////////////////////
1028	// Get data and instruction requests from processor
1029	///////////////////////////////////////////////////////////////////////
1030
1031	r_iss.getRequests(m_ireq, m_dreq);
1032
1033	////////////////////////////////////////////////////////////////////////////////////
1034	// ICACHE_FSM
1035	//
1036	// 1/ Coherence operations
1037	// They are handled as interrupts generated by the CC_RECEIVE FSM.
1038	// - There is a coherence request when r_tgt_icache_req is set.
1039	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states.
1040	// - There is a cleanup ack request when r_cleanup_icache_req is set.
1041	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT,
1042	// MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states.
1043	// - For both types of requests, actions associated to the pre-empted state
1044	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
1045	// or CC_CLACK) to execute the requested coherence operation, and returns
1046	// to the pre-empted state.
1047	//
1048	// 2/ Processor requests
1049	// They are taken in IDLE state only. In case of cache miss, or uncacheable
1050	// instruction, the ICACHE FSM request a VCI transaction to CMD FSM,
1051	// using the r_icache_miss_req or r_icache_unc_req flip-flops. These
1052	// flip-flops are reset when the transaction starts.
1053	// - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state
1054	// to select a slot and possibly request a cleanup transaction to the CC_SEND FSM.
1055	// It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM,
1056	// The availability of the missing cache line is signaled by the response fifo,
1057	// and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT
1058	// and ICACHE_MISS_DIR_UPDT states.
1059	// - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT
1060	// to wait the response from the RSP FSM, through the response fifo.
1061	// The missing instruction is directly returned to processor in this state.
1062	//
1063	// 3/ TLB miss
1064	// In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the
1065	// ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr
1066	// register, and goes to the ICACHE_TLB_WAIT state.
1067	// The tlb update is entirely done by the DCACHE FSM (who becomes the owner
1068	// of ITLB until the update is completed, and reset r_icache_tlb_miss_req
1069	// to signal the completion.
1070	//
1071	// 4/ XTN requests
1072	// The DCACHE FSM signals XTN processor requests to ICACHE_FSM
1073	// using the r_dcache_xtn_req flip-flop.
1074	// The request opcode and the address to be invalidated are transmitted
1075	// in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively.
1076	// The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation
1077	// is completed.
1078	//
1079	// 5/ Error Handling
1080	// The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error
1081	// in a cache miss or uncacheable read VCI transaction. Nothing is written
1082	// in the response fifo. This flip-flop is reset by the ICACHE-FSM.
1083	////////////////////////////////////////////////////////////////////////////////////////
1084
1085	// default value for m_irsp
1086	m_irsp.valid = false;
1087	m_irsp.error = false;
1088	m_irsp.instruction = 0;
1089
1090	switch (r_icache_fsm.read())
1091	{
1092	/////////////////
1093	case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests,
1094	// and coherence requests with a fixed priority:
1095	// 1/ Coherence requests => ICACHE_CC_CHECK
1096	// 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_*
1097	// 3/ tlb miss => ICACHE_TLB_WAIT
1098	// 4/ cacheable read miss => ICACHE_MISS_SELECT
1099	// 5/ uncacheable read miss => ICACHE_UNC_REQ
1100	{
1101	// coherence clack interrupt
1102	if (r_icache_clack_req.read())
1103	{
1104	r_icache_fsm = ICACHE_CC_CHECK;
1105	r_icache_fsm_save = r_icache_fsm.read();
1106	break;
1107	}
1108
1109	// coherence interrupt
1110	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1111	{
1112	r_icache_fsm = ICACHE_CC_CHECK;
1113	r_icache_fsm_save = r_icache_fsm.read();
1114	break;
1115	}
1116
1117	// XTN requests sent by DCACHE FSM
1118	// These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT),
1119	// because they require access to icache or itlb, that are already accessed
1120	if (r_dcache_xtn_req.read())
1121	{
1122	if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR )
1123	{
1124	r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
1125	}
1126	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH)
1127	{
1128	r_icache_flush_count = 0;
1129	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1130	}
1131	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL)
1132	{
1133	r_icache_fsm = ICACHE_XTN_TLB_INVAL;
1134	}
1135	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL)
1136	{
1137	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
1138	}
1139	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
1140	{
1141	uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) \|
1142	((uint64_t)r_mmu_word_lo.read());
1143
1144	r_icache_vci_paddr = (paddr_t)pa;
1145	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1146	}
1147	else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT)
1148	{
1149	r_icache_paddr_ext = r_dcache_save_wdata.read();
1150	r_dcache_xtn_req = false;
1151	}
1152	else
1153	{
1154	assert(false and
1155	"undefined XTN request received by ICACHE FSM");
1156	}
1157	break;
1158	} // end if xtn_req
1159
1160	// processor request
1161	if (m_ireq.valid )
1162	{
1163	bool cacheable;
1164	paddr_t paddr;
1165	bool tlb_hit = false;
1166	pte_info_t tlb_flags;
1167	size_t tlb_way;
1168	size_t tlb_set;
1169	paddr_t tlb_nline;
1170	uint32_t cache_inst = 0;
1171	size_t cache_way;
1172	size_t cache_set;
1173	size_t cache_word;
1174	int cache_state = CACHE_SLOT_STATE_EMPTY;
1175
1176	// We register processor request
1177	r_icache_vaddr_save = m_ireq.addr;
1178	paddr = (paddr_t) m_ireq.addr;
1179
1180	// sytematic itlb access (if activated)
1181	if (r_mmu_mode.read() & INS_TLB_MASK)
1182	{
1183
1184	#ifdef INSTRUMENTATION
1185	m_cpt_itlb_read++;
1186	#endif
1187	tlb_hit = r_itlb.translate(m_ireq.addr,
1188	&paddr,
1189	&tlb_flags,
1190	&tlb_nline, // unused
1191	&tlb_way, // unused
1192	&tlb_set); // unused
1193	}
1194	else if (vci_param::N > 32)
1195	{
1196	paddr = paddr \| ((paddr_t) r_icache_paddr_ext.read() << 32);
1197	}
1198
1199	// systematic icache access (if activated)
1200	if (r_mmu_mode.read() & INS_CACHE_MASK)
1201	{
1202
1203
1204	#ifdef INSTRUMENTATION
1205	m_cpt_icache_data_read++;
1206	m_cpt_icache_dir_read++;
1207	#endif
1208	r_icache.read(paddr,
1209	&cache_inst,
1210	&cache_way,
1211	&cache_set,
1212	&cache_word,
1213	&cache_state);
1214	}
1215
1216	// We compute cacheability and check access rights:
1217	// - If MMU activated : cacheability is defined by the C bit in the PTE,
1218	// and the access rights are defined by the U and X bits in the PTE.
1219	// - If MMU not activated : cacheability is defined by the segment table,
1220	// and there is no access rights checking
1221
1222	if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated:
1223	{
1224	// cacheability
1225	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1226	else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr];
1227	}
1228	else // itlb activated
1229	{
1230	if (tlb_hit) // ITLB hit
1231	{
1232	// cacheability
1233	if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
1234	else cacheable = tlb_flags.c;
1235
1236	// access rights checking
1237	if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
1238	{
1239
1240	#if DEBUG_ICACHE
1241	if ( m_debug_icache_fsm )
1242	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation"
1243	<< " : PADDR = " << std::hex << paddr << std::endl;
1244	#endif
1245	r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION;
1246	r_mmu_ibvar = m_ireq.addr;
1247	m_irsp.valid = true;
1248	m_irsp.error = true;
1249	m_irsp.instruction = 0;
1250	break;
1251	}
1252	else if (not tlb_flags.x)
1253	{
1254
1255	#if DEBUG_ICACHE
1256	if ( m_debug_icache_fsm )
1257	std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation"
1258	<< " : PADDR = " << std::hex << paddr << std::endl;
1259	#endif
1260	r_mmu_ietr = MMU_READ_EXEC_VIOLATION;
1261	r_mmu_ibvar = m_ireq.addr;
1262	m_irsp.valid = true;
1263	m_irsp.error = true;
1264	m_irsp.instruction = 0;
1265	break;
1266	}
1267	}
1268	else // ITLB miss
1269	{
1270
1271	#ifdef INSTRUMENTATION
1272	m_cpt_itlb_miss++;
1273	#endif
1274	r_icache_fsm = ICACHE_TLB_WAIT;
1275	r_icache_tlb_miss_req = true;
1276	break;
1277	}
1278	} // end if itlb activated
1279
1280	// physical address registration
1281	r_icache_vci_paddr = paddr;
1282
1283	// Finally, we send the response to processor, and compute next state
1284	if (cacheable)
1285	{
1286	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
1287	{
1288
1289	#ifdef INSTRUMENTATION
1290	m_cpt_icache_miss++;
1291	#endif
1292	// we request a VCI transaction
1293	r_icache_fsm = ICACHE_MISS_SELECT;
1294	#if DEBUG_ICACHE
1295	if (m_debug_icache_fsm)
1296	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
1297	<< " : PADDR = " << std::hex << paddr << std::endl;
1298	#endif
1299	r_icache_miss_req = true;
1300	}
1301	else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
1302	{
1303	// stalled until cleanup is acknowledged
1304	r_icache_fsm = ICACHE_IDLE;
1305	}
1306	else // cache hit
1307	{
1308
1309	#ifdef INSTRUMENTATION
1310	m_cpt_ins_read++;
1311	#endif
1312	// return instruction to processor
1313	m_irsp.valid = true;
1314	m_irsp.instruction = cache_inst;
1315	r_icache_fsm = ICACHE_IDLE;
1316	#if DEBUG_ICACHE
1317	if (m_debug_icache_fsm)
1318	std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
1319	<< " : PADDR = " << std::hex << paddr
1320	<< " / INST = " << cache_inst << std::endl;
1321	#endif
1322	}
1323	}
1324	else // non cacheable read
1325	{
1326	r_icache_unc_req = true;
1327	r_icache_fsm = ICACHE_UNC_WAIT;
1328
1329	#if DEBUG_ICACHE
1330	if (m_debug_icache_fsm)
1331	{
1332	std::cout << " <PROC " << name()
1333	<< " ICACHE_IDLE> READ UNCACHEABLE in icache"
1334	<< " : PADDR = " << std::hex << paddr << std::endl;
1335	}
1336	#endif
1337	}
1338	} // end if m_ireq.valid
1339	break;
1340	}
1341	/////////////////////
1342	case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss
1343	// the itlb is udated by the DCACHE FSM, as well as the
1344	// r_mmu_ietr and r_mmu_ibvar registers in case of error.
1345	// the itlb is not accessed by ICACHE FSM until DCACHE FSM
1346	// reset the r_icache_tlb_miss_req flip-flop
1347	// external coherence request are accepted in this state.
1348	{
1349	// coherence clack interrupt
1350	if (r_icache_clack_req.read())
1351	{
1352	r_icache_fsm = ICACHE_CC_CHECK;
1353	r_icache_fsm_save = r_icache_fsm.read();
1354	break;
1355	}
1356
1357	// coherence interrupt
1358	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1359	{
1360	r_icache_fsm = ICACHE_CC_CHECK;
1361	r_icache_fsm_save = r_icache_fsm.read();
1362	break;
1363	}
1364
1365	if (m_ireq.valid) m_cost_ins_tlb_miss_frz++;
1366
1367	// DCACHE FSM signals response by reseting the request flip-flop
1368	if (not r_icache_tlb_miss_req.read())
1369	{
1370	if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated
1371	{
1372	r_icache_tlb_rsp_error = false;
1373	m_irsp.error = true;
1374	m_irsp.valid = true;
1375	r_icache_fsm = ICACHE_IDLE;
1376	}
1377	else // tlb updated : return to IDLE state
1378	{
1379	r_icache_fsm = ICACHE_IDLE;
1380	}
1381	}
1382	break;
1383	}
1384	//////////////////////////
1385	case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries
1386	{
1387	r_itlb.flush();
1388	r_dcache_xtn_req = false;
1389	r_icache_fsm = ICACHE_IDLE;
1390	break;
1391	}
1392	////////////////////////////
1393	case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using
1394	// r_icache_flush_count as a slot counter,
1395	// looping in this state until all slots are visited.
1396	// It can require two cycles per slot:
1397	// We test here the slot state, and make the actual inval
1398	// (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
1399	// A cleanup request is generated for each valid line
1400	{
1401	// coherence clack interrupt
1402	if (r_icache_clack_req.read())
1403	{
1404	r_icache_fsm = ICACHE_CC_CHECK;
1405	r_icache_fsm_save = r_icache_fsm.read();
1406	break;
1407	}
1408
1409	// coherence request (from CC_RECEIVE FSM)
1410	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1411	{
1412	r_icache_fsm = ICACHE_CC_CHECK;
1413	r_icache_fsm_save = r_icache_fsm.read();
1414	break;
1415	}
1416
1417	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent
1418	{
1419	int state;
1420	paddr_t tag;
1421	size_t way = r_icache_flush_count.read() / m_icache_sets;
1422	size_t set = r_icache_flush_count.read() % m_icache_sets;
1423
1424	#ifdef INSTRUMENTATION
1425	m_cpt_icache_dir_read++;
1426	#endif
1427	r_icache.read_dir(way,
1428	set,
1429	&tag,
1430	&state);
1431
1432	if (state == CACHE_SLOT_STATE_VALID) // inval required
1433	{
1434	// request cleanup
1435	r_icache_cc_send_req = true;
1436	r_icache_cc_send_nline = tag * m_icache_sets + set;
1437	r_icache_cc_send_way = way;
1438	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1439
1440	// goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
1441	r_icache_miss_way = way;
1442	r_icache_miss_set = set;
1443	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO;
1444	}
1445	else if (r_icache_flush_count.read() ==
1446	(m_icache_sets*m_icache_ways - 1)) // last slot
1447	{
1448	r_dcache_xtn_req = false;
1449	m_drsp.valid = true;
1450	r_icache_fsm = ICACHE_IDLE;
1451	}
1452
1453	// saturation counter, to have the same last slot condition
1454	// in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
1455	if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1))
1456	{
1457	r_icache_flush_count = r_icache_flush_count.read() + 1;
1458	}
1459	}
1460	break;
1461	}
1462	///////////////////////////////
1463	case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush
1464	{
1465	size_t way = r_icache_miss_way.read();
1466	size_t set = r_icache_miss_set.read();
1467
1468	#ifdef INSTRUMENTATION
1469	m_cpt_icache_dir_write++;
1470	#endif
1471
1472	r_icache.write_dir(way,
1473	set,
1474	CACHE_SLOT_STATE_ZOMBI);
1475
1476	if (r_icache_flush_count.read() ==
1477	(m_icache_sets*m_icache_ways - 1)) // last slot
1478	{
1479	r_dcache_xtn_req = false;
1480	m_drsp.valid = true;
1481	r_icache_fsm = ICACHE_IDLE;
1482	}
1483	else
1484	{
1485	r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
1486	}
1487	break;
1488	}
1489
1490	//////////////////////////
1491	case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
1492	// stored in the r_dcache_save_wdata register
1493	{
1494	r_itlb.inval(r_dcache_save_wdata.read());
1495	r_dcache_xtn_req = false;
1496	r_icache_fsm = ICACHE_IDLE;
1497	break;
1498	}
1499	///////////////////////////////
1500	case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
1501	// requires 3 cycles (in case of hit on itlb and icache).
1502	// In this state, access TLB to translate virtual address
1503	// stored in the r_dcache_save_wdata register.
1504	{
1505	paddr_t paddr;
1506	bool hit;
1507
1508	// read physical address in TLB when MMU activated
1509	if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated
1510	{
1511
1512	#ifdef INSTRUMENTATION
1513	m_cpt_itlb_read++;
1514	#endif
1515	hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr);
1516	}
1517	else // itlb not activated
1518	{
1519	paddr = (paddr_t) r_dcache_save_wdata.read();
1520	hit = true;
1521	}
1522
1523	if (hit) // continue the selective inval process
1524	{
1525	r_icache_vci_paddr = paddr;
1526	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
1527	}
1528	else // miss : send a request to DCACHE FSM
1529	{
1530
1531	#ifdef INSTRUMENTATION
1532	m_cpt_itlb_miss++;
1533	#endif
1534	r_icache_tlb_miss_req = true;
1535	r_icache_vaddr_save = r_dcache_save_wdata.read();
1536	r_icache_fsm = ICACHE_TLB_WAIT;
1537	}
1538	break;
1539	}
1540	///////////////////////////////
1541	case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
1542	// require 2 cycles. In this state, we read directory
1543	// with address stored in r_icache_vci_paddr register.
1544	{
1545	int state;
1546	size_t way;
1547	size_t set;
1548	size_t word;
1549
1550	#ifdef INSTRUMENTATION
1551	m_cpt_icache_dir_read++;
1552	#endif
1553	r_icache.read_dir(r_icache_vci_paddr.read(),
1554	&state,
1555	&way,
1556	&set,
1557	&word);
1558
1559	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
1560	{
1561	r_icache_miss_way = way;
1562	r_icache_miss_set = set;
1563	r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO;
1564	}
1565	else // miss : acknowlege the XTN request and return
1566	{
1567	r_dcache_xtn_req = false;
1568	r_icache_fsm = ICACHE_IDLE;
1569	}
1570	break;
1571	}
1572	///////////////////////////////
1573	case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval
1574	{
1575	if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request not sent
1576	{
1577
1578	#ifdef INSTRUMENTATION
1579	m_cpt_icache_dir_write++;
1580	#endif
1581	r_icache.write_dir(r_icache_miss_way.read(),
1582	r_icache_miss_set.read(),
1583	CACHE_SLOT_STATE_ZOMBI);
1584
1585	// request cleanup
1586	r_icache_cc_send_req = true;
1587	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1588	r_icache_cc_send_way = r_icache_miss_way.read();
1589	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1590
1591	// acknowledge the XTN request and return
1592	r_dcache_xtn_req = false;
1593	r_icache_fsm = ICACHE_IDLE;
1594	}
1595	break;
1596	}
1597	////////////////////////
1598	case ICACHE_MISS_SELECT: // Try to select a slot in associative set,
1599	// Waiting in this state if no slot available.
1600	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
1601	// we send the cleanup request in this state.
1602	// If not, a r_icache_cleanup_victim_req flip-flop is
1603	// utilized for saving this cleanup request, and it will be sent later
1604	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
1605	// The r_icache_miss_clack flip-flop is set
1606	// when a cleanup is required
1607	{
1608	if (m_ireq.valid) m_cost_ins_miss_frz++;
1609
1610	// coherence clack interrupt
1611	if (r_icache_clack_req.read())
1612	{
1613	r_icache_fsm = ICACHE_CC_CHECK;
1614	r_icache_fsm_save = r_icache_fsm.read();
1615	break;
1616	}
1617
1618	// coherence interrupt
1619	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1620	{
1621	r_icache_fsm = ICACHE_CC_CHECK;
1622	r_icache_fsm_save = r_icache_fsm.read();
1623	break;
1624	}
1625
1626
1627	bool found;
1628	bool cleanup;
1629	size_t way;
1630	size_t set;
1631	paddr_t victim;
1632
1633	#ifdef INSTRUMENTATION
1634	m_cpt_icache_dir_read++;
1635	#endif
1636	r_icache.read_select(r_icache_vci_paddr.read(),
1637	&victim,
1638	&way,
1639	&set,
1640	&found,
1641	&cleanup);
1642	if (not found)
1643	{
1644	break;
1645	}
1646	else
1647	{
1648	r_icache_miss_way = way;
1649	r_icache_miss_set = set;
1650
1651	if (cleanup)
1652	{
1653	if (not r_icache_cc_send_req.read())
1654	{
1655	r_icache_cc_send_req = true;
1656	r_icache_cc_send_nline = victim;
1657	r_icache_cc_send_way = way;
1658	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1659	}
1660	else
1661	{
1662	r_icache_cleanup_victim_req = true;
1663	r_icache_cleanup_victim_nline = victim;
1664	}
1665
1666	r_icache_miss_clack = true;
1667	r_icache_fsm = ICACHE_MISS_CLEAN;
1668	}
1669	else
1670	{
1671	r_icache_fsm = ICACHE_MISS_WAIT;
1672	}
1673
1674	#if DEBUG_ICACHE
1675	if (m_debug_icache_fsm)
1676	{
1677	std::cout << " <PROC " << name()
1678	<< " ICACHE_MISS_SELECT> Select a slot:" << std::dec
1679	<< " / WAY = " << way
1680	<< " / SET = " << set;
1681	if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
1682	else std::cout << std::endl;
1683	}
1684	#endif
1685	}
1686	break;
1687	}
1688	///////////////////////
1689	case ICACHE_MISS_CLEAN: // switch the slot to zombi state
1690	{
1691	if (m_ireq.valid) m_cost_ins_miss_frz++;
1692
1693	#ifdef INSTRUMENTATION
1694	m_cpt_icache_dir_write++;
1695	#endif
1696	r_icache.write_dir(r_icache_miss_way.read(),
1697	r_icache_miss_set.read(),
1698	CACHE_SLOT_STATE_ZOMBI);
1699	#if DEBUG_ICACHE
1700	if (m_debug_icache_fsm)
1701	{
1702	std::cout << " <PROC " << name()
1703	<< " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
1704	<< " / WAY = " << r_icache_miss_way.read()
1705	<< " / SET = " << r_icache_miss_set.read() << std::endl;
1706	}
1707	#endif
1708
1709	r_icache_fsm = ICACHE_MISS_WAIT;
1710	break;
1711	}
1712	//////////////////////
1713	case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
1714	{
1715	if (m_ireq.valid) m_cost_ins_miss_frz++;
1716
1717	// send cleanup victim request
1718	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1719	{
1720	r_icache_cc_send_req = true;
1721	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1722	r_icache_cc_send_way = r_icache_miss_way;
1723	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1724	r_icache_cleanup_victim_req = false;
1725	}
1726
1727	// coherence clack interrupt
1728	if (r_icache_clack_req.read())
1729	{
1730	r_icache_fsm = ICACHE_CC_CHECK;
1731	r_icache_fsm_save = r_icache_fsm.read();
1732	break;
1733	}
1734
1735	// coherence interrupt
1736	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1737	{
1738	r_icache_fsm = ICACHE_CC_CHECK;
1739	r_icache_fsm_save = r_icache_fsm.read();
1740	break;
1741	}
1742
1743	if (r_vci_rsp_ins_error.read()) // bus error
1744	{
1745	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1746	r_mmu_ibvar = r_icache_vaddr_save.read();
1747	m_irsp.valid = true;
1748	m_irsp.error = true;
1749	r_vci_rsp_ins_error = false;
1750	r_icache_fsm = ICACHE_IDLE;
1751	}
1752	else if (r_vci_rsp_fifo_icache.rok()) // response available
1753	{
1754	r_icache_miss_word = 0;
1755	r_icache_fsm = ICACHE_MISS_DATA_UPDT;
1756	}
1757	break;
1758	}
1759	///////////////////////////
1760	case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle)
1761	{
1762	if (m_ireq.valid) m_cost_ins_miss_frz++;
1763
1764	if (r_vci_rsp_fifo_icache.rok()) // response available
1765	{
1766
1767	#ifdef INSTRUMENTATION
1768	m_cpt_icache_data_write++;
1769	#endif
1770	r_icache.write(r_icache_miss_way.read(),
1771	r_icache_miss_set.read(),
1772	r_icache_miss_word.read(),
1773	r_vci_rsp_fifo_icache.read());
1774	#if DEBUG_ICACHE
1775	if (m_debug_icache_fsm)
1776	{
1777	std::cout << " <PROC " << name()
1778	<< " ICACHE_MISS_DATA_UPDT> Write one word:"
1779	<< " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
1780	<< " WAY = " << r_icache_miss_way.read()
1781	<< " SET = " << r_icache_miss_set.read()
1782	<< " WORD = " << r_icache_miss_word.read() << std::endl;
1783	}
1784	#endif
1785	vci_rsp_fifo_icache_get = true;
1786	r_icache_miss_word = r_icache_miss_word.read() + 1;
1787
1788	if (r_icache_miss_word.read() == m_icache_words - 1) // last word
1789	{
1790	r_icache_fsm = ICACHE_MISS_DIR_UPDT;
1791	}
1792	}
1793	break;
1794	}
1795	//////////////////////////
1796	case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted,
1797	// and the cleanup ack has not been received,
1798	// as indicated by r_icache_miss_clack.
1799	// - If no matching coherence request (r_icache_miss_inval)
1800	// switch directory slot to VALID state.
1801	// - If matching coherence request, switch directory slot
1802	// to ZOMBI state, and send a cleanup request.
1803	{
1804	if (m_ireq.valid ) m_cost_ins_miss_frz++;
1805
1806	// send cleanup victim request
1807	if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
1808	{
1809	r_icache_cc_send_req = true;
1810	r_icache_cc_send_nline = r_icache_cleanup_victim_nline;
1811	r_icache_cc_send_way = r_icache_miss_way;
1812	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1813	r_icache_cleanup_victim_req = false;
1814	}
1815
1816	// coherence clack interrupt
1817	if (r_icache_clack_req.read())
1818	{
1819	r_icache_fsm = ICACHE_CC_CHECK;
1820	r_icache_fsm_save = r_icache_fsm.read();
1821	break;
1822	}
1823
1824	// coherence interrupt
1825	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
1826	{
1827	r_icache_fsm = ICACHE_CC_CHECK;
1828	r_icache_fsm_save = r_icache_fsm.read();
1829	break;
1830	}
1831
1832	if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line
1833	{
1834	if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup
1835	{
1836	if (not r_icache_cc_send_req.read())
1837	{
1838	r_icache_miss_inval = false;
1839	// request cleanup
1840	r_icache_cc_send_req = true;
1841	r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
1842	r_icache_cc_send_way = r_icache_miss_way.read();
1843	r_icache_cc_send_type = CC_TYPE_CLEANUP;
1844
1845	#ifdef INSTRUMENTATION
1846	m_cpt_icache_dir_write++;
1847	#endif
1848	r_icache.write_dir(r_icache_vci_paddr.read(),
1849	r_icache_miss_way.read(),
1850	r_icache_miss_set.read(),
1851	CACHE_SLOT_STATE_ZOMBI);
1852	#if DEBUG_ICACHE
1853	if (m_debug_icache_fsm)
1854	{
1855	std::cout << " <PROC " << name()
1856	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
1857	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1858	<< " WAY = " << std::dec << r_icache_miss_way.read()
1859	<< " SET = " << r_icache_miss_set.read() << std::endl;
1860	}
1861	#endif
1862	}
1863	else
1864	break;
1865	}
1866	else // Switch slot to VALID state
1867	{
1868
1869	#ifdef INSTRUMENTATION
1870	m_cpt_icache_dir_write++;
1871	#endif
1872	r_icache.write_dir(r_icache_vci_paddr.read(),
1873	r_icache_miss_way.read(),
1874	r_icache_miss_set.read(),
1875	CACHE_SLOT_STATE_VALID);
1876	#if DEBUG_ICACHE
1877	if (m_debug_icache_fsm)
1878	{
1879	std::cout << " <PROC " << name()
1880	<< " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
1881	<< " PADDR = " << std::hex << r_icache_vci_paddr.read()
1882	<< " WAY = " << std::dec << r_icache_miss_way.read()
1883	<< " SET = " << r_icache_miss_set.read() << std::endl;
1884	}
1885	#endif
1886	}
1887
1888	r_icache_fsm = ICACHE_IDLE;
1889	}
1890	break;
1891	}
1892	////////////////////
1893	case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
1894	{
1895	// coherence clack interrupt
1896	if (r_icache_clack_req.read())
1897	{
1898	r_icache_fsm = ICACHE_CC_CHECK;
1899	r_icache_fsm_save = r_icache_fsm.read();
1900	break;
1901	}
1902
1903	// coherence interrupt
1904	if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
1905	{
1906	r_icache_fsm = ICACHE_CC_CHECK;
1907	r_icache_fsm_save = r_icache_fsm.read();
1908	break;
1909	}
1910
1911	if (r_vci_rsp_ins_error.read()) // bus error
1912	{
1913	r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS;
1914	r_mmu_ibvar = m_ireq.addr;
1915	r_vci_rsp_ins_error = false;
1916	m_irsp.valid = true;
1917	m_irsp.error = true;
1918	r_icache_fsm = ICACHE_IDLE;
1919	}
1920	else if (r_vci_rsp_fifo_icache.rok()) // instruction available
1921	{
1922	vci_rsp_fifo_icache_get = true;
1923	r_icache_fsm = ICACHE_IDLE;
1924	if (m_ireq.valid and
1925	(m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified
1926	{
1927	m_irsp.valid = true;
1928	m_irsp.instruction = r_vci_rsp_fifo_icache.read();
1929	}
1930	}
1931	break;
1932	}
1933	/////////////////////
1934	case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm
1935	// handling coherence requests.
1936	// if there is a matching pending miss, it is
1937	// signaled in the r_icache_miss_inval flip-flop.
1938	// The return state is defined in r_icache_fsm_save.
1939	{
1940	paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
1941	paddr_t mask = ~((m_icache_words << 2) - 1);
1942
1943	// CLACK handler
1944	// We switch the directory slot to EMPTY state
1945	// and reset r_icache_miss_clack if the cleanup ack
1946	// is matching a pending miss.
1947	if (r_icache_clack_req.read())
1948	{
1949
1950	if (m_ireq.valid) m_cost_ins_miss_frz++;
1951
1952	#ifdef INSTRUMENTATION
1953	m_cpt_icache_dir_write++;
1954	#endif
1955	r_icache.write_dir(0,
1956	r_icache_clack_way.read(),
1957	r_icache_clack_set.read(),
1958	CACHE_SLOT_STATE_EMPTY);
1959
1960	if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and
1961	(r_icache_miss_way.read() == r_icache_clack_way.read()))
1962	{
1963	r_icache_miss_clack = false;
1964	}
1965
1966	r_icache_clack_req = false;
1967
1968	// return to cc_save state
1969	r_icache_fsm = r_icache_fsm_save.read();
1970
1971	#if DEBUG_ICACHE
1972	if (m_debug_icache_fsm)
1973	{
1974	std::cout << " <PROC " << name()
1975	<< " ICACHE_CC_CHECK> CC_TYPE_CLACK slot returns to empty state"
1976	<< " set = " << r_icache_clack_set.read()
1977	<< " / way = " << r_icache_clack_way.read() << std::endl;
1978	}
1979	#endif
1980
1981	break;
1982	}
1983
1984	assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
1985
1986	// Match between MISS address and CC address
1987	if (r_cc_receive_icache_req.read() and
1988	((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or
1989	(r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or
1990	(r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
1991	((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
1992	{
1993	// signaling the matching
1994	r_icache_miss_inval = true;
1995
1996	// in case of update, go to CC_UPDT
1997	// JUST TO POP THE FIFO
1998	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
1999	{
2000	r_icache_fsm = ICACHE_CC_UPDT;
2001	r_icache_cc_word = r_cc_receive_word_idx.read();
2002
2003	// just pop the fifo , don't write in icache
2004	r_icache_cc_need_write = false;
2005	}
2006	// the request is dealt with
2007	else
2008	{
2009	r_cc_receive_icache_req = false;
2010	r_icache_fsm = r_icache_fsm_save.read();
2011	}
2012	#if DEBUG_ICACHE
2013	if (m_debug_icache_fsm)
2014	{
2015	std::cout << " <PROC " << name()
2016	<< " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
2017	<< " PADDR = " << std::hex << paddr << std::endl;
2018	}
2019	#endif
2020	}
2021
2022	// CC request handler
2023
2024	int state = 0;
2025	size_t way = 0;
2026	size_t set = 0;
2027	size_t word = 0;
2028
2029	#ifdef INSTRUMENTATION
2030	m_cpt_icache_dir_read++;
2031	#endif
2032	r_icache.read_dir(paddr,
2033	&state,
2034	&way,
2035	&set,
2036	&word);
2037
2038	r_icache_cc_way = way;
2039	r_icache_cc_set = set;
2040
2041	if (state == CACHE_SLOT_STATE_VALID) // hit
2042	{
2043	// need to update the cache state
2044	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update
2045	{
2046	r_icache_cc_need_write = true;
2047	r_icache_fsm = ICACHE_CC_UPDT;
2048	r_icache_cc_word = r_cc_receive_word_idx.read();
2049	}
2050	else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
2051	{
2052	r_icache_fsm = ICACHE_CC_INVAL;
2053	}
2054	}
2055	else // miss
2056	{
2057	// multicast acknowledgement required in case of update
2058	if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
2059	{
2060	r_icache_fsm = ICACHE_CC_UPDT;
2061	r_icache_cc_word = r_cc_receive_word_idx.read();
2062
2063	// just pop the fifo , don't write in icache
2064	r_icache_cc_need_write = false;
2065	}
2066	else // No response needed
2067	{
2068	r_cc_receive_icache_req = false;
2069	r_icache_fsm = r_icache_fsm_save.read();
2070	}
2071	}
2072	break;
2073	}
2074	/////////////////////
2075	case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state
2076	{
2077	assert (not r_icache_cc_send_req.read() &&
2078	"ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
2079	"must not be set");
2080
2081	#ifdef INSTRUMENTATION
2082	m_cpt_icache_dir_read++;
2083	#endif
2084
2085	// Switch slot state to ZOMBI and send CLEANUP command
2086	r_icache.write_dir(r_icache_cc_way.read(),
2087	r_icache_cc_set.read(),
2088	CACHE_SLOT_STATE_ZOMBI);
2089
2090	// coherence request completed
2091	r_icache_cc_send_req = true;
2092	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2093	r_icache_cc_send_way = r_icache_cc_way.read();
2094	r_icache_cc_send_type = CC_TYPE_CLEANUP;
2095
2096	r_icache_fsm = r_icache_fsm_save.read();
2097
2098	#if DEBUG_ICACHE
2099	if (m_debug_icache_fsm)
2100	{
2101	std::cout << " <PROC " << name()
2102	<< " ICACHE_CC_INVAL> slot returns to ZOMBI state"
2103	<< " set = " << r_icache_cc_set.read()
2104	<< " / way = " << r_icache_cc_way.read() << std::endl;
2105	}
2106	#endif
2107
2108	break;
2109	}
2110	////////////////////
2111	case ICACHE_CC_UPDT: // hit update : write one word per cycle
2112	{
2113	assert (not r_icache_cc_send_req.read() &&
2114	"ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
2115	"must not be set");
2116
2117	if (not r_cc_receive_updt_fifo_be.rok()) break;
2118
2119
2120	size_t word = r_icache_cc_word.read();
2121	size_t way = r_icache_cc_way.read();
2122	size_t set = r_icache_cc_set.read();
2123
2124	if (r_icache_cc_need_write.read())
2125	{
2126	r_icache.write(way,
2127	set,
2128	word,
2129	r_cc_receive_updt_fifo_data.read(),
2130	r_cc_receive_updt_fifo_be.read());
2131
2132	r_icache_cc_word = word + 1;
2133
2134	#ifdef INSTRUMENTATION
2135	m_cpt_icache_data_write++;
2136	#endif
2137
2138	#if DEBUG_ICACHE
2139	if (m_debug_icache_fsm)
2140	{
2141	std::cout << " <PROC " << name()
2142	<< " ICACHE_CC_UPDT> Write one word "
2143	<< " set = " << r_icache_cc_set.read()
2144	<< " / way = " << r_icache_cc_way.read()
2145	<< " / word = " << r_icache_cc_word.read() << std::endl;
2146	}
2147	#endif
2148	}
2149
2150	if (r_cc_receive_updt_fifo_eop.read()) // last word
2151	{
2152	// no need to write in the cache anymore
2153	r_icache_cc_need_write = false;
2154
2155	// coherence request completed
2156	r_cc_receive_icache_req = false;
2157
2158	// request multicast acknowledgement
2159	r_icache_cc_send_req = true;
2160	r_icache_cc_send_nline = r_cc_receive_icache_nline.read();
2161	r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read();
2162	r_icache_cc_send_type = CC_TYPE_MULTI_ACK;
2163
2164	r_icache_fsm = r_icache_fsm_save.read();
2165	}
2166	//consume fifo if not eop
2167	cc_receive_updt_fifo_get = true;
2168
2169	break;
2170	}
2171
2172	} // end switch r_icache_fsm
2173
2174	////////////////////////////////////////////////////////////////////////////////////
2175	// DCACHE FSM
2176	//
2177	// 1/ Coherence operations
2178	// They are handled as interrupts generated by the CC_RECEIVE FSM.
2179	// - There is a coherence request when r_tgt_dcache_req is set.
2180	// They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT
2181	// and SC_WAIT states.
2182	// - There is a cleanup acknowledge request when r_cleanup_dcache_req is set.
2183	// They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT,
2184	// MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states.
2185	// - For both types of requests, actions associated to the pre-empted state
2186	// are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK
2187	// or CC_CLACK) to execute the requested coherence operation, and returns
2188	// to the pre-empted state.
2189	//
2190	// 2/ TLB miss
2191	// The page tables are generally cacheable.
2192	// In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated
2193	// sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE,
2194	// this sub-fsm implement the table-walk...
2195	//
2196	// 3/ processor requests
2197	// Processor requests are taken in IDLE state only.
2198	// The IDLE state implements a two stages pipe-line to handle write bursts:
2199	// - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid).
2200	// - The registration in wbuf and the dcache update is done in stage P1
2201	// (if the processor request is a write).
2202	// The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define
2203	// the operations that must be done in P1 stage, and the access type
2204	// (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req.
2205	// READ requests are delayed if a cache update is requested.
2206	// WRITE or SC requests can require a PTE Dirty bit update (in memory),
2207	// that is done (before handling the processor request) by a dedicated sub-fsm.
2208	// If a PTE is modified, both the itlb and dtlb are selectively, but sequencially
2209	// cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state).
2210	//
2211	// 4/ Atomic instructions LL/SC
2212	// The LL/SC address are non cacheable (systematic access to memory).
2213	// The llsc buffer contains a registration for an active LL/SC operation
2214	// (with an address, a registration key, an aging counter and a valid bit).
2215	// - LL requests from the processor are transmitted as a one flit VCI command
2216	// (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must
2217	// be 8 as the response is 2 flits long (data and registration key)
2218	// - SC requests from the processor are systematically transmitted to the
2219	// memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC
2220	// as PKTID value). The first flit contains the registration key, the second
2221	// flit contains the data to write in case of success.
2222	// The cache is not updated, as this is done in case of success by the
2223	// coherence transaction.
2224	//
2225	// 5/ Non cacheable access:
2226	// This component implement a strong order between non cacheable access
2227	// (read or write) : A new non cacheable VCI transaction starts only when
2228	// the previous non cacheable transaction is completed. After send the VCI
2229	// transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
2230	// So the processor is blocked until the respone arrives in CACHE L1.
2231	//
2232	// 6/ Error handling:
2233	// When the MMU is not activated, Read Bus Errors are synchronous events,
2234	// Some Write Bus Errors are synchronous events when the request is a non cacheable access
2235	// but some Write Bus Errors are asynchronous events when the request is cacheable access
2236	// (processor is not frozen).
2237	// - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
2238	// r_vci_rsp_data_error flip-flop, without writing any data in the
2239	// r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
2240	// by the DCACHE FSM.
2241	// - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
2242	// the asynchronous error using the setWriteBerr() method.
2243	// When the MMU is activated bus error are rare events, as the MMU
2244	// checks the physical address before the VCI transaction starts.
2245	////////////////////////////////////////////////////////////////////////////////////////
2246
2247	// default value for m_drsp
2248	m_drsp.valid = false;
2249	m_drsp.error = false;
2250	m_drsp.rdata = 0;
2251
2252	// watchdog timeout signal
2253	// when wdt_max is zero, the watchdog mechanism is deactivated.
2254	bool dcache_watchdog_timeout = (r_dcache_wdt_max.read() > 0) &&
2255	(r_dcache_wdt.read() == r_dcache_wdt_max.read());
2256
2257	switch (r_dcache_fsm.read())
2258	{
2259	case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
2260	// 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN
2261	// 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK
2262	// 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS
2263	// 4) XTN request (processor) => DCACHE_XTN_*
2264	// 5) DTLB miss (processor) => DCACHE_TLB_MISS
2265	// 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE
2266	// 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT
2267	// 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT
2268	// 9) LL access (processor) => DCACHE_LL_WAIT
2269	// 10) SC access (processor) => DCACHE_SC_WAIT
2270	//
2271	// There is a fixed priority to handle requests to DCACHE:
2272	// 1/ the ITLB/DTLB invalidate requests
2273	// 2/ the coherence requests,
2274	// 3/ the processor requests (including DTLB miss),
2275	// 4/ the ITLB miss requests,
2276	// The address space processor request are handled as follows:
2277	// - WRITE request is blocked if the Dirty bit mus be set.
2278	// If DTLB hit, the P1 stage is activated (writes WBUF, and
2279	// updates DCACHE if DCACHE hit) & processor request acknowledged.
2280	// - READ request generate a simultaneouss access to DCACHE.DATA
2281	// and DCACHE.DIR, but is delayed if DCACHE update required.
2282	//
2283	// There is 4 configurations defining the access type to
2284	// DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the
2285	// dreq.valid (dreq) and r_dcache_updt_req (updt) signals:
2286	// dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA /
2287	// 0 / 0 / NOP / NOP / NOP /
2288	// 0 / 1 / NOP / NOP / WRITE /
2289	// 1 / 0 / READ / READ / NOP /
2290	// 1 / 1 / READ / READ / WRITE /
2291	// Those two registers are set at each cycle from the 3 signals
2292	// updt_request, wbuf_request, wbuf_write_miss.
2293	{
2294	paddr_t paddr;
2295	pte_info_t tlb_flags;
2296	size_t tlb_way;
2297	size_t tlb_set;
2298	paddr_t tlb_nline = 0;
2299	size_t cache_way;
2300	size_t cache_set;
2301	size_t cache_word;
2302	uint32_t cache_rdata = 0;
2303	bool tlb_hit = false;
2304	int cache_state = CACHE_SLOT_STATE_EMPTY;
2305
2306	bool tlb_inval_required = false; // request TLB inval after cache update
2307	bool wbuf_write_miss = false; // miss a WBUF write request
2308	bool updt_request = false; // request DCACHE update in P1 stage
2309	bool wbuf_request = false; // request WBUF write in P1 stage
2310
2311	// physical address computation : systematic DTLB access if activated
2312	paddr = (paddr_t) m_dreq.addr;
2313	if (m_dreq.valid)
2314	{
2315	if (r_mmu_mode.read() & DATA_TLB_MASK) // DTLB activated
2316	{
2317	tlb_hit = r_dtlb.translate(m_dreq.addr,
2318	&paddr,
2319	&tlb_flags,
2320	&tlb_nline,
2321	&tlb_way,
2322	&tlb_set);
2323	#ifdef INSTRUMENTATION
2324	m_cpt_dtlb_read++;
2325	#endif
2326	}
2327	else // identity mapping
2328	{
2329	// we take into account the paddr extension
2330	if (vci_param::N > 32)
2331	paddr = paddr \| ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
2332	}
2333	} // end physical address computation
2334
2335	// systematic DCACHE access depending on r_dcache_updt_req (if activated)
2336	if (r_mmu_mode.read() & DATA_CACHE_MASK)
2337	{
2338
2339	if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA
2340	{
2341	r_dcache.read_dir(paddr,
2342	&cache_state,
2343	&cache_way,
2344	&cache_set,
2345	&cache_word);
2346
2347	r_dcache.write(r_dcache_save_cache_way.read(),
2348	r_dcache_save_cache_set.read(),
2349	r_dcache_save_cache_word.read(),
2350	r_dcache_save_wdata.read(),
2351	r_dcache_save_be.read());
2352	#ifdef INSTRUMENTATION
2353	m_cpt_dcache_dir_read++;
2354	m_cpt_dcache_data_write++;
2355	#endif
2356	}
2357	else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA
2358	{
2359	r_dcache.read(paddr,
2360	&cache_rdata,
2361	&cache_way,
2362	&cache_set,
2363	&cache_word,
2364	&cache_state);
2365
2366	#ifdef INSTRUMENTATION
2367	m_cpt_dcache_dir_read++;
2368	m_cpt_dcache_data_read++;
2369	#endif
2370	}
2371	else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA
2372	{
2373	r_dcache.write(r_dcache_save_cache_way.read(),
2374	r_dcache_save_cache_set.read(),
2375	r_dcache_save_cache_word.read(),
2376	r_dcache_save_wdata.read(),
2377	r_dcache_save_be.read());
2378	#ifdef INSTRUMENTATION
2379	m_cpt_dcache_data_write++;
2380	#endif
2381	}
2382	} // end dcache access
2383
2384	// DCACHE update in P1 stage can require ITLB / DTLB inval or flush
2385	if (r_dcache_updt_req.read())
2386	{
2387	size_t way = r_dcache_save_cache_way.read();
2388	size_t set = r_dcache_save_cache_set.read();
2389
2390	if (r_dcache_in_tlb[way * m_dcache_sets + set])
2391	{
2392	tlb_inval_required = true;
2393	r_dcache_tlb_inval_set = 0;
2394	r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >>
2395	(uint32_log2(m_dcache_words << 2));
2396	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
2397	}
2398	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
2399	{
2400	r_itlb.reset();
2401	r_dtlb.reset();
2402	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
2403	}
2404
2405	#if DEBUG_DCACHE
2406	if (m_debug_dcache_fsm)
2407	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2408	<< " Cache update in P1 stage" << std::dec
2409	<< " / WAY = " << r_dcache_save_cache_way.read()
2410	<< " / SET = " << r_dcache_save_cache_set.read()
2411	<< " / WORD = " << r_dcache_save_cache_word.read() << std::hex
2412	<< " / WDATA = " << r_dcache_save_wdata.read()
2413	<< " / BE = " << r_dcache_save_be.read() << std::endl;
2414	#endif
2415	} // end test TLB inval
2416
2417	// Try WBUF update in P1 stage
2418	// Miss if the write request is non cacheable, and there is a pending
2419	// non cacheable write, or if the write buffer is full.
2420	if (r_dcache_wbuf_req.read())
2421	{
2422	bool wok = r_wbuf.write(r_dcache_save_paddr.read(),
2423	r_dcache_save_be.read(),
2424	r_dcache_save_wdata.read(),
2425	true);
2426	#ifdef INSTRUMENTATION
2427	m_cpt_wbuf_write++;
2428	#endif
2429	if (not wok ) // miss if write buffer full
2430	{
2431	wbuf_write_miss = true;
2432	}
2433	} // end WBUF update
2434
2435	// Computing the response to processor,
2436	// and the next value for r_dcache_fsm
2437
2438	// itlb/dtlb invalidation self-request
2439	if (tlb_inval_required)
2440	{
2441	r_dcache_fsm_scan_save = r_dcache_fsm.read();
2442	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
2443	}
2444
2445	// coherence clack request (from DSPIN CLACK)
2446	else if (r_dcache_clack_req.read())
2447	{
2448	r_dcache_fsm = DCACHE_CC_CHECK;
2449	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2450	}
2451	// coherence request (from CC_RECEIVE FSM)
2452	else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
2453	{
2454	r_dcache_fsm = DCACHE_CC_CHECK;
2455	r_dcache_fsm_cc_save = r_dcache_fsm.read();
2456	}
2457
2458	// processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE)
2459	// we don't take the processor request, and registers
2460	// are frozen in case of wbuf_write_miss
2461	else if (m_dreq.valid and not wbuf_write_miss)
2462	{
2463	// register processor request and DCACHE response
2464	r_dcache_save_vaddr = m_dreq.addr;
2465	r_dcache_save_be = m_dreq.be;
2466	r_dcache_save_wdata = m_dreq.wdata;
2467	r_dcache_save_paddr = paddr;
2468	r_dcache_save_cache_way = cache_way;
2469	r_dcache_save_cache_set = cache_set;
2470	r_dcache_save_cache_word = cache_word;
2471
2472	// READ XTN requests from processor
2473	// They are executed in this DCACHE_IDLE state.
2474	// The processor must not be in user mode
2475	if (m_dreq.type == iss_t::XTN_READ)
2476	{
2477	int xtn_opcode = (int) m_dreq.addr / 4;
2478
2479	// checking processor mode:
2480	if (m_dreq.mode == iss_t::MODE_USER)
2481	{
2482	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2483	r_mmu_dbvar = m_dreq.addr;
2484	m_drsp.valid = true;
2485	m_drsp.error = true;
2486	m_drsp.rdata = 0;
2487	r_dcache_fsm = DCACHE_IDLE;
2488	}
2489	else
2490	{
2491	switch (xtn_opcode)
2492	{
2493	case iss_t::XTN_INS_ERROR_TYPE:
2494	m_drsp.rdata = r_mmu_ietr.read();
2495	m_drsp.valid = true;
2496	m_drsp.error = false;
2497	break;
2498
2499	case iss_t::XTN_DATA_ERROR_TYPE:
2500	m_drsp.rdata = r_mmu_detr.read();
2501	m_drsp.valid = true;
2502	m_drsp.error = false;
2503	break;
2504
2505	case iss_t::XTN_INS_BAD_VADDR:
2506	m_drsp.rdata = r_mmu_ibvar.read();
2507	m_drsp.valid = true;
2508	m_drsp.error = false;
2509	break;
2510
2511	case iss_t::XTN_DATA_BAD_VADDR:
2512	m_drsp.rdata = r_mmu_dbvar.read();
2513	m_drsp.valid = true;
2514	m_drsp.error = false;
2515	break;
2516
2517	case iss_t::XTN_PTPR:
2518	m_drsp.rdata = r_mmu_ptpr.read();
2519	m_drsp.valid = true;
2520	m_drsp.error = false;
2521	break;
2522
2523	case iss_t::XTN_TLB_MODE:
2524	m_drsp.rdata = r_mmu_mode.read();
2525	m_drsp.valid = true;
2526	m_drsp.error = false;
2527	break;
2528
2529	case iss_t::XTN_MMU_PARAMS:
2530	m_drsp.rdata = r_mmu_params;
2531	m_drsp.valid = true;
2532	m_drsp.error = false;
2533	break;
2534
2535	case iss_t::XTN_MMU_RELEASE:
2536	m_drsp.rdata = r_mmu_release;
2537	m_drsp.valid = true;
2538	m_drsp.error = false;
2539	break;
2540
2541	case iss_t::XTN_MMU_WORD_LO:
2542	m_drsp.rdata = r_mmu_word_lo.read();
2543	m_drsp.valid = true;
2544	m_drsp.error = false;
2545	break;
2546
2547	case iss_t::XTN_MMU_WORD_HI:
2548	m_drsp.rdata = r_mmu_word_hi.read();
2549	m_drsp.valid = true;
2550	m_drsp.error = false;
2551	break;
2552
2553	case iss_t::XTN_DATA_PADDR_EXT:
2554	m_drsp.rdata = r_dcache_paddr_ext.read();
2555	m_drsp.valid = true;
2556	m_drsp.error = false;
2557	break;
2558
2559	case iss_t::XTN_INST_PADDR_EXT:
2560	m_drsp.rdata = r_icache_paddr_ext.read();
2561	m_drsp.valid = true;
2562	m_drsp.error = false;
2563	break;
2564
2565	case XTN_WDT_MAX:
2566	m_drsp.rdata = r_dcache_wdt_max.read();
2567	m_drsp.valid = true;
2568	m_drsp.error = false;
2569	break;
2570
2571	default:
2572	r_mmu_detr = MMU_READ_UNDEFINED_XTN;
2573	r_mmu_dbvar = m_dreq.addr;
2574	m_drsp.valid = true;
2575	m_drsp.error = true;
2576	m_drsp.rdata = 0;
2577	break;
2578	} // end switch xtn_opcode
2579	} // end else
2580	} // end if XTN_READ
2581
2582	// Handling WRITE XTN requests from processor.
2583	// They are not executed in this DCACHE_IDLE state
2584	// if they require access to the caches or the TLBs
2585	// that are already accessed.
2586	// Caches can be invalidated or flushed in user mode,
2587	// and the sync instruction can be executed in user mode
2588	else if (m_dreq.type == iss_t::XTN_WRITE)
2589	{
2590	int xtn_opcode = (int)m_dreq.addr / 4;
2591	r_dcache_xtn_opcode = xtn_opcode;
2592
2593	// checking processor mode:
2594	if ((m_dreq.mode == iss_t::MODE_USER) &&
2595	(xtn_opcode != iss_t::XTN_SYNC) &&
2596	(xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
2597	(xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
2598	(xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
2599	(xtn_opcode != iss_t::XTN_ICACHE_FLUSH))
2600	{
2601	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2602	r_mmu_dbvar = m_dreq.addr;
2603	m_drsp.valid = true;
2604	m_drsp.error = true;
2605	m_drsp.rdata = 0;
2606	r_dcache_fsm = DCACHE_IDLE;
2607	}
2608	else
2609	{
2610	switch (xtn_opcode)
2611	{
2612	case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
2613	r_dcache_xtn_req = true;
2614	r_dcache_fsm = DCACHE_XTN_SWITCH;
2615	break;
2616
2617	case iss_t::XTN_TLB_MODE: // no cache or tlb access
2618	r_mmu_mode = m_dreq.wdata;
2619	m_drsp.valid = true;
2620	r_dcache_fsm = DCACHE_IDLE;
2621	break;
2622
2623	case iss_t::XTN_DTLB_INVAL: // dtlb access
2624	r_dcache_fsm = DCACHE_XTN_DT_INVAL;
2625	break;
2626
2627	case iss_t::XTN_ITLB_INVAL: // itlb access
2628	r_dcache_xtn_req = true;
2629	r_dcache_fsm = DCACHE_XTN_IT_INVAL;
2630	break;
2631
2632	case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access
2633	r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
2634	break;
2635
2636	case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
2637	{
2638	uint64_t pa = ((uint64_t)r_mmu_word_hi.read() << 32) \|
2639	((uint64_t)r_mmu_word_lo.read());
2640
2641	r_dcache_save_paddr = (paddr_t)pa;
2642	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
2643	break;
2644	}
2645	case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
2646	r_dcache_flush_count = 0;
2647	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
2648	break;
2649
2650	case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
2651	r_dcache_xtn_req = true;
2652	r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA;
2653	break;
2654
2655	case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
2656	r_dcache_xtn_req = true;
2657	r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA;
2658	break;
2659
2660	case iss_t::XTN_ICACHE_FLUSH: // icache access
2661	r_dcache_xtn_req = true;
2662	r_dcache_fsm = DCACHE_XTN_IC_FLUSH;
2663	break;
2664
2665	case iss_t::XTN_SYNC: // wait until write buffer empty
2666	r_dcache_fsm = DCACHE_XTN_SYNC;
2667	break;
2668
2669	case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access
2670	r_mmu_word_lo = m_dreq.wdata;
2671	m_drsp.valid = true;
2672	r_dcache_fsm = DCACHE_IDLE;
2673	break;
2674
2675	case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access
2676	r_mmu_word_hi = m_dreq.wdata;
2677	m_drsp.valid = true;
2678	r_dcache_fsm = DCACHE_IDLE;
2679	break;
2680
2681	case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access
2682	r_dcache_llsc_valid = false;
2683	m_drsp.valid = true;
2684	r_dcache_fsm = DCACHE_IDLE;
2685	break;
2686
2687	case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access
2688	r_dcache_paddr_ext = m_dreq.wdata;
2689	m_drsp.valid = true;
2690	r_dcache_fsm = DCACHE_IDLE;
2691	break;
2692
2693	case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access
2694	r_dcache_xtn_req = true;
2695	r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT;
2696	break;
2697
2698	case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
2699	case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
2700	m_drsp.valid = true;
2701	r_dcache_fsm = DCACHE_IDLE;
2702	break;
2703
2704	case XTN_WDT_MAX:
2705	r_dcache_wdt_max = m_dreq.wdata;
2706	m_drsp.valid = true;
2707	r_dcache_fsm = DCACHE_IDLE;
2708	break;
2709
2710	case XTN_CC_TEST:
2711	r_dcache_to_cc_test_dest = m_dreq.wdata;
2712	r_dcache_to_cc_test_req = true;
2713	r_dcache_wdt = 0;
2714	r_dcache_fsm = DCACHE_XTN_CC_TEST;
2715	break;
2716
2717	case iss_t::XTN_DEBUG_MASK: // debug mask
2718	m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0);
2719	m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0);
2720	m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0);
2721	m_drsp.valid = true;
2722	r_dcache_fsm = DCACHE_IDLE;
2723	break;
2724
2725	default:
2726	r_mmu_detr = MMU_WRITE_UNDEFINED_XTN;
2727	r_mmu_dbvar = m_dreq.addr;
2728	m_drsp.valid = true;
2729	m_drsp.error = true;
2730	r_dcache_fsm = DCACHE_IDLE;
2731	break;
2732	} // end switch xtn_opcode
2733	} // end else
2734	} // end if XTN_WRITE
2735
2736	// Handling processor requests to address space (READ/WRITE/LL/SC)
2737	// The dtlb and dcache can be activated or not.
2738	// We compute the cacheability, and check processor request validity:
2739	// - If DTLB not activated : cacheability is defined by the segment table,
2740	// and there is no access rights checking.
2741	// - If DTLB activated : cacheability is defined by the C bit in the PTE,
2742	// and the U & W bits of the PTE are checked, as well as the DTLB hit.
2743	// Jumps to the TLB_MISS sub-fsm in case of dtlb miss.
2744	else
2745	{
2746	bool valid_req;
2747	bool cacheable;
2748
2749	if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated
2750	{
2751	valid_req = true;
2752
2753	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2754	else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
2755	}
2756	else // dtlb activated
2757	{
2758	if (tlb_hit) // tlb hit
2759	{
2760	// cacheability
2761	if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
2762	else cacheable = tlb_flags.c;
2763
2764	// access rights checking
2765	if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
2766	{
2767	if ((m_dreq.type == iss_t::DATA_READ) or
2768	(m_dreq.type == iss_t::DATA_LL))
2769	{
2770	r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
2771	}
2772	else
2773	{
2774	r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION;
2775	}
2776	valid_req = false;
2777	r_mmu_dbvar = m_dreq.addr;
2778	m_drsp.valid = true;
2779	m_drsp.error = true;
2780	m_drsp.rdata = 0;
2781	#if DEBUG_DCACHE
2782	if (m_debug_dcache_fsm)
2783	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2784	<< " HIT in dtlb, but privilege violation" << std::endl;
2785	#endif
2786	}
2787	else if (not tlb_flags.w and
2788	((m_dreq.type == iss_t::DATA_WRITE) or
2789	(m_dreq.type == iss_t::DATA_SC)))
2790	{
2791	r_mmu_detr = MMU_WRITE_ACCES_VIOLATION;
2792	valid_req = false;
2793	r_mmu_dbvar = m_dreq.addr;
2794	m_drsp.valid = true;
2795	m_drsp.error = true;
2796	m_drsp.rdata = 0;
2797	#if DEBUG_DCACHE
2798	if (m_debug_dcache_fsm)
2799	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2800	<< " HIT in dtlb, but writable violation" << std::endl;
2801	#endif
2802	}
2803	else
2804	{
2805	valid_req = true;
2806	}
2807	}
2808	else // tlb miss
2809	{
2810	valid_req = false;
2811	r_dcache_tlb_vaddr = m_dreq.addr;
2812	r_dcache_tlb_ins = false;
2813	r_dcache_fsm = DCACHE_TLB_MISS;
2814	}
2815	} // end DTLB activated
2816
2817	if (valid_req) // processor request is valid (after MMU check)
2818	{
2819	// READ request
2820	// The read requests are taken only if there is no cache update.
2821	// We request a VCI transaction to CMD FSM if miss or uncachable
2822
2823	if (((m_dreq.type == iss_t::DATA_READ))
2824	and not r_dcache_updt_req.read())
2825	{
2826	if (cacheable) // cacheable read
2827	{
2828	if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
2829	{
2830	#ifdef INSTRUMENTATION
2831	m_cpt_dcache_miss++;
2832	#endif
2833	// request a VCI DMISS transaction
2834	r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
2835
2836	r_dcache_vci_paddr = paddr;
2837	r_dcache_vci_miss_req = true;
2838	r_dcache_miss_type = PROC_MISS;
2839	r_dcache_fsm = DCACHE_MISS_SELECT;
2840	#if DEBUG_DCACHE
2841	if (m_debug_dcache_fsm)
2842	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2843	<< " READ MISS in dcache"
2844	<< " / PADDR = " << std::hex << paddr << std::endl;
2845	#endif
2846	}
2847	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
2848	{
2849	// stalled until cleanup is acknowledged
2850	r_dcache_fsm = DCACHE_IDLE;
2851	#if DEBUG_DCACHE
2852	if (m_debug_dcache_fsm)
2853	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2854	<< " Pending cleanup, stalled until cleanup acknowledge"
2855	<< " / PADDR = " << std::hex << paddr << std::endl;
2856	#endif
2857	}
2858	else // cache hit
2859	{
2860	#ifdef INSTRUMENTATION
2861	m_cpt_data_read++;
2862	#endif
2863	// returns data to processor
2864	m_drsp.valid = true;
2865	m_drsp.error = false;
2866	m_drsp.rdata = cache_rdata;
2867	#if DEBUG_DCACHE
2868	if (m_debug_dcache_fsm)
2869	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2870	<< " READ HIT in dcache"
2871	<< " : PADDR = " << std::hex << paddr
2872	<< " / DATA = " << std::hex << cache_rdata << std::endl;
2873	#endif
2874	}
2875	}
2876	else // uncacheable read
2877	{
2878	r_dcache_vci_paddr = paddr;
2879	r_dcache_vci_unc_be = m_dreq.be;
2880	r_dcache_vci_unc_write = false;
2881	r_dcache_vci_unc_req = true;
2882	r_dcache_fsm = DCACHE_UNC_WAIT;
2883
2884	// reset to 0 the watchdog timer
2885	r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
2886	r_dcache_wdt = 0;
2887	#if DEBUG_DCACHE
2888	if (m_debug_dcache_fsm)
2889	std::cout << " <PROC " << name() << " DCACHE_IDLE>"
2890	<< " READ UNCACHEABLE in dcache"
2891	<< " / PADDR = " << std::hex << paddr << std::endl;
2892	#endif
2893	}
2894	} // end READ
2895
2896	// LL request (non cachable)
2897	// We request a VCI LL transaction to CMD FSM and register
2898	// the LL/SC operation in llsc buffer.
2899	else if (m_dreq.type == iss_t::DATA_LL)
2900	{
2901	// register paddr in LLSC buffer
2902	r_dcache_llsc_paddr = paddr;
2903	r_dcache_llsc_count = LLSC_TIMEOUT;
2904	r_dcache_llsc_valid = true;
2905
2906	// request an LL VCI transaction and go to DCACHE_LL_WAIT state
2907	r_dcache_vci_ll_req = true;
2908	r_dcache_vci_paddr = paddr;
2909	r_dcache_ll_rsp_count = 0;
2910	r_dcache_fsm = DCACHE_LL_WAIT;
2911
2912	}// end LL
2913
2914	// WRITE request:
2915	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2916	// the processor and set the Dirty bit before handling the write request,
2917	// going to the DCACHE_DIRTY_GT_PTE state.
2918	// If we don't need to set the Dirty bit, we can acknowledge
2919	// the processor request, as the write arguments (including the
2920	// physical address) are registered in r_dcache_save registers,
2921	// and the write will be done in the P1 pipeline stage.
2922	else if (m_dreq.type == iss_t::DATA_WRITE)
2923	{
2924	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2925	and not tlb_flags.d) // Dirty bit must be set
2926	{
2927	// The PTE physical address is obtained from the nline value (dtlb),
2928	// and from the virtual address (word index)
2929	if (tlb_flags.b ) // PTE1
2930	{
2931	r_dcache_dirty_paddr = (paddr_t)(tlb_nline * (m_dcache_words << 2)) \|
2932	(paddr_t)((m_dreq.addr >> 19) & 0x3c);
2933	}
2934	else // PTE2
2935	{
2936	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2937	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
2938	}
2939	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
2940	}
2941	else // Write request accepted
2942	{
2943	#ifdef INSTRUMENTATION
2944	m_cpt_data_write++;
2945	#endif
2946	// cleaning llsc buffer if address matching
2947	if (paddr == r_dcache_llsc_paddr.read())
2948	r_dcache_llsc_valid = false;
2949
2950	if (not cacheable) // uncacheable write
2951	{
2952	r_dcache_vci_paddr = paddr;
2953	r_dcache_vci_wdata = m_dreq.wdata;
2954	r_dcache_vci_unc_write = true;
2955	r_dcache_vci_unc_be = m_dreq.be;
2956	r_dcache_vci_unc_req = true;
2957	r_dcache_fsm = DCACHE_UNC_WAIT;
2958
2959	// reset to 0 the watchdog timer
2960	r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
2961	r_dcache_wdt = 0;
2962	}
2963	else
2964	{
2965	// response to processor
2966	m_drsp.valid = true;
2967	// activating P1 stage
2968	wbuf_request = true;
2969	updt_request = (cache_state == CACHE_SLOT_STATE_VALID);
2970	}
2971	}
2972	} // end WRITE
2973
2974	// SC request:
2975	// If the TLB is activated and the PTE Dirty bit is not set, we stall
2976	// the processor and set the Dirty bit before handling the write request,
2977	// going to the DCACHE_DIRTY_GT_PTE state.
2978	// If we don't need to set the Dirty bit, we test the llsc buffer:
2979	// If failure, we send a negative response to processor.
2980	// If success, we request a SC transaction to CMD FSM and go
2981	// to DCACHE_SC_WAIT state.
2982	// We don't check a possible write hit in dcache, as the cache update
2983	// is done by the coherence transaction induced by the SC...
2984	else if (m_dreq.type == iss_t::DATA_SC)
2985	{
2986	if ((r_mmu_mode.read() & DATA_TLB_MASK)
2987	and not tlb_flags.d) // Dirty bit must be set
2988	{
2989	// The PTE physical address is obtained from the nline value (dtlb),
2990	// and the word index (virtual address)
2991	if (tlb_flags.b) // PTE1
2992	{
2993	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2994	(paddr_t) ((m_dreq.addr >> 19) & 0x3c);
2995	}
2996	else // PTE2
2997	{
2998	r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) \|
2999	(paddr_t) ((m_dreq.addr >> 9) & 0x38);
3000	}
3001	r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
3002	m_drsp.valid = false;
3003	m_drsp.error = false;
3004	m_drsp.rdata = 0;
3005	}
3006	else // SC request accepted
3007	{
3008	#ifdef INSTRUMENTATION
3009	m_cpt_data_sc++;
3010	#endif
3011	// checking local success
3012	if (r_dcache_llsc_valid.read() and
3013	(r_dcache_llsc_paddr.read() == paddr)) // local success
3014	{
3015	// request an SC CMD and go to DCACHE_SC_WAIT state
3016	r_dcache_vci_paddr = paddr;
3017	r_dcache_vci_sc_req = true;
3018	r_dcache_vci_sc_data = m_dreq.wdata;
3019	r_dcache_fsm = DCACHE_SC_WAIT;
3020	}
3021	else // local fail
3022	{
3023	m_drsp.valid = true;
3024	m_drsp.error = false;
3025	m_drsp.rdata = 0x1;
3026	}
3027	}
3028	} // end SC
3029	} // end valid_req
3030	} // end if read/write/ll/sc request
3031	} // end processor request
3032
3033	// itlb miss request
3034	else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
3035	{
3036	r_dcache_tlb_ins = true;
3037	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3038	r_dcache_fsm = DCACHE_TLB_MISS;
3039	}
3040
3041	// Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req
3042	r_dcache_updt_req = updt_request;
3043	r_dcache_wbuf_req = wbuf_request or
3044	(r_dcache_wbuf_req.read() and wbuf_write_miss);
3045	break;
3046	}
3047	/////////////////////
3048	case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss.
3049	// Input arguments are:
3050	// - r_dcache_tlb_vaddr
3051	// - r_dcache_tlb_ins (true when itlb miss)
3052	// The sub-fsm access the dcache to find the missing TLB entry,
3053	// and activates the cache miss procedure in case of miss.
3054	// It bypass the first level page table access if possible.
3055	// It uses atomic access to update the R/L access bits
3056	// in the page table if required.
3057	// It directly updates the itlb or dtlb, and writes into the
3058	// r_mmu_ins_* or r_mmu_data* error reporting registers.
3059	{
3060	uint32_t ptba = 0;
3061	bool bypass;
3062	paddr_t pte_paddr;
3063
3064	// evaluate bypass in order to skip first level page table access
3065	if (r_dcache_tlb_ins.read()) // itlb miss
3066	{
3067	bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3068	}
3069	else // dtlb miss
3070	{
3071	bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
3072	}
3073
3074	if (not bypass) // Try to read PTE1/PTD1 in dcache
3075	{
3076	pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) \|
3077	((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
3078	r_dcache_tlb_paddr = pte_paddr;
3079	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3080	}
3081	else // Try to read PTE2 in dcache
3082	{
3083	pte_paddr = (paddr_t) ptba << PAGE_K_NBITS \|
3084	(paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3);
3085	r_dcache_tlb_paddr = pte_paddr;
3086	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3087	}
3088
3089	#if DEBUG_DCACHE
3090	if (m_debug_dcache_fsm)
3091	{
3092	if (r_dcache_tlb_ins.read())
3093	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
3094	else
3095	std::cout << " <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
3096	std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
3097	<< " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
3098	<< " / BYPASS = " << bypass
3099	<< " / PTE_ADR = " << pte_paddr << std::endl;
3100	}
3101	#endif
3102
3103	break;
3104	}
3105	/////////////////////////
3106	case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
3107	{
3108	// coherence clack request (from DSPIN CLACK)
3109	if (r_dcache_clack_req.read())
3110	{
3111	r_dcache_fsm = DCACHE_CC_CHECK;
3112	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3113	break;
3114	}
3115
3116	// coherence request (from CC_RECEIVE FSM)
3117	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3118	{
3119	r_dcache_fsm = DCACHE_CC_CHECK;
3120	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3121	break;
3122	}
3123
3124	uint32_t entry;
3125	size_t way;
3126	size_t set;
3127	size_t word;
3128	int cache_state;
3129	r_dcache.read(r_dcache_tlb_paddr.read(),
3130	&entry,
3131	&way,
3132	&set,
3133	&word,
3134	&cache_state);
3135	#ifdef INSTRUMENTATION
3136	m_cpt_dcache_data_read++;
3137	m_cpt_dcache_dir_read++;
3138	#endif
3139	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3140	{
3141	if (not (entry & PTE_V_MASK)) // unmapped
3142	{
3143	if (r_dcache_tlb_ins.read())
3144	{
3145	r_mmu_ietr = MMU_READ_PT1_UNMAPPED;
3146	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3147	r_icache_tlb_miss_req = false;
3148	r_icache_tlb_rsp_error = true;
3149	}
3150	else
3151	{
3152	r_mmu_detr = MMU_READ_PT1_UNMAPPED;
3153	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3154	m_drsp.valid = true;
3155	m_drsp.error = true;
3156	}
3157	r_dcache_fsm = DCACHE_IDLE;
3158
3159	#if DEBUG_DCACHE
3160	if (m_debug_dcache_fsm)
3161	{
3162	std::cout << " <PROC " << name()
3163	<< " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
3164	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3165	<< std::dec << " / way = " << way
3166	<< std::dec << " / set = " << set
3167	<< std::dec << " / word = " << word
3168	<< std::hex << " / PTE1 = " << entry << std::endl;
3169	}
3170	#endif
3171
3172	}
3173	else if (entry & PTE_T_MASK) // PTD : me must access PT2
3174	{
3175	// mark the cache line ac containing a PTD
3176	r_dcache_contains_ptd[m_dcache_sets * way + set] = true;
3177
3178	// register bypass
3179	if (r_dcache_tlb_ins.read()) // itlb
3180	{
3181	r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
3182	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3183	r_dcache_tlb_paddr.read() / (m_icache_words << 2));
3184	}
3185	else // dtlb
3186	{
3187	r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
3188	entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
3189	r_dcache_tlb_paddr.read() / (m_dcache_words << 2));
3190	}
3191	r_dcache_tlb_paddr =
3192	(paddr_t)(entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS \|
3193	(paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
3194	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3195
3196	#if DEBUG_DCACHE
3197	if (m_debug_dcache_fsm)
3198	{
3199	std::cout << " <PROC " << name()
3200	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3201	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3202	<< std::dec << " / way = " << way
3203	<< std::dec << " / set = " << set
3204	<< std::dec << " / word = " << word
3205	<< std::hex << " / PTD = " << entry << std::endl;
3206	}
3207	#endif
3208	}
3209	else // PTE1 : we must update the TLB
3210	{
3211	r_dcache_in_tlb[m_icache_sets * way + set] = true;
3212	r_dcache_tlb_pte_flags = entry;
3213	r_dcache_tlb_cache_way = way;
3214	r_dcache_tlb_cache_set = set;
3215	r_dcache_tlb_cache_word = word;
3216	r_dcache_fsm = DCACHE_TLB_PTE1_SELECT;
3217
3218	#if DEBUG_DCACHE
3219	if (m_debug_dcache_fsm)
3220	{
3221	std::cout << " <PROC " << name()
3222	<< " DCACHE_TLB_PTE1_GET> HIT in dcache"
3223	<< std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
3224	<< std::dec << " / way = " << way
3225	<< std::dec << " / set = " << set
3226	<< std::dec << " / word = " << word
3227	<< std::hex << " / PTE1 = " << entry << std::endl;
3228	}
3229	#endif
3230	}
3231	}
3232	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3233	{
3234	// stalled until cleanup is acknowledged
3235	r_dcache_fsm = DCACHE_TLB_PTE1_GET;
3236	}
3237	else // we must load the missing cache line in dcache
3238	{
3239	r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
3240
3241	r_dcache_vci_miss_req = true;
3242	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3243	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3244	r_dcache_miss_type = PTE1_MISS;
3245	r_dcache_fsm = DCACHE_MISS_SELECT;
3246
3247	#if DEBUG_DCACHE
3248	if (m_debug_dcache_fsm)
3249	{
3250	std::cout << " <PROC " << name()
3251	<< " DCACHE_TLB_PTE1_GET> MISS in dcache:"
3252	<< " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3253	}
3254	#endif
3255	}
3256	break;
3257	}
3258	////////////////////////////
3259	case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
3260	{
3261	size_t way;
3262	size_t set;
3263
3264	if (r_dcache_tlb_ins.read())
3265	{
3266	r_itlb.select(r_dcache_tlb_vaddr.read(),
3267	true, // PTE1
3268	&way,
3269	&set);
3270	#ifdef INSTRUMENTATION
3271	m_cpt_itlb_read++;
3272	#endif
3273	}
3274	else
3275	{
3276	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3277	true, // PTE1
3278	&way,
3279	&set);
3280	#ifdef INSTRUMENTATION
3281	m_cpt_dtlb_read++;
3282	#endif
3283	}
3284	r_dcache_tlb_way = way;
3285	r_dcache_tlb_set = set;
3286	r_dcache_fsm = DCACHE_TLB_PTE1_UPDT;
3287
3288	#if DEBUG_DCACHE
3289	if (m_debug_dcache_fsm)
3290	{
3291	if (r_dcache_tlb_ins.read())
3292	std::cout << " <PROC " << name()
3293	<< " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
3294	else
3295	std::cout << " <PROC " << name()
3296	<< ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
3297	std::cout << " way = " << std::dec << way
3298	<< " / set = " << set << std::endl;
3299	}
3300	#endif
3301	break;
3302	}
3303	//////////////////////////
3304	case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit
3305	// - if L/R bit already set, exit the sub-fsm.
3306	// - if not, we update the page table but we dont write
3307	// neither in DCACHE, nor in TLB, as this will be done by
3308	// the coherence mechanism.
3309	{
3310	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3311	uint32_t pte = r_dcache_tlb_pte_flags.read();
3312	bool pt_updt = false;
3313	bool local = true;
3314
3315	// We should compute the access locality:
3316	// The PPN MSB bits define the destination cluster index.
3317	// The m_srcid MSB bits define the source cluster index.
3318	// The number of bits to compare depends on the number of clusters,
3319	// and can be obtained in the mapping table.
3320	// As long as this computation is not done, all access are local.
3321
3322	if (local) // local access
3323	{
3324	if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3325	{
3326	pt_updt = true;
3327	r_dcache_vci_cas_old = pte;
3328	r_dcache_vci_cas_new = pte \| PTE_L_MASK;
3329	pte = pte \| PTE_L_MASK;
3330	r_dcache_tlb_pte_flags = pte;
3331	}
3332	}
3333	else // remote access
3334	{
3335	if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3336	{
3337	pt_updt = true;
3338	r_dcache_vci_cas_old = pte;
3339	r_dcache_vci_cas_new = pte \| PTE_R_MASK;
3340	pte = pte \| PTE_R_MASK;
3341	r_dcache_tlb_pte_flags = pte;
3342	}
3343	}
3344
3345	if (not pt_updt) // update TLB and return
3346	{
3347	if (r_dcache_tlb_ins.read())
3348	{
3349	r_itlb.write(true, // 2M page
3350	pte,
3351	0, // argument unused for a PTE1
3352	r_dcache_tlb_vaddr.read(),
3353	r_dcache_tlb_way.read(),
3354	r_dcache_tlb_set.read(),
3355	nline);
3356	#ifdef INSTRUMENTATION
3357	m_cpt_itlb_write++;
3358	#endif
3359
3360	#if DEBUG_DCACHE
3361	if (m_debug_dcache_fsm)
3362	{
3363	std::cout << " <PROC " << name()
3364	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
3365	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3366	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3367	r_itlb.printTrace();
3368	}
3369	#endif
3370	}
3371	else
3372	{
3373	r_dtlb.write(true, // 2M page
3374	pte,
3375	0, // argument unused for a PTE1
3376	r_dcache_tlb_vaddr.read(),
3377	r_dcache_tlb_way.read(),
3378	r_dcache_tlb_set.read(),
3379	nline);
3380	#ifdef INSTRUMENTATION
3381	m_cpt_dtlb_write++;
3382	#endif
3383
3384	#if DEBUG_DCACHE
3385	if (m_debug_dcache_fsm)
3386	{
3387	std::cout << " <PROC " << name()
3388	<< " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
3389	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3390	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3391	r_dtlb.printTrace();
3392	}
3393	#endif
3394	}
3395	r_dcache_fsm = DCACHE_TLB_RETURN;
3396	}
3397	else // update page table but not TLB
3398	{
3399	r_dcache_fsm = DCACHE_TLB_LR_UPDT;
3400
3401	#if DEBUG_DCACHE
3402	if (m_debug_dcache_fsm)
3403	{
3404	std::cout << " <PROC " << name()
3405	<< " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
3406	<< std::endl;
3407	}
3408	#endif
3409	}
3410	break;
3411	}
3412	/////////////////////////
3413	case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
3414	{
3415	// coherence clack request (from DSPIN CLACK)
3416	if (r_dcache_clack_req.read())
3417	{
3418	r_dcache_fsm = DCACHE_CC_CHECK;
3419	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3420	break;
3421	}
3422
3423	// coherence request (from CC_RECEIVE FSM)
3424	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3425	{
3426	r_dcache_fsm = DCACHE_CC_CHECK;
3427	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3428	break;
3429	}
3430
3431	uint32_t pte_flags;
3432	uint32_t pte_ppn;
3433	size_t way;
3434	size_t set;
3435	size_t word;
3436	int cache_state;
3437
3438	r_dcache.read(r_dcache_tlb_paddr.read(),
3439	&pte_flags,
3440	&pte_ppn,
3441	&way,
3442	&set,
3443	&word,
3444	&cache_state);
3445	#ifdef INSTRUMENTATION
3446	m_cpt_dcache_data_read++;
3447	m_cpt_dcache_dir_read++;
3448	#endif
3449	if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache
3450	{
3451	if (not (pte_flags & PTE_V_MASK)) // unmapped
3452	{
3453	if (r_dcache_tlb_ins.read())
3454	{
3455	r_mmu_ietr = MMU_READ_PT2_UNMAPPED;
3456	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
3457	r_icache_tlb_miss_req = false;
3458	r_icache_tlb_rsp_error = true;
3459	}
3460	else
3461	{
3462	r_mmu_detr = MMU_READ_PT2_UNMAPPED;
3463	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
3464	m_drsp.valid = true;
3465	m_drsp.error = true;
3466	}
3467	r_dcache_fsm = DCACHE_IDLE;
3468
3469	#if DEBUG_DCACHE
3470	if (m_debug_dcache_fsm)
3471	{
3472	std::cout << " <PROC " << name()
3473	<< " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
3474	<< " PTE_FLAGS = " << std::hex << pte_flags
3475	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3476	}
3477	#endif
3478	}
3479	else // mapped : we must update the TLB
3480	{
3481	r_dcache_in_tlb[m_dcache_sets * way + set] = true;
3482	r_dcache_tlb_pte_flags = pte_flags;
3483	r_dcache_tlb_pte_ppn = pte_ppn;
3484	r_dcache_tlb_cache_way = way;
3485	r_dcache_tlb_cache_set = set;
3486	r_dcache_tlb_cache_word = word;
3487	r_dcache_fsm = DCACHE_TLB_PTE2_SELECT;
3488
3489	#if DEBUG_DCACHE
3490	if (m_debug_dcache_fsm)
3491	{
3492	std::cout << " <PROC " << name()
3493	<< " DCACHE_TLB_PTE2_GET> HIT in dcache:"
3494	<< " PTE_FLAGS = " << std::hex << pte_flags
3495	<< " PTE_PPN = " << std::hex << pte_ppn << std::endl;
3496	}
3497	#endif
3498	}
3499	}
3500	else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
3501	{
3502	// stalled until cleanup is acknowledged
3503	r_dcache_fsm = DCACHE_TLB_PTE2_GET;
3504
3505	#if DEBUG_DCACHE
3506	if (m_debug_dcache_fsm)
3507	{
3508	std::cout << " <PROC " << name()
3509	<< " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
3510	<< std::endl;
3511	}
3512	#endif
3513	}
3514	else // we must load the missing cache line in dcache
3515	{
3516	r_dcache_vci_wdt_trdid = r_dcache_wdt_timeout.read();
3517
3518	r_dcache_fsm = DCACHE_MISS_SELECT;
3519	r_dcache_vci_miss_req = true;
3520	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3521	r_dcache_save_paddr = r_dcache_tlb_paddr.read();
3522	r_dcache_miss_type = PTE2_MISS;
3523
3524	#if DEBUG_DCACHE
3525	if (m_debug_dcache_fsm)
3526	{
3527	std::cout << " <PROC " << name()
3528	<< " DCACHE_TLB_PTE2_GET> MISS in dcache:"
3529	<< " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
3530	}
3531	#endif
3532	}
3533	break;
3534	}
3535	////////////////////////////
3536	case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2
3537	{
3538	size_t way;
3539	size_t set;
3540
3541	if (r_dcache_tlb_ins.read())
3542	{
3543	r_itlb.select(r_dcache_tlb_vaddr.read(),
3544	false, // PTE2
3545	&way,
3546	&set);
3547	#ifdef INSTRUMENTATION
3548	m_cpt_itlb_read++;
3549	#endif
3550	}
3551	else
3552	{
3553	r_dtlb.select(r_dcache_tlb_vaddr.read(),
3554	false, // PTE2
3555	&way,
3556	&set);
3557	#ifdef INSTRUMENTATION
3558	m_cpt_dtlb_read++;
3559	#endif
3560	}
3561
3562	#if DEBUG_DCACHE
3563	if (m_debug_dcache_fsm)
3564	{
3565	if (r_dcache_tlb_ins.read())
3566	std::cout << " <PROC " << name()
3567	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
3568	else
3569	std::cout << " <PROC " << name()
3570	<< " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
3571	std::cout << " way = " << std::dec << way
3572	<< " / set = " << set << std::endl;
3573	}
3574	#endif
3575	r_dcache_tlb_way = way;
3576	r_dcache_tlb_set = set;
3577	r_dcache_fsm = DCACHE_TLB_PTE2_UPDT;
3578	break;
3579	}
3580	//////////////////////////
3581	case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit
3582	// - if L/R bit already set, exit the sub-fsm.
3583	// - if not, we update the page table but we dont write
3584	// neither in DCACHE, nor in TLB, as this will be done by
3585	// the coherence mechanism.
3586	{
3587	paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
3588	uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
3589	uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read();
3590	bool pt_updt = false;
3591	bool local = true;
3592
3593	// We should compute the access locality:
3594	// The PPN MSB bits define the destination cluster index.
3595	// The m_srcid MSB bits define the source cluster index.
3596	// The number of bits to compare depends on the number of clusters,
3597	// and can be obtained in the mapping table.
3598	// As long as this computation is not done, all access are local.
3599
3600	if (local) // local access
3601	{
3602	if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
3603	{
3604	pt_updt = true;
3605	r_dcache_vci_cas_old = pte_flags;
3606	r_dcache_vci_cas_new = pte_flags \| PTE_L_MASK;
3607	pte_flags = pte_flags \| PTE_L_MASK;
3608	r_dcache_tlb_pte_flags = pte_flags;
3609	}
3610	}
3611	else // remote access
3612	{
3613	if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
3614	{
3615	pt_updt = true;
3616	r_dcache_vci_cas_old = pte_flags;
3617	r_dcache_vci_cas_new = pte_flags \| PTE_R_MASK;
3618	pte_flags = pte_flags \| PTE_R_MASK;
3619	r_dcache_tlb_pte_flags = pte_flags;
3620	}
3621	}
3622
3623	if (not pt_updt) // update TLB
3624	{
3625	if (r_dcache_tlb_ins.read())
3626	{
3627	r_itlb.write( false, // 4K page
3628	pte_flags,
3629	pte_ppn,
3630	r_dcache_tlb_vaddr.read(),
3631	r_dcache_tlb_way.read(),
3632	r_dcache_tlb_set.read(),
3633	nline );
3634	#ifdef INSTRUMENTATION
3635	m_cpt_itlb_write++;
3636	#endif
3637
3638	#if DEBUG_DCACHE
3639	if (m_debug_dcache_fsm)
3640	{
3641	std::cout << " <PROC " << name()
3642	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
3643	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3644	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3645	r_itlb.printTrace();
3646	}
3647	#endif
3648	}
3649	else
3650	{
3651	r_dtlb.write(false, // 4K page
3652	pte_flags,
3653	pte_ppn,
3654	r_dcache_tlb_vaddr.read(),
3655	r_dcache_tlb_way.read(),
3656	r_dcache_tlb_set.read(),
3657	nline);
3658	#ifdef INSTRUMENTATION
3659	m_cpt_dtlb_write++;
3660	#endif
3661
3662	#if DEBUG_DCACHE
3663	if (m_debug_dcache_fsm)
3664	{
3665	std::cout << " <PROC " << name()
3666	<< " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
3667	<< " / set = " << std::dec << r_dcache_tlb_set.read()
3668	<< " / way = " << r_dcache_tlb_way.read() << std::endl;
3669	r_dtlb.printTrace();
3670	}
3671	#endif
3672
3673	}
3674	r_dcache_fsm = DCACHE_TLB_RETURN;
3675	}
3676	else // update page table but not TLB
3677	{
3678	r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
3679
3680	#if DEBUG_DCACHE
3681	if (m_debug_dcache_fsm)
3682	{
3683	std::cout << " <PROC " << name()
3684	<< " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
3685	}
3686	#endif
3687	}
3688	break;
3689	}
3690	////////////////////////
3691	case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit
3692	{
3693	#if DEBUG_DCACHE
3694	if (m_debug_dcache_fsm)
3695	{
3696	std::cout << " <PROC " << name()
3697	<< " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
3698	}
3699	#endif
3700	// r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
3701	r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
3702
3703	// checking llsc reservation buffer
3704	if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read())
3705	r_dcache_llsc_valid = false;
3706
3707	// request a CAS CMD and go to DCACHE_TLB_LR_WAIT state
3708	r_dcache_vci_cas_req = true;
3709	r_dcache_fsm = DCACHE_TLB_LR_WAIT;
3710	break;
3711	}
3712	////////////////////////
3713	case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit.
3714	// We consume the response in rsp FIFO,
3715	// and exit the sub-fsm, but we don't
3716	// analyse the response, because we don't
3717	// care if the L/R bit update is not done.
3718	// We must take the coherence requests because
3719	// there is a risk of dead-lock
3720
3721	{
3722	// coherence clack request (from DSPIN CLACK)
3723	if (r_dcache_clack_req.read())
3724	{
3725	r_dcache_fsm = DCACHE_CC_CHECK;
3726	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3727	break;
3728	}
3729
3730	// coherence request (from CC_RECEIVE FSM)
3731	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3732	{
3733	r_dcache_fsm = DCACHE_CC_CHECK;
3734	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3735	break;
3736	}
3737
3738	if (r_vci_rsp_data_error.read()) // bus error
3739	{
3740	std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
3741	std::cout << "This should not happen in this state" << std::endl;
3742	exit(0);
3743	}
3744	else if (r_vci_rsp_fifo_dcache.rok()) // response available
3745	{
3746	#if DEBUG_DCACHE
3747	if (m_debug_dcache_fsm)
3748	{
3749	std::cout << " <PROC " << name()
3750	<< " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
3751	}
3752	#endif
3753	vci_rsp_fifo_dcache_get = true;
3754	r_dcache_fsm = DCACHE_TLB_RETURN;
3755	}
3756	break;
3757	}
3758	///////////////////////
3759	case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type
3760	{
3761	#if DEBUG_DCACHE
3762	if (m_debug_dcache_fsm)
3763	{
3764	std::cout << " <PROC " << name()
3765	<< " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
3766	}
3767	#endif
3768	if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false;
3769	r_dcache_fsm = DCACHE_IDLE;
3770	break;
3771	}
3772	///////////////////////
3773	case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written,
3774	// and both itlb and dtlb must be flushed.
3775	// Caution : the itlb miss requests must be taken
3776	// to avoid dead-lock in case of simultaneous ITLB miss
3777	// Caution : the clack and cc requests must be taken
3778	// to avoid dead-lock
3779	{
3780	// coherence clack request (from DSPIN CLACK)
3781	if (r_dcache_clack_req.read())
3782	{
3783	r_dcache_fsm = DCACHE_CC_CHECK;
3784	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3785	break;
3786	}
3787
3788	// coherence request (from CC_RECEIVE FSM)
3789	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3790	{
3791	r_dcache_fsm = DCACHE_CC_CHECK;
3792	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3793	break;
3794	}
3795
3796	// itlb miss request
3797	if (r_icache_tlb_miss_req.read())
3798	{
3799	r_dcache_tlb_ins = true;
3800	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3801	r_dcache_fsm = DCACHE_TLB_MISS;
3802	break;
3803	}
3804
3805	if (not r_dcache_xtn_req.read())
3806	{
3807	r_dtlb.flush();
3808	r_mmu_ptpr = m_dreq.wdata;
3809	r_dcache_fsm = DCACHE_IDLE;
3810	m_drsp.valid = true;
3811	}
3812	break;
3813	}
3814	/////////////////////
3815	case DCACHE_XTN_SYNC: // waiting until write buffer empty
3816	// The coherence request must be taken
3817	// as there is a risk of dead-lock
3818	{
3819	// coherence clack request (from DSPIN CLACK)
3820	if (r_dcache_clack_req.read())
3821	{
3822	r_dcache_fsm = DCACHE_CC_CHECK;
3823	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3824	break;
3825	}
3826
3827	// coherence request (from CC_RECEIVE FSM)
3828	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3829	{
3830	r_dcache_fsm = DCACHE_CC_CHECK;
3831	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3832	break;
3833	}
3834
3835	if (r_wbuf.empty())
3836	{
3837	m_drsp.valid = true;
3838	r_dcache_fsm = DCACHE_IDLE;
3839	}
3840	break;
3841	}
3842	////////////////////////
3843	case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM
3844	case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken
3845	case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache
3846	case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss,
3847	case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss
3848
3849	{
3850	// coherence clack request (from DSPIN CLACK)
3851	if (r_dcache_clack_req.read())
3852	{
3853	r_dcache_fsm = DCACHE_CC_CHECK;
3854	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3855	break;
3856	}
3857
3858	// coherence request (from CC_RECEIVE FSM)
3859	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3860	{
3861	r_dcache_fsm = DCACHE_CC_CHECK;
3862	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3863	break;
3864	}
3865
3866	// itlb miss request
3867	if (r_icache_tlb_miss_req.read())
3868	{
3869	r_dcache_tlb_ins = true;
3870	r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
3871	r_dcache_fsm = DCACHE_TLB_MISS;
3872	break;
3873	}
3874
3875	// test if XTN request to icache completed
3876	if (not r_dcache_xtn_req.read())
3877	{
3878	r_dcache_fsm = DCACHE_IDLE;
3879	m_drsp.valid = true;
3880	}
3881	break;
3882	}
3883	/////////////////////////
3884	case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using
3885	// r_dcache_flush_count as a slot counter,
3886	// looping in this state until all slots have been visited.
3887	// It can require two cycles per slot:
3888	// We test here the slot state, and make the actual inval
3889	// (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state.
3890	// A cleanup request is generated for each valid line.
3891	// returns to IDLE and flush TLBs when last slot
3892	{
3893	// coherence clack request (from DSPIN CLACK)
3894	if (r_dcache_clack_req.read())
3895	{
3896	r_dcache_fsm = DCACHE_CC_CHECK;
3897	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3898	break;
3899	}
3900
3901	// coherence request (from CC_RECEIVE FSM)
3902	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
3903	{
3904	r_dcache_fsm = DCACHE_CC_CHECK;
3905	r_dcache_fsm_cc_save = r_dcache_fsm.read();
3906	break;
3907	}
3908
3909	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
3910	{
3911	int state;
3912	paddr_t tag;
3913	size_t way = r_dcache_flush_count.read() / m_dcache_sets;
3914	size_t set = r_dcache_flush_count.read() % m_dcache_sets;
3915
3916	#ifdef INSTRUMENTATION
3917	m_cpt_dcache_dir_read++;
3918	#endif
3919	r_dcache.read_dir(way,
3920	set,
3921	&tag,
3922	&state);
3923
3924	if (state == CACHE_SLOT_STATE_VALID) // inval required
3925	{
3926	// request cleanup
3927	r_dcache_cc_send_req = true;
3928	r_dcache_cc_send_nline = tag * m_dcache_sets + set;
3929	r_dcache_cc_send_way = way;
3930	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
3931
3932	// goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
3933	r_dcache_miss_way = way;
3934	r_dcache_miss_set = set;
3935	r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
3936	}
3937	else if (r_dcache_flush_count.read() ==
3938	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3939	{
3940	r_dtlb.reset();
3941	r_itlb.reset();
3942	r_dcache_fsm = DCACHE_IDLE;
3943	m_drsp.valid = true;
3944	}
3945
3946	// saturation counter
3947	if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1))
3948	r_dcache_flush_count = r_dcache_flush_count.read() + 1;
3949	}
3950	break;
3951	}
3952	////////////////////////////
3953	case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state
3954	// and reset directory extension.
3955	// returns to IDLE and flush TLBs when last slot
3956	{
3957	size_t way = r_dcache_miss_way.read();
3958	size_t set = r_dcache_miss_set.read();
3959
3960	r_dcache_in_tlb[m_dcache_sets * way + set] = false;
3961	r_dcache_contains_ptd[m_dcache_sets * way + set] = false;
3962
3963	#ifdef INSTRUMENTATION
3964	m_cpt_dcache_dir_write++;
3965	#endif
3966	r_dcache.write_dir(way,
3967	set,
3968	CACHE_SLOT_STATE_ZOMBI);
3969
3970	if (r_dcache_flush_count.read() ==
3971	(m_dcache_sets*m_dcache_ways - 1)) // last slot
3972	{
3973	r_dtlb.reset();
3974	r_itlb.reset();
3975	r_dcache_fsm = DCACHE_IDLE;
3976	m_drsp.valid = true;
3977	}
3978	else
3979	{
3980	r_dcache_fsm = DCACHE_XTN_DC_FLUSH;
3981	}
3982	break;
3983	}
3984	/////////////////////////
3985	case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
3986	{
3987	r_dtlb.inval(r_dcache_save_wdata.read());
3988	r_dcache_fsm = DCACHE_IDLE;
3989	m_drsp.valid = true;
3990	break;
3991	}
3992	////////////////////////////
3993	case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address
3994	// requires 3 cycles: access tlb, read cache, inval cache
3995	// we compute the physical address in this state
3996	{
3997	paddr_t paddr;
3998	bool hit;
3999
4000	if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated
4001	{
4002
4003	#ifdef INSTRUMENTATION
4004	m_cpt_dtlb_read++;
4005	#endif
4006	hit = r_dtlb.translate(r_dcache_save_wdata.read(),
4007	&paddr);
4008	}
4009	else // dtlb not activated
4010	{
4011	paddr = (paddr_t)r_dcache_save_wdata.read();
4012	if (vci_param::N > 32)
4013	paddr = paddr \| ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
4014	hit = true;
4015	}
4016
4017	if (hit) // tlb hit
4018	{
4019	r_dcache_save_paddr = paddr;
4020	r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
4021	}
4022	else // tlb miss
4023	{
4024
4025	#ifdef INSTRUMENTATION
4026	m_cpt_dtlb_miss++;
4027	#endif
4028	r_dcache_tlb_ins = false; // dtlb
4029	r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
4030	r_dcache_fsm = DCACHE_TLB_MISS;
4031	}
4032
4033	#if DEBUG_DCACHE
4034	if (m_debug_dcache_fsm)
4035	{
4036	std::cout << " <PROC " << name()
4037	<< " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
4038	<< " / VADDR = " << r_dcache_save_wdata.read()
4039	<< " / PADDR = " << paddr << std::endl;
4040	}
4041	#endif
4042
4043	break;
4044	}
4045	////////////////////////////
4046	case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address
4047	// requires 2 cycles: read cache / inval cache
4048	// In this state we read dcache.
4049	{
4050	size_t way;
4051	size_t set;
4052	size_t word;
4053	int state;
4054
4055	#ifdef INSTRUMENTATION
4056	m_cpt_dcache_dir_read++;
4057	#endif
4058	r_dcache.read_dir(r_dcache_save_paddr.read(),
4059	&state,
4060	&way,
4061	&set,
4062	&word);
4063
4064	if (state == CACHE_SLOT_STATE_VALID) // inval to be done
4065	{
4066	r_dcache_xtn_way = way;
4067	r_dcache_xtn_set = set;
4068	r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
4069	}
4070	else // miss : nothing to do
4071	{
4072	r_dcache_fsm = DCACHE_IDLE;
4073	m_drsp.valid = true;
4074	}
4075
4076	#if DEBUG_DCACHE
4077	if (m_debug_dcache_fsm)
4078	{
4079	std::cout << " <PROC " << name()
4080	<< " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
4081	<< " / PADDR = " << r_dcache_save_paddr.read() << std::dec
4082	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID)
4083	<< " / SET = " << set
4084	<< " / WAY = " << way << std::endl;
4085	}
4086	#endif
4087	break;
4088	}
4089	////////////////////////////
4090	case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line
4091	// Blocked if previous cleanup not completed
4092	// Test if itlb or dtlb inval is required
4093	{
4094	if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
4095	{
4096	size_t way = r_dcache_xtn_way.read();
4097	size_t set = r_dcache_xtn_set.read();
4098	paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4099
4100	#ifdef INSTRUMENTATION
4101	m_cpt_dcache_dir_write++;
4102	#endif
4103	r_dcache.write_dir(way,
4104	set,
4105	CACHE_SLOT_STATE_ZOMBI);
4106
4107	// request cleanup
4108	r_dcache_cc_send_req = true;
4109	r_dcache_cc_send_nline = nline;
4110	r_dcache_cc_send_way = way;
4111	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4112
4113	// possible itlb & dtlb invalidate
4114	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4115	{
4116	r_dcache_tlb_inval_line = nline;
4117	r_dcache_tlb_inval_set = 0;
4118	r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END;
4119	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4120	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4121	}
4122	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4123	{
4124	r_itlb.reset();
4125	r_dtlb.reset();
4126	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4127	r_dcache_fsm = DCACHE_IDLE;
4128	m_drsp.valid = true;
4129	}
4130	else
4131	{
4132	r_dcache_fsm = DCACHE_IDLE;
4133	m_drsp.valid = true;
4134	}
4135
4136	#if DEBUG_DCACHE
4137	if (m_debug_dcache_fsm)
4138	{
4139	std::cout << " <PROC " << name()
4140	<< " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
4141	<< " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
4142	}
4143	#endif
4144	}
4145	break;
4146	}
4147	//////////////////////////////
4148	case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
4149	{
4150	r_dcache_fsm = DCACHE_IDLE;
4151	m_drsp.valid = true;
4152	break;
4153	}
4154	//////////////////////////////
4155	case DCACHE_XTN_CC_TEST: // wait the CC_TEST to finish
4156	{
4157	// coherence clack request (from DSPIN CLACK)
4158	if (r_dcache_clack_req.read())
4159	{
4160	r_dcache_fsm = DCACHE_CC_CHECK;
4161	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4162	break;
4163	}
4164
4165	// coherence request (from CC_RECEIVE FSM)
4166	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4167	{
4168	r_dcache_fsm = DCACHE_CC_CHECK;
4169	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4170	break;
4171	}
4172
4173	// increment watchdog timer for black-hole detection
4174	r_dcache_wdt = r_dcache_wdt.read() + 1;
4175	if (dcache_watchdog_timeout)
4176	{
4177	r_mmu_detr = MMU_WDT_TIMEOUT;
4178	m_drsp.valid = true;
4179	m_drsp.error = true;
4180	r_dcache_fsm = DCACHE_IDLE;
4181
4182	// TODO: send the TRDID in the coherence packet to detect an early
4183	// WDT timeout
4184	// debug: this counter is used to detect an early WDT timeout.
4185	// It is sent as the data uncacheable transactions TRDID. When a
4186	// response is treated by the RSP FSM, the RTRDID is compared to
4187	// this counter to determine if a timeout was triggered during the
4188	// transaction.
4189	r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1;
4190
4191	#if DEBUG_DCACHE
4192	if (m_debug_dcache_fsm)
4193	{
4194	std::cout << " <PROC " << name() << " DCACHE_XTN_CC_TEST>"
4195	" watchdog timer exception" << std::endl;
4196	}
4197	#endif
4198	break;
4199	}
4200
4201	// wait the CC_TEST request to finish
4202	if (not r_dcache_to_cc_test_req.read())
4203	{
4204	m_drsp.valid = true;
4205	r_dcache_fsm = DCACHE_IDLE;
4206
4207	#if DEBUG_DCACHE
4208	if (m_debug_dcache_fsm)
4209	{
4210	std::cout << " <PROC " << name()
4211	<< " DCACHE_XTN_CC_TEST> CC_TEST finished:"
4212	<< std::hex
4213	<< " / DEST = " << r_dcache_to_cc_test_dest.read()
4214	<< std::dec << std::endl;
4215	}
4216	#endif
4217	}
4218	break;
4219	}
4220	////////////////////////
4221	case DCACHE_MISS_SELECT: // Try to select a slot in associative set,
4222	// Waiting in this state if no slot available.
4223	// If a victim slot has been choosen and the r_icache_cc_send_req is false,
4224	// we send the cleanup request in this state.
4225	// If not, a r_icache_cleanup_victim_req flip-flop is
4226	// utilized for saving this cleanup request, and it will be sent later
4227	// in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
4228	// The r_icache_miss_clack flip-flop is set
4229	// when a cleanup is required
4230	{
4231	if (m_dreq.valid) m_cost_data_miss_frz++;
4232
4233	// coherence clack request (from DSPIN CLACK)
4234	if (r_dcache_clack_req.read())
4235	{
4236	r_dcache_fsm = DCACHE_CC_CHECK;
4237	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4238	break;
4239	}
4240
4241	// coherence request (from CC_RECEIVE FSM)
4242	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4243	{
4244	r_dcache_fsm = DCACHE_CC_CHECK;
4245	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4246	break;
4247	}
4248
4249	bool found = false;
4250	bool cleanup = false;
4251	size_t way = 0;
4252	size_t set = 0;
4253	paddr_t victim = 0;
4254
4255	#ifdef INSTRUMENTATION
4256	m_cpt_dcache_dir_read++;
4257	#endif
4258	r_dcache.read_select(r_dcache_save_paddr.read(),
4259	&victim,
4260	&way,
4261	&set,
4262	&found,
4263	&cleanup);
4264
4265	if (not found)
4266	{
4267	break;
4268	}
4269	else
4270	{
4271	r_dcache_miss_way = way;
4272	r_dcache_miss_set = set;
4273
4274	// reset to 0 the watchdog timer
4275	r_dcache_wdt = 0;
4276
4277	if (cleanup)
4278	{
4279	if (not r_dcache_cc_send_req.read())
4280	{
4281	r_dcache_cc_send_req = true;
4282	r_dcache_cc_send_nline = victim;
4283	r_dcache_cc_send_way = way;
4284	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4285
4286	}
4287	else
4288	{
4289	r_dcache_cleanup_victim_req = true;
4290	r_dcache_cleanup_victim_nline = victim;
4291	}
4292
4293	r_dcache_miss_clack = true;
4294	r_dcache_fsm = DCACHE_MISS_CLEAN;
4295	}
4296	else
4297	{
4298	r_dcache_fsm = DCACHE_MISS_WAIT;
4299	}
4300
4301	#if DEBUG_DCACHE
4302	if (m_debug_dcache_fsm)
4303	{
4304	std::cout << " <PROC " << name()
4305	<< " DCACHE_MISS_SELECT> Select a slot:" << std::dec
4306	<< " / WAY = " << way
4307	<< " / SET = " << set
4308	<< " / PADDR = " << std::hex << r_dcache_save_paddr.read();
4309	if (cleanup) std::cout << " / VICTIM = " << (victimm_dcache_words4) << std::endl;
4310	else std::cout << std::endl;
4311	}
4312	#endif
4313	} // end found
4314	break;
4315	}
4316	///////////////////////
4317	case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state
4318	// and possibly request itlb or dtlb invalidate
4319	{
4320	if (m_dreq.valid) m_cost_data_miss_frz++;
4321
4322	size_t way = r_dcache_miss_way.read();
4323	size_t set = r_dcache_miss_set.read();
4324
4325	#ifdef INSTRUMENTATION
4326	m_cpt_dcache_dir_read++;
4327	#endif
4328	r_dcache.write_dir(way,
4329	set,
4330	CACHE_SLOT_STATE_ZOMBI);
4331	#if DEBUG_DCACHE
4332	if (m_debug_dcache_fsm)
4333	{
4334	std::cout << " <PROC " << name()
4335	<< " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
4336	<< " / way = " << way
4337	<< " / set = " << set << std::endl;
4338	}
4339	#endif
4340	// if selective itlb & dtlb invalidate are required
4341	// the miss response is not handled before invalidate completed
4342	if (r_dcache_in_tlb[way * m_dcache_sets + set])
4343	{
4344	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4345
4346	if (not r_dcache_cleanup_victim_req.read())
4347	r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
4348	else
4349	r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
4350
4351	r_dcache_tlb_inval_set = 0;
4352	r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
4353	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
4354	}
4355	else if (r_dcache_contains_ptd[way * m_dcache_sets + set])
4356	{
4357	r_itlb.reset();
4358	r_dtlb.reset();
4359	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4360	r_dcache_fsm = DCACHE_MISS_WAIT;
4361	}
4362	else
4363	{
4364	r_dcache_fsm = DCACHE_MISS_WAIT;
4365	}
4366	break;
4367	}
4368	//////////////////////
4369	case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM
4370	// This state is in charge of error signaling
4371	// There is 5 types of error depending on the requester
4372	{
4373	if (m_dreq.valid) m_cost_data_miss_frz++;
4374
4375	// send cleanup victim request
4376	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4377	{
4378	r_dcache_cc_send_req = true;
4379	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4380	r_dcache_cc_send_way = r_dcache_miss_way;
4381	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4382	r_dcache_cleanup_victim_req = false;
4383	}
4384
4385	// coherence clack request (from DSPIN CLACK)
4386	if (r_dcache_clack_req.read())
4387	{
4388	r_dcache_fsm = DCACHE_CC_CHECK;
4389	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4390	break;
4391	}
4392
4393	// coherence request (from CC_RECEIVE FSM)
4394	if (r_cc_receive_dcache_req.read() and
4395	not r_dcache_cc_send_req.read() and
4396	not r_dcache_cleanup_victim_req.read())
4397	{
4398	r_dcache_fsm = DCACHE_CC_CHECK;
4399	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4400	break;
4401	}
4402
4403	// increment watchdog timer for black-hole detection
4404	r_dcache_wdt = r_dcache_wdt.read() + 1;
4405	if (dcache_watchdog_timeout)
4406	{
4407	r_mmu_detr = MMU_WDT_TIMEOUT;
4408	r_mmu_dbvar = r_dcache_save_vaddr.read();
4409	m_drsp.valid = true;
4410	m_drsp.error = true;
4411	r_dcache_fsm = DCACHE_IDLE;
4412
4413	// debug: this counter is used to detect an early WDT timeout.
4414	// It is sent as the data miss transactions TRDID. When a data miss
4415	// response is treated by the RSP FSM, the RTRDID is compared to
4416	// this counter to determine if a timeout was triggered during the
4417	// transaction.
4418	r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1;
4419
4420	#if DEBUG_DCACHE
4421	if (m_debug_dcache_fsm)
4422	{
4423	std::cout << " <PROC " << name() << " DCACHE_MISS_WAIT>"
4424	" watchdog timer exception" << std::endl;
4425	}
4426	#endif
4427	break;
4428	}
4429
4430	if (r_vci_rsp_data_error.read()) // bus error
4431	{
4432	switch (r_dcache_miss_type.read())
4433	{
4434	case PROC_MISS:
4435	{
4436	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4437	r_mmu_dbvar = r_dcache_save_vaddr.read();
4438	m_drsp.valid = true;
4439	m_drsp.error = true;
4440	r_dcache_fsm = DCACHE_IDLE;
4441	break;
4442	}
4443	case PTE1_MISS:
4444	{
4445	if (r_dcache_tlb_ins.read())
4446	{
4447	r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS;
4448	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4449	r_icache_tlb_miss_req = false;
4450	r_icache_tlb_rsp_error = true;
4451	}
4452	else
4453	{
4454	r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS;
4455	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4456	m_drsp.valid = true;
4457	m_drsp.error = true;
4458	}
4459	r_dcache_fsm = DCACHE_IDLE;
4460	break;
4461	}
4462	case PTE2_MISS:
4463	{
4464	if (r_dcache_tlb_ins.read())
4465	{
4466	r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS;
4467	r_mmu_ibvar = r_dcache_tlb_vaddr.read();
4468	r_icache_tlb_miss_req = false;
4469	r_icache_tlb_rsp_error = true;
4470	}
4471	else
4472	{
4473	r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS;
4474	r_mmu_dbvar = r_dcache_tlb_vaddr.read();
4475	m_drsp.valid = true;
4476	m_drsp.error = true;
4477	}
4478	r_dcache_fsm = DCACHE_IDLE;
4479	break;
4480	}
4481	} // end switch type
4482	r_vci_rsp_data_error = false;
4483	}
4484	else if (r_vci_rsp_fifo_dcache.rok()) // valid response available
4485	{
4486	r_dcache_miss_word = 0;
4487	r_dcache_fsm = DCACHE_MISS_DATA_UPDT;
4488	}
4489	break;
4490	}
4491	//////////////////////////
4492	case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle)
4493	{
4494	if (m_dreq.valid) m_cost_data_miss_frz++;
4495
4496	if (r_vci_rsp_fifo_dcache.rok()) // one word available
4497	{
4498	#ifdef INSTRUMENTATION
4499	m_cpt_dcache_data_write++;
4500	#endif
4501	r_dcache.write(r_dcache_miss_way.read(),
4502	r_dcache_miss_set.read(),
4503	r_dcache_miss_word.read(),
4504	r_vci_rsp_fifo_dcache.read());
4505	#if DEBUG_DCACHE
4506	if (m_debug_dcache_fsm)
4507	{
4508	std::cout << " <PROC " << name()
4509	<< " DCACHE_MISS_DATA_UPDT> Write one word:"
4510	<< " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read()
4511	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4512	<< " / SET = " << r_dcache_miss_set.read()
4513	<< " / WORD = " << r_dcache_miss_word.read() << std::endl;
4514	}
4515	#endif
4516	vci_rsp_fifo_dcache_get = true;
4517	r_dcache_miss_word = r_dcache_miss_word.read() + 1;
4518
4519	if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word
4520	{
4521	r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
4522	}
4523	}
4524	break;
4525	}
4526	//////////////////////////
4527	case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted
4528	// and the cleanup ack has not been received,
4529	// as indicated by the r_dcache_miss clack.
4530	// - If no matching coherence request (r_dcache_inval_miss)
4531	// switch directory slot to VALID state.
4532	// - If matching coherence request, switch directory slot
4533	// to ZOMBI state, and send a cleanup request.
4534	{
4535	if (m_dreq.valid) m_cost_data_miss_frz++;
4536
4537	// send cleanup victim request
4538	if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
4539	{
4540	r_dcache_cc_send_req = true;
4541	r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline;
4542	r_dcache_cc_send_way = r_dcache_miss_way;
4543	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4544	r_dcache_cleanup_victim_req = false;
4545	}
4546
4547	// coherence clack request (from DSPIN CLACK)
4548	if (r_dcache_clack_req.read())
4549	{
4550	r_dcache_fsm = DCACHE_CC_CHECK;
4551	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4552	break;
4553	}
4554
4555	// coherence request (from CC_RECEIVE FSM)
4556	if (r_cc_receive_dcache_req.read() and
4557	not r_dcache_cc_send_req.read() and
4558	not r_dcache_cleanup_victim_req.read())
4559	{
4560	r_dcache_fsm = DCACHE_CC_CHECK;
4561	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4562	break;
4563	}
4564
4565	if (not r_dcache_miss_clack.read()) // waiting cleanup acknowledge
4566	{
4567	if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup
4568	{
4569	if (not r_dcache_cc_send_req.read()) // blocked until previous request sent
4570	{
4571	r_dcache_miss_inval = false;
4572	// request cleanup
4573	r_dcache_cc_send_req = true;
4574	r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
4575	r_dcache_cc_send_way = r_dcache_miss_way.read();
4576	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
4577
4578	#ifdef INSTRUMENTATION
4579	m_cpt_dcache_dir_write++;
4580	#endif
4581	r_dcache.write_dir( r_dcache_save_paddr.read(),
4582	r_dcache_miss_way.read(),
4583	r_dcache_miss_set.read(),
4584	CACHE_SLOT_STATE_ZOMBI );
4585	#if DEBUG_DCACHE
4586	if (m_debug_dcache_fsm)
4587	std::cout << " <PROC " << name()
4588	<< " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
4589	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4590	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4591	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4592	#endif
4593	}
4594	else
4595	break;
4596	}
4597	else // switch slot to VALID state
4598	{
4599
4600	#ifdef INSTRUMENTATION
4601	m_cpt_dcache_dir_write++;
4602	#endif
4603	r_dcache.write_dir(r_dcache_save_paddr.read(),
4604	r_dcache_miss_way.read(),
4605	r_dcache_miss_set.read(),
4606	CACHE_SLOT_STATE_VALID);
4607
4608	#if DEBUG_DCACHE
4609	if (m_debug_dcache_fsm)
4610	std::cout << " <PROC " << name()
4611	<< " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
4612	<< " PADDR = " << std::hex << r_dcache_save_paddr.read()
4613	<< " / WAY = " << std::dec << r_dcache_miss_way.read()
4614	<< " / SET = " << r_dcache_miss_set.read() << std::endl;
4615	#endif
4616	// reset directory extension
4617	size_t way = r_dcache_miss_way.read();
4618	size_t set = r_dcache_miss_set.read();
4619	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
4620	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
4621	}
4622	if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
4623	else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
4624	else r_dcache_fsm = DCACHE_IDLE;
4625	}
4626	break;
4627	}
4628	/////////////////////
4629	case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write
4630	{
4631	// coherence clack request (from DSPIN CLACK)
4632	if (r_dcache_clack_req.read())
4633	{
4634	r_dcache_fsm = DCACHE_CC_CHECK;
4635	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4636	break;
4637	}
4638
4639	// coherence request (from CC_RECEIVE FSM)
4640	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4641	{
4642	r_dcache_fsm = DCACHE_CC_CHECK;
4643	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4644	break;
4645	}
4646
4647	// increment watchdog timer for black-hole detection
4648	r_dcache_wdt = r_dcache_wdt.read() + 1;
4649	if (dcache_watchdog_timeout)
4650	{
4651	r_mmu_detr = MMU_WDT_TIMEOUT;
4652	r_mmu_dbvar = m_dreq.addr;
4653	m_drsp.valid = true;
4654	m_drsp.error = true;
4655	r_dcache_fsm = DCACHE_IDLE;
4656
4657	// debug: this counter is used to detect an early WDT timeout.
4658	// It is sent as the data uncacheable transactions TRDID. When a
4659	// response is treated by the RSP FSM, the RTRDID is compared to
4660	// this counter to determine if a timeout was triggered during the
4661	// transaction.
4662	r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1;
4663
4664	#if DEBUG_DCACHE
4665	if (m_debug_dcache_fsm)
4666	{
4667	std::cout << " <PROC " << name() << " DCACHE_MISS_WAIT>"
4668	" watchdog timer exception" << std::endl;
4669	}
4670	#endif
4671	break;
4672	}
4673
4674	if (r_vci_rsp_data_error.read()) // bus error
4675	{
4676	if (r_dcache_vci_unc_write.read())
4677	r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
4678	else
4679	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4680
4681	r_mmu_dbvar = m_dreq.addr;
4682	r_vci_rsp_data_error = false;
4683	m_drsp.error = true;
4684	m_drsp.valid = true;
4685	r_dcache_fsm = DCACHE_IDLE;
4686	break;
4687	}
4688	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4689	{
4690	// consume data
4691	vci_rsp_fifo_dcache_get = true;
4692	r_dcache_fsm = DCACHE_IDLE;
4693
4694	// acknowledge the processor request if it has not been modified
4695	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4696	{
4697	m_drsp.valid = true;
4698	m_drsp.error = false;
4699	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4700	}
4701	}
4702	break;
4703	}
4704	/////////////////////
4705	case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction
4706	{
4707	// coherence clack request (from DSPIN CLACK)
4708	if (r_dcache_clack_req.read())
4709	{
4710	r_dcache_fsm = DCACHE_CC_CHECK;
4711	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4712	break;
4713	}
4714
4715	// coherence request (from CC_RECEIVE FSM)
4716	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4717	{
4718	r_dcache_fsm = DCACHE_CC_CHECK;
4719	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4720	break;
4721	}
4722
4723	if (r_vci_rsp_data_error.read()) // bus error
4724	{
4725	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4726	r_mmu_dbvar = m_dreq.addr;
4727	r_vci_rsp_data_error = false;
4728	m_drsp.error = true;
4729	m_drsp.valid = true;
4730	r_dcache_fsm = DCACHE_IDLE;
4731	break;
4732	}
4733	else if (r_vci_rsp_fifo_dcache.rok()) // data available
4734	{
4735	// consume data
4736	vci_rsp_fifo_dcache_get = true;
4737
4738	if (r_dcache_ll_rsp_count.read() == 0) // first flit
4739	{
4740	// set key value in llsc reservation buffer
4741	r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read();
4742	r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
4743	}
4744	else // last flit
4745	{
4746	// acknowledge the processor request if it has not been modified
4747	if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
4748	{
4749	m_drsp.valid = true;
4750	m_drsp.error = false;
4751	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4752	}
4753	r_dcache_fsm = DCACHE_IDLE;
4754	}
4755	}
4756	break;
4757	}
4758	////////////////////
4759	case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
4760	{
4761	// coherence clack request (from DSPIN CLACK)
4762	if (r_dcache_clack_req.read())
4763	{
4764	r_dcache_fsm = DCACHE_CC_CHECK;
4765	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4766	break;
4767	}
4768
4769	// coherence request (from CC_RECEIVE FSM)
4770	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4771	{
4772	r_dcache_fsm = DCACHE_CC_CHECK;
4773	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4774	break;
4775	}
4776
4777	if (r_vci_rsp_data_error.read()) // bus error
4778	{
4779	r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
4780	r_mmu_dbvar = m_dreq.addr;
4781	r_vci_rsp_data_error = false;
4782	m_drsp.error = true;
4783	m_drsp.valid = true;
4784	r_dcache_fsm = DCACHE_IDLE;
4785	break;
4786	}
4787	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4788	{
4789	// consume response
4790	vci_rsp_fifo_dcache_get = true;
4791	m_drsp.valid = true;
4792	m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
4793	r_dcache_fsm = DCACHE_IDLE;
4794	}
4795	break;
4796	}
4797	//////////////////////////
4798	case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory
4799	// before handling a processor WRITE or SC request
4800	// Input argument is r_dcache_dirty_paddr
4801	// In this first state, we get PTE value in dcache
4802	// and post a CAS request to CMD FSM
4803	{
4804	// get PTE in dcache
4805	uint32_t pte;
4806	size_t way;
4807	size_t set;
4808	size_t word; // unused
4809	int state;
4810
4811	#ifdef INSTRUMENTATION
4812	m_cpt_dcache_data_read++;
4813	m_cpt_dcache_dir_read++;
4814	#endif
4815	r_dcache.read(r_dcache_dirty_paddr.read(),
4816	&pte,
4817	&way,
4818	&set,
4819	&word,
4820	&state);
4821
4822	assert( (state == CACHE_SLOT_STATE_VALID) and
4823	"error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
4824
4825	// request CAS transaction to CMD_FSM
4826	r_dcache_dirty_way = way;
4827	r_dcache_dirty_set = set;
4828
4829	// check llsc reservation buffer
4830	if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read())
4831	r_dcache_llsc_valid = false;
4832
4833	// request a CAS CMD and go to DCACHE_DIRTY_WAIT state
4834	r_dcache_vci_cas_req = true;
4835	r_dcache_vci_paddr = r_dcache_dirty_paddr.read();
4836	r_dcache_vci_cas_old = pte;
4837	r_dcache_vci_cas_new = pte \| PTE_D_MASK;
4838	r_dcache_fsm = DCACHE_DIRTY_WAIT;
4839
4840	#if DEBUG_DCACHE
4841	if (m_debug_dcache_fsm)
4842	{
4843	std::cout << " <PROC " << name()
4844	<< " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
4845	<< " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
4846	<< " / PTE_VALUE = " << pte << std::dec
4847	<< " / SET = " << set
4848	<< " / WAY = " << way << std::endl;
4849	}
4850	#endif
4851	break;
4852	}
4853	///////////////////////
4854	case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit,
4855	// and return to IDLE state when response is received.
4856	// we don't care if the CAS is a failure:
4857	// - if the CAS is a success, the coherence mechanism
4858	// updates the local copy.
4859	// - if the CAS is a failure, we just retry the write.
4860	{
4861	// coherence clack request (from DSPIN CLACK)
4862	if (r_dcache_clack_req.read())
4863	{
4864	r_dcache_fsm = DCACHE_CC_CHECK;
4865	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4866	break;
4867	}
4868
4869	// coherence request (from CC_RECEIVE FSM)
4870	if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
4871	{
4872	r_dcache_fsm = DCACHE_CC_CHECK;
4873	r_dcache_fsm_cc_save = r_dcache_fsm.read();
4874	break;
4875	}
4876
4877	if (r_vci_rsp_data_error.read()) // bus error
4878	{
4879	std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
4880	std::cout << "This should not happen in this state" << std::endl;
4881	exit(0);
4882	}
4883	else if (r_vci_rsp_fifo_dcache.rok()) // response available
4884	{
4885	vci_rsp_fifo_dcache_get = true;
4886	r_dcache_fsm = DCACHE_IDLE;
4887
4888	#if DEBUG_DCACHE
4889	if (m_debug_dcache_fsm)
4890	{
4891	std::cout << " <PROC " << name()
4892	<< " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
4893	}
4894	#endif
4895	}
4896	break;
4897	}
4898	/////////////////////
4899	case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM
4900	// handling coherence requests for DCACHE.
4901	// If there is a matching pending miss on the modified cache
4902	// line this is signaled in the r_dcache_miss inval flip-flop.
4903	// If the updated (or invalidated) cache line has copies in TLBs
4904	// these TLB copies are invalidated.
4905	// The return state is defined in r_dcache_fsm_cc_save
4906	{
4907	paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
4908	paddr_t mask = ~((m_dcache_words << 2) - 1);
4909
4910	// CLACK handler
4911	// We switch the directory slot to EMPTY state and reset
4912	// r_dcache_miss_clack if the cleanup ack is matching a pending miss.
4913	if (r_dcache_clack_req.read())
4914	{
4915	if (m_dreq.valid ) m_cost_data_miss_frz++;
4916
4917	#ifdef INSTRUMENTATION
4918	m_cpt_dcache_dir_write++;
4919	#endif
4920	r_dcache.write_dir(0,
4921	r_dcache_clack_way.read(),
4922	r_dcache_clack_set.read(),
4923	CACHE_SLOT_STATE_EMPTY);
4924
4925	if ((r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
4926	(r_dcache_miss_way.read() == r_dcache_clack_way.read()))
4927	{
4928	r_dcache_miss_clack = false;
4929	}
4930
4931	r_dcache_clack_req = false;
4932
4933	// return to cc_save state
4934	r_dcache_fsm = r_dcache_fsm_cc_save.read() ;
4935
4936	#if DEBUG_DCACHE
4937	if (m_debug_dcache_fsm)
4938	{
4939	std::cout << " <PROC " << name()
4940	<< " DCACHE_CC_CHECK> CLACK for PADDR " << paddr
4941	<< " Switch slot to EMPTY state : "
4942	<< " set = " << r_dcache_clack_set.read()
4943	<< " / way = " << r_dcache_clack_way.read() << std::endl;
4944	}
4945	#endif
4946	break;
4947	}
4948
4949	assert(not r_dcache_cc_send_req.read() and
4950	"CC_SEND must be available in DCACHE_CC_CHECK");
4951
4952	// Match between MISS address and CC address
4953	if (r_cc_receive_dcache_req.read() and
4954	((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or
4955	(r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or
4956	(r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
4957	((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
4958	{
4959	// signaling matching
4960	r_dcache_miss_inval = true;
4961
4962	// in case of update, go to CC_UPDT
4963	// JUST TO POP THE FIFO
4964	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
4965	{
4966	r_dcache_fsm = DCACHE_CC_UPDT;
4967	r_dcache_cc_word = r_cc_receive_word_idx.read();
4968
4969	// just pop the fifo , don't write in icache
4970	r_dcache_cc_need_write = false;
4971	}
4972	// the request is dealt with
4973	else
4974	{
4975	r_cc_receive_dcache_req = false;
4976	r_dcache_fsm = r_dcache_fsm_cc_save.read();
4977	}
4978
4979	#if DEBUG_DCACHE
4980	if (m_debug_dcache_fsm)
4981	{
4982	std::cout << " <PROC " << name()
4983	<< " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
4984	<< " PADDR = " << std::hex << paddr << std::endl;
4985	}
4986	#endif
4987	}
4988
4989	// CC request handler
4990
4991	int state = 0;
4992	size_t way = 0;
4993	size_t set = 0;
4994	size_t word = 0;
4995
4996	#ifdef INSTRUMENTATION
4997	m_cpt_dcache_dir_read++;
4998	#endif
4999	r_dcache.read_dir(paddr,
5000	&state,
5001	&way,
5002	&set,
5003	&word); // unused
5004
5005	r_dcache_cc_way = way;
5006	r_dcache_cc_set = set;
5007
5008	if (state == CACHE_SLOT_STATE_VALID) // hit
5009	{
5010	// need to update the cache state
5011	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update
5012	{
5013	r_dcache_cc_need_write = true;
5014	r_dcache_fsm = DCACHE_CC_UPDT;
5015	r_dcache_cc_word = r_cc_receive_word_idx.read();
5016	}
5017	else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval
5018	{
5019	r_dcache_fsm = DCACHE_CC_INVAL;
5020	}
5021	}
5022	else // miss
5023	{
5024	// multicast acknowledgement required in case of update
5025	if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
5026	{
5027	r_dcache_fsm = DCACHE_CC_UPDT;
5028	r_dcache_cc_word = r_cc_receive_word_idx.read();
5029
5030	// just pop the fifo , don't write in icache
5031	r_dcache_cc_need_write = false;
5032	}
5033	else // No response needed
5034	{
5035	r_cc_receive_dcache_req = false;
5036	r_dcache_fsm = r_dcache_fsm_cc_save.read();
5037	}
5038	}
5039
5040	#if DEBUG_DCACHE
5041	if (m_debug_dcache_fsm)
5042	{
5043	std::cout << " <PROC " << name()
5044	<< " DCACHE_CC_CHECK> Coherence request received:"
5045	<< " PADDR = " << std::hex << paddr
5046	<< " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
5047	<< " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl;
5048	}
5049	#endif
5050
5051	break;
5052	}
5053	/////////////////////
5054	case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
5055	// CLEANUP after possible invalidation of copies in
5056	// TLBs
5057	{
5058	size_t way = r_dcache_cc_way.read();
5059	size_t set = r_dcache_cc_set.read();
5060
5061	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
5062	{
5063	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
5064	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
5065	r_dcache_tlb_inval_set = 0;
5066	r_dcache_fsm_scan_save = r_dcache_fsm.read();
5067	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
5068	break;
5069	}
5070
5071	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
5072	{
5073	r_itlb.reset();
5074	r_dtlb.reset();
5075	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
5076
5077	#if DEBUG_DCACHE
5078	if (m_debug_dcache_fsm)
5079	{
5080	std::cout << " <PROC " << name()
5081	<< " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
5082	}
5083	#endif
5084	}
5085
5086	assert(not r_dcache_cc_send_req.read() &&
5087	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
5088	"must not be set");
5089
5090	// Switch slot state to ZOMBI and send CLEANUP command
5091	r_dcache.write_dir(way,
5092	set,
5093	CACHE_SLOT_STATE_ZOMBI);
5094
5095	// coherence request completed
5096	r_cc_receive_dcache_req = false;
5097	r_dcache_cc_send_req = true;
5098	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
5099	r_dcache_cc_send_way = r_dcache_cc_way.read();
5100	r_dcache_cc_send_type = CC_TYPE_CLEANUP;
5101	r_dcache_fsm = r_dcache_fsm_cc_save.read();
5102
5103	#if DEBUG_DCACHE
5104	if (m_debug_dcache_fsm)
5105	{
5106	std::cout << " <PROC " << name()
5107	<< " DCACHE_CC_INVAL> Switch slot to EMPTY state:" << std::dec
5108	<< " / WAY = " << way
5109	<< " / SET = " << set << std::endl;
5110	}
5111	#endif
5112	break;
5113	}
5114	///////////////////
5115	case DCACHE_CC_UPDT: // hit update: write one word per cycle,
5116	// after possible invalidation of copies in TLBs
5117	{
5118	size_t word = r_dcache_cc_word.read();
5119	size_t way = r_dcache_cc_way.read();
5120	size_t set = r_dcache_cc_set.read();
5121
5122	if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval
5123	{
5124	r_dcache_in_tlb[way * m_dcache_sets + set] = false;
5125	r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
5126	r_dcache_tlb_inval_set = 0;
5127	r_dcache_fsm_scan_save = r_dcache_fsm.read();
5128	r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
5129
5130	break;
5131	}
5132
5133	if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush
5134	{
5135	r_itlb.reset();
5136	r_dtlb.reset();
5137	r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
5138
5139	#if DEBUG_DCACHE
5140	if (m_debug_dcache_fsm)
5141	{
5142	std::cout << " <PROC " << name()
5143	<< " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
5144	}
5145	#endif
5146	}
5147
5148	assert (not r_dcache_cc_send_req.read() &&
5149	"ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
5150	"must not be set");
5151
5152	if (not r_cc_receive_updt_fifo_be.rok()) break;
5153
5154	if (r_dcache_cc_need_write.read())
5155	{
5156
5157	#ifdef INSTRUMENTATION
5158	m_cpt_dcache_data_write++;
5159	#endif
5160	r_dcache.write(way,
5161	set,
5162	word,
5163	r_cc_receive_updt_fifo_data.read(),
5164	r_cc_receive_updt_fifo_be.read());
5165
5166	r_dcache_cc_word = word + 1;
5167
5168	#if DEBUG_DCACHE
5169	if (m_debug_dcache_fsm)
5170	{
5171	std::cout << " <PROC " << name()
5172	<< " DCACHE_CC_UPDT> Write one word" << std::dec
5173	<< " / WAY = " << way
5174	<< " / SET = " << set
5175	<< " / WORD = " << word
5176	<< " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
5177	}
5178	#endif
5179	}
5180
5181	if (r_cc_receive_updt_fifo_eop.read()) // last word
5182	{
5183	// no need to write in the cache anymore
5184	r_dcache_cc_need_write = false;
5185
5186	// coherence request completed
5187	r_cc_receive_dcache_req = false;
5188
5189	// request multicast acknowledgement
5190	r_dcache_cc_send_req = true;
5191	r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
5192	r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
5193	r_dcache_cc_send_type = CC_TYPE_MULTI_ACK;
5194	r_dcache_fsm = r_dcache_fsm_cc_save.read();
5195	}
5196
5197	//consume fifo if not eop
5198	cc_receive_updt_fifo_get = true;
5199
5200	break;
5201	}
5202	///////////////////////////
5203	case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB
5204	// It makes assumption: m_itlb_sets == m_dtlb_sets
5205	// All ways are handled in parallel.
5206	// We enter this state when a DCACHE line is modified,
5207	// and there is a copy in itlb or dtlb.
5208	// It can be caused by:
5209	// - a coherence inval or updt transaction,
5210	// - a line inval caused by a cache miss
5211	// - a processor XTN inval request,
5212	// - a WRITE hit,
5213	// - a Dirty bit update
5214	// Input arguments are:
5215	// - r_dcache_tlb_inval_line
5216	// - r_dcache_tlb_inval_set
5217	// - r_dcache_fsm_scan_save
5218	{
5219	paddr_t line = r_dcache_tlb_inval_line.read();
5220	size_t set = r_dcache_tlb_inval_set.read();
5221	size_t way;
5222	bool ok;
5223
5224	for (way = 0; way < m_itlb_ways; way++)
5225	{
5226	ok = r_itlb.inval(line, way, set);
5227
5228	#if DEBUG_DCACHE
5229	if (m_debug_dcache_fsm and ok)
5230	{
5231	std::cout << " <PROC " << name()
5232	<< ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
5233	<< " line = " << line << std::dec
5234	<< " / set = " << set
5235	<< " / way = " << way << std::endl;
5236	}
5237	#endif
5238	}
5239
5240	for (way = 0; way < m_dtlb_ways; way++)
5241	{
5242	ok = r_dtlb.inval( line, way, set);
5243
5244	#if DEBUG_DCACHE
5245	if (m_debug_dcache_fsm and ok)
5246	std::cout << " <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
5247	<< " Invalidate DTLB entry" << std::hex
5248	<< " / line = " << line << std::dec
5249	<< " / set = " << set
5250	<< " / way = " << way << std::endl;
5251	#endif
5252	}
5253
5254	// return to the calling state when TLB inval completed
5255	if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1))
5256	{
5257	r_dcache_fsm = r_dcache_fsm_scan_save.read();
5258	}
5259	r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1;
5260	break;
5261	}
5262	} // end switch r_dcache_fsm
5263
5264	///////////////// wbuf update ///////////////////////////////////////////////////////
5265	r_wbuf.update();
5266
5267	///////////////// llsc update ///////////////////////////////////////////////////////
5268	if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1;
5269	if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false;
5270
5271	//////////////// test processor frozen //////////////////////////////////////////////
5272	// The simulation exit if the number of consecutive frozen cycles
5273	// is larger than the m_max_frozen_cycles (constructor parameter)
5274	if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid))
5275	{
5276	m_cpt_frz_cycles++; // used for instrumentation
5277	m_cpt_stop_simulation++; // used for debug
5278	if (m_cpt_stop_simulation > m_max_frozen_cycles)
5279	{
5280	std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
5281	<< " stop at cycle " << m_cpt_total_cycles << std::endl
5282	<< " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles
5283	<< std::endl;
5284	r_iss.dump();
5285	exit(1);
5286	}
5287	}
5288	else
5289	{
5290	m_cpt_stop_simulation = 0;
5291	}
5292
5293	/////////// execute one iss cycle /////////////////////////////////
5294	{
5295	uint32_t it = 0;
5296	for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) if (p_irq[i].read()) it \|= (1 << i);
5297	r_iss.executeNCycles(1, m_irsp, m_drsp, it);
5298	}
5299
5300	////////////////////////////////////////////////////////////////////////////
5301	// The VCI_CMD FSM controls the following ressources:
5302	// - r_vci_cmd_fsm
5303	// - r_vci_cmd_min
5304	// - r_vci_cmd_max
5305	// - r_vci_cmd_cpt
5306	// - r_vci_cmd_imiss_prio
5307	// - wbuf (reset)
5308	// - r_icache_miss_req (reset)
5309	// - r_icache_unc_req (reset)
5310	// - r_dcache_vci_miss_req (reset)
5311	// - r_dcache_vci_unc_req (reset)
5312	// - r_dcache_vci_ll_req (reset)
5313	// - r_dcache_vci_sc_req (reset in case of local sc fail)
5314	// - r_dcache_vci_cas_req (reset)
5315	//
5316	// This FSM handles requests from both the DCACHE FSM & the ICACHE FSM.
5317	// There are 8 request types, with the following priorities :
5318	// 1 - Data Read Miss : r_dcache_vci_miss_req and miss in the write buffer
5319	// 2 - Data Read Uncachable : r_dcache_vci_unc_req
5320	// 3 - Instruction Miss : r_icache_miss_req and miss in the write buffer
5321	// 4 - Instruction Uncachable : r_icache_unc_req
5322	// 5 - Data Write : r_wbuf.rok()
5323	// 6 - Data Linked Load : r_dcache_vci_ll_req
5324	// 7 - Data Store Conditionnal: r_dcache_vci_sc_req
5325	// 8 - Compare And Swap : r_dcache_vci_cas_req
5326	//
5327	// As we want to support several simultaneous VCI transactions, the VCI_CMD_FSM
5328	// and the VCI_RSP_FSM are fully desynchronized.
5329	//
5330	// VCI formats:
5331	// According to the VCI advanced specification, all read requests packets
5332	// (data Uncached, Miss data, instruction Uncached, Miss instruction)
5333	// are one word packets.
5334	// For write burst packets, all words are in the same cache line,
5335	// and addresses must be contiguous (the BE field is 0 in case of "holes").
5336	// The sc command packet implements actually a compare-and-swap mechanism
5337	// and the packet contains two flits.
5338	////////////////////////////////////////////////////////////////////////////////////
5339
5340
5341	switch (r_vci_cmd_fsm.read())
5342	{
5343	//////////////
5344	case CMD_IDLE:
5345	{
5346	// DCACHE read requests (r_dcache_vci_miss_req or r_dcache_vci_ll_req), and
5347	// ICACHE read requests (r_icache_miss_req) require both a write_buffer access
5348	// to check a possible pending write on the same cache line.
5349	// As there is only one possible access per cycle to write buffer, we implement
5350	// a round-robin priority between DCACHE and ICACHE for this access,
5351	// using the r_vci_cmd_imiss_prio flip-flop.
5352
5353	size_t wbuf_min;
5354	size_t wbuf_max;
5355
5356	bool dcache_miss_req = r_dcache_vci_miss_req.read() and
5357	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5358
5359	bool dcache_ll_req = r_dcache_vci_ll_req.read() and
5360	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5361
5362	bool dcache_sc_req = r_dcache_vci_sc_req.read() and
5363	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5364
5365	bool dcache_cas_req = r_dcache_vci_cas_req.read() and
5366	(not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
5367
5368	bool icache_miss_req = r_icache_miss_req.read() and
5369	(not (r_dcache_vci_miss_req.read() or
5370	r_dcache_vci_ll_req.read() or
5371	r_dcache_vci_cas_req.read() or
5372	r_dcache_vci_sc_req.read()) or
5373	r_vci_cmd_imiss_prio.read());
5374
5375	// 1 - Data unc write
5376	if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
5377	{
5378	r_vci_cmd_fsm = CMD_DATA_UNC_WRITE;
5379	r_dcache_vci_unc_req = false;
5380	}
5381	// 2 data read miss
5382	else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5383	{
5384	r_vci_cmd_fsm = CMD_DATA_MISS;
5385	r_dcache_vci_miss_req = false;
5386	r_vci_cmd_imiss_prio = true;
5387	}
5388	// 3 - Data Read Uncachable
5389	else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read())
5390	{
5391	r_vci_cmd_fsm = CMD_DATA_UNC_READ;
5392	r_dcache_vci_unc_req = false;
5393	}
5394	// 4 - Data Linked Load
5395	else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5396	{
5397	r_vci_cmd_fsm = CMD_DATA_LL;
5398	r_dcache_vci_ll_req = false;
5399	r_vci_cmd_imiss_prio = true;
5400	}
5401	// 5 - Instruction Miss
5402	else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()))
5403	{
5404	r_vci_cmd_fsm = CMD_INS_MISS;
5405	r_icache_miss_req = false;
5406	r_vci_cmd_imiss_prio = false;
5407	}
5408	// 6 - Instruction Uncachable
5409	else if (r_icache_unc_req.read())
5410	{
5411	r_vci_cmd_fsm = CMD_INS_UNC;
5412	r_icache_unc_req = false;
5413	}
5414	// 7 - Data Write
5415	else if (r_wbuf.rok(&wbuf_min, &wbuf_max))
5416	{
5417	r_vci_cmd_fsm = CMD_DATA_WRITE;
5418	r_vci_cmd_cpt = wbuf_min;
5419	r_vci_cmd_min = wbuf_min;
5420	r_vci_cmd_max = wbuf_max;
5421	}
5422	// 8 - Data Store Conditionnal
5423	else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5424	{
5425	r_vci_cmd_fsm = CMD_DATA_SC;
5426	r_dcache_vci_sc_req = false;
5427	r_vci_cmd_imiss_prio = true;
5428	r_vci_cmd_cpt = 0;
5429	}
5430	// 9 - Compare And Swap
5431	else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
5432	{
5433	r_vci_cmd_fsm = CMD_DATA_CAS;
5434	r_dcache_vci_cas_req = false;
5435	r_vci_cmd_imiss_prio = true;
5436	r_vci_cmd_cpt = 0;
5437	}
5438
5439	#if DEBUG_CMD
5440	if (m_debug_cmd_fsm )
5441	{
5442	std::cout << " <PROC " << name() << " CMD_IDLE>"
5443	<< " / dmiss_req = " << dcache_miss_req
5444	<< " / imiss_req = " << icache_miss_req
5445	<< std::endl;
5446	}
5447	#endif
5448	break;
5449	}
5450	////////////////////
5451	case CMD_DATA_WRITE:
5452	{
5453	if (p_vci.cmdack.read())
5454	{
5455	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5456	if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
5457	{
5458	r_vci_cmd_fsm = CMD_IDLE;
5459	r_wbuf.sent();
5460	}
5461	}
5462	break;
5463	}
5464	/////////////////
5465	case CMD_DATA_SC:
5466	case CMD_DATA_CAS:
5467	{
5468	// The CAS and SC VCI commands contain two flits
5469	if (p_vci.cmdack.read())
5470	{
5471	r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
5472	if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ;
5473	}
5474	break;
5475	}
5476	//////////////////
5477	case CMD_INS_MISS:
5478	case CMD_INS_UNC:
5479	case CMD_DATA_MISS:
5480	case CMD_DATA_UNC_READ:
5481	case CMD_DATA_UNC_WRITE:
5482	case CMD_DATA_LL:
5483	{
5484	// all read VCI commands contain one single flit
5485	if (p_vci.cmdack.read()) {
5486	r_vci_cmd_fsm = CMD_IDLE;
5487	}
5488	break;
5489	}
5490
5491	} // end switch r_vci_cmd_fsm
5492
5493	//////////////////////////////////////////////////////////////////////////
5494	// The VCI_RSP FSM controls the following ressources:
5495	// - r_vci_rsp_fsm:
5496	// - r_vci_rsp_fifo_icache (push)
5497	// - r_vci_rsp_fifo_dcache (push)
5498	// - r_vci_rsp_data_error (set)
5499	// - r_vci_rsp_ins_error (set)
5500	// - r_vci_rsp_cpt
5501	// - r_dcache_vci_sc_req (reset when SC response recieved)
5502	//
5503	// As the VCI_RSP and VCI_CMD are fully desynchronized to support several
5504	// simultaneous VCI transactions, this FSM uses the VCI RPKTID field
5505	// to identify the transactions.
5506	//
5507	// VCI vormat:
5508	// This component checks the response packet length and accepts only
5509	// single word packets for write response packets.
5510	//
5511	// Error handling:
5512	// This FSM analyzes the VCI error code and signals directly the Write Bus Error.
5513	// In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error
5514	// flip_flop and the error is signaled by the DCACHE FSM.
5515	// In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error
5516	// flip_flop and the error is signaled by the ICACHE FSM.
5517	// In case of Cleanup Error, the simulation stops with an error message...
5518	//////////////////////////////////////////////////////////////////////////
5519
5520	switch (r_vci_rsp_fsm.read())
5521	{
5522	//////////////
5523	case RSP_IDLE:
5524	{
5525	if (p_vci.rspval.read())
5526	{
5527	r_vci_rsp_cpt = 0;
5528
5529	if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC)
5530	{
5531	// debug: verify that the available response concerns the current transaction.
5532	if (r_dcache_wdt_timeout.read() != p_vci.rtrdid.read())
5533	{
5534	std::cout << name() << ": Late response received after TIMEOUT "
5535	<< std::dec << "(cycle " << m_cpt_total_cycles << ")"
5536	<< std::endl;
5537
5538	exit(1);
5539	}
5540
5541	r_vci_rsp_fsm = RSP_DATA_UNC;
5542	}
5543	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS)
5544	{
5545	// debug: verify that the available response concerns the current transaction.
5546	if (r_dcache_wdt_timeout.read() != p_vci.rtrdid.read())
5547	{
5548	std::cout << name() << ": Late response received after TIMEOUT "
5549	<< std::dec << "(cycle " << m_cpt_total_cycles << ")"
5550	<< std::endl;
5551
5552	exit(1);
5553	}
5554
5555	r_vci_rsp_fsm = RSP_DATA_MISS;
5556	}
5557	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC)
5558	{
5559	r_vci_rsp_fsm = RSP_INS_UNC;
5560	}
5561	else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS)
5562	{
5563	r_vci_rsp_fsm = RSP_INS_MISS;
5564	}
5565	else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE)
5566	{
5567	r_vci_rsp_fsm = RSP_DATA_WRITE;
5568	}
5569	else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS)
5570	{
5571	r_vci_rsp_fsm = RSP_DATA_UNC;
5572	}
5573	else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL)
5574	{
5575	r_vci_rsp_fsm = RSP_DATA_LL;
5576	}
5577	else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC)
5578	{
5579	r_vci_rsp_fsm = RSP_DATA_UNC;
5580	}
5581	else
5582	{
5583	assert(false and "Unexpected VCI response");
5584	}
5585	}
5586	break;
5587	}
5588	//////////////////
5589	case RSP_INS_MISS:
5590	{
5591	if (p_vci.rspval.read())
5592	{
5593	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5594	{
5595	r_vci_rsp_ins_error = true;
5596	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5597	}
5598	else // no error reported
5599	{
5600	if (r_vci_rsp_fifo_icache.wok())
5601	{
5602	if (r_vci_rsp_cpt.read() >= m_icache_words)
5603	{
5604	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5605	<< " VCI response packet too long "
5606	<< " for instruction miss" << std::endl;
5607	exit(0);
5608	}
5609	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5610	vci_rsp_fifo_icache_put = true,
5611	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5612	if (p_vci.reop.read())
5613	{
5614	if (r_vci_rsp_cpt.read() != (m_icache_words - 1))
5615	{
5616	std::cout << "ERROR in VCI_CC_VCACHE " << name()
5617	<< " VCI response packet too short"
5618	<< " for instruction miss" << std::endl;
5619	exit(0);
5620	}
5621	r_vci_rsp_fsm = RSP_IDLE;
5622	}
5623	}
5624	}
5625	}
5626	break;
5627	}
5628	/////////////////
5629	case RSP_INS_UNC:
5630	{
5631	if (p_vci.rspval.read())
5632	{
5633	assert(p_vci.reop.read() and
5634	"illegal VCI response packet for uncachable instruction");
5635
5636	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5637	{
5638	r_vci_rsp_ins_error = true;
5639	r_vci_rsp_fsm = RSP_IDLE;
5640	}
5641	else // no error reported
5642	{
5643	if (r_vci_rsp_fifo_icache.wok())
5644	{
5645	vci_rsp_fifo_icache_put = true;
5646	vci_rsp_fifo_icache_data = p_vci.rdata.read();
5647	r_vci_rsp_fsm = RSP_IDLE;
5648	}
5649	}
5650	}
5651	break;
5652	}
5653	///////////////////
5654	case RSP_DATA_MISS:
5655	{
5656	if (p_vci.rspval.read())
5657	{
5658	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5659	{
5660	r_vci_rsp_data_error = true;
5661	if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
5662	}
5663	else // no error reported
5664	{
5665	if (r_vci_rsp_fifo_dcache.wok())
5666	{
5667	assert((r_vci_rsp_cpt.read() < m_dcache_words) and
5668	"The VCI response packet for data miss is too long");
5669
5670	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5671	vci_rsp_fifo_dcache_put = true,
5672	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5673	if (p_vci.reop.read())
5674	{
5675	assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and
5676	"The VCI response packet for data miss is too short");
5677
5678	r_vci_rsp_fsm = RSP_IDLE;
5679	}
5680	}
5681	}
5682	}
5683	break;
5684	}
5685	//////////////////
5686	case RSP_DATA_UNC:
5687	{
5688	if (p_vci.rspval.read())
5689	{
5690	assert(p_vci.reop.read() and
5691	"illegal VCI response packet for uncachable read data");
5692
5693	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5694	{
5695	r_vci_rsp_data_error = true;
5696	r_vci_rsp_fsm = RSP_IDLE;
5697	}
5698	else // no error reported
5699	{
5700	if (r_vci_rsp_fifo_dcache.wok())
5701	{
5702	vci_rsp_fifo_dcache_put = true;
5703	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5704	r_vci_rsp_fsm = RSP_IDLE;
5705	}
5706	}
5707	}
5708	break;
5709	}
5710	/////////////////
5711	case RSP_DATA_LL:
5712	{
5713	if (p_vci.rspval.read())
5714	{
5715	if ((p_vci.rerror.read() & 0x1) != 0) // error reported
5716	{
5717	r_vci_rsp_data_error = true;
5718	r_vci_rsp_fsm = RSP_IDLE;
5719	break;
5720	}
5721	if (r_vci_rsp_cpt.read() == 0) //first flit
5722	{
5723	if (r_vci_rsp_fifo_dcache.wok())
5724	{
5725	assert(!p_vci.reop.read() &&
5726	"illegal VCI response packet for LL");
5727	vci_rsp_fifo_dcache_put = true;
5728	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5729	r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1;
5730	}
5731	break;
5732	}
5733	else // last flit
5734	{
5735	if (r_vci_rsp_fifo_dcache.wok())
5736	{
5737	assert(p_vci.reop.read() &&
5738	"illegal VCI response packet for LL");
5739	vci_rsp_fifo_dcache_put = true;
5740	vci_rsp_fifo_dcache_data = p_vci.rdata.read();
5741	r_vci_rsp_fsm = RSP_IDLE;
5742	}
5743	break;
5744	}
5745	}
5746	break;
5747	}
5748	////////////////////
5749	case RSP_DATA_WRITE:
5750	{
5751	if (p_vci.rspval.read())
5752	{
5753	assert(p_vci.reop.read() and
5754	"a VCI response packet must contain one flit for a write transaction");
5755
5756	r_vci_rsp_fsm = RSP_IDLE;
5757	uint32_t wbuf_index = p_vci.rtrdid.read();
5758	r_wbuf.completed(wbuf_index);
5759	if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr();
5760	}
5761	break;
5762	}
5763	} // end switch r_vci_rsp_fsm
5764
5765	/////////////////////////////////////////////////////////////////////////////////////
5766	// The CC_SEND FSM is in charge of sending cleanups and the multicast
5767	// acknowledgements on the coherence network. It has two clients (DCACHE FSM
5768	// and ICACHE FSM) that are served with a round-robin priority.
5769	// The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as
5770	// soon as the request has been sent.
5771	/////////////////////////////////////////////////////////////////////////////////////
5772	switch (r_cc_send_fsm.read())
5773	{
5774	///////////////////////////
5775	case CC_SEND_IDLE:
5776	{
5777	///////////////////////////////////////////////////////
5778	// Handle CC_TEST request //
5779	///////////////////////////////////////////////////////
5780	if (r_cc_test_to_cc_send_req.read())
5781	{
5782	r_cc_send_fsm = CC_SEND_TEST_HEADER;
5783	break;
5784	}
5785
5786	///////////////////////////////////////////////////////
5787	// handling round robin between icache and dcache : //
5788	// we first check for the last client and listen for //
5789	// a request of the other, then update the client //
5790	// r_cc_send_last_client : 0 dcache / 1 icache
5791	///////////////////////////////////////////////////////
5792	bool update_last_client = r_cc_send_last_client.read();
5793	if (r_cc_send_last_client.read() == 0) // last client was dcache
5794	{
5795	if (r_icache_cc_send_req.read()) // request from icache
5796	update_last_client = 1; // update last client to icache
5797	}
5798	else // last client was icache
5799	{
5800	if (r_dcache_cc_send_req.read()) // request from dcache
5801	update_last_client = 0; // update last client to dcache
5802	}
5803	r_cc_send_last_client = update_last_client;
5804
5805	// if there is an actual request
5806	if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read())
5807	{
5808	// the new client is dcache and has a cleanup request
5809	if ((update_last_client == 0) and
5810	(r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
5811	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5812	// the new client is dcache and has a multi acknowledgement request
5813	else if ((update_last_client == 0) and
5814	(r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5815	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5816	// the new client is icache and has a cleanup request
5817	else if ((update_last_client == 1) and
5818	(r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
5819	r_cc_send_fsm = CC_SEND_CLEANUP_1;
5820	// the new client is icache and has a multi acknowledgement request
5821	else if ((update_last_client == 1) and
5822	(r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
5823	r_cc_send_fsm = CC_SEND_MULTI_ACK;
5824	}
5825	break;
5826	}
5827	///////////////////////////
5828	case CC_SEND_CLEANUP_1:
5829	{
5830	// wait for the first flit to be consumed
5831	if (p_dspin_p2m.read.read())
5832	r_cc_send_fsm = CC_SEND_CLEANUP_2;
5833
5834	break;
5835	}
5836	///////////////////////////
5837	case CC_SEND_CLEANUP_2:
5838	{
5839	// wait for the second flit to be consumed
5840	if (p_dspin_p2m.read.read())
5841	{
5842	if (r_cc_send_last_client.read() == 0) // dcache active request
5843	r_dcache_cc_send_req = false; // reset dcache request
5844	else // icache active request
5845	r_icache_cc_send_req = false; // reset icache request
5846
5847	// go back to idle state
5848	r_cc_send_fsm = CC_SEND_IDLE;
5849	}
5850	break;
5851	}
5852	///////////////////////////
5853	case CC_SEND_MULTI_ACK:
5854	{
5855	// wait for the flit to be consumed
5856	if (p_dspin_p2m.read.read())
5857	{
5858	if (r_cc_send_last_client.read() == 0) // dcache active request
5859	r_dcache_cc_send_req = false; // reset dcache request
5860	else // icache active request
5861	r_icache_cc_send_req = false; // reset icache request
5862	// go back to idle state
5863	r_cc_send_fsm = CC_SEND_IDLE;
5864	}
5865	break;
5866	}
5867	///////////////////////////
5868	case CC_SEND_TEST_HEADER:
5869	{
5870	// the r_cc_test_to_cc_send_req can be reset by the CC_TEST FSM
5871	// when there is a watchdog timeout
5872	if (not r_cc_test_to_cc_send_req.read())
5873	{
5874	r_cc_send_fsm = CC_SEND_IDLE;
5875	break;
5876	}
5877
5878	if (not p_dspin_p2m.read.read()) break;
5879	r_cc_send_fsm = CC_SEND_TEST_SIGNATURE;
5880	break;
5881	}
5882	///////////////////////////
5883	case CC_SEND_TEST_SIGNATURE:
5884	{
5885	// the r_cc_test_to_cc_send_req can be reset by the CC_TEST FSM
5886	// when there is a watchdog timeout
5887	if (not p_dspin_p2m.read.read() and r_cc_test_to_cc_send_req.read()) break;
5888	r_cc_test_to_cc_send_req = false;
5889	r_cc_send_fsm = CC_SEND_IDLE;
5890	break;
5891	}
5892	} // end switch CC_SEND FSM
5893
5894	///////////////////////////////////////////////////////////////////////////////
5895	// CC_RECEIVE FSM
5896	// This FSM receive all coherence packets on a DSPIN40 port.
5897	// There is 5 packet types:
5898	// - CC_DATA_INVAL : DCACHE invalidate request
5899	// - CC_DATA_UPDT : DCACHE update request (multi-words)
5900	// - CC_INST_INVAL : ICACHE invalidate request
5901	// - CC_INST_UPDT : ICACHE update request (multi-words)
5902	// - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE)
5903	// - CC_TEST_M2P : M2P coherence network test packet
5904	//////////////////////////////////////////////////////////////////////////////
5905	switch (r_cc_receive_fsm.read())
5906	{
5907	/////////////////////
5908	case CC_RECEIVE_IDLE:
5909	{
5910	// a coherence request has arrived
5911	if (p_dspin_m2p.write.read())
5912	{
5913	// initialize dspin received data
5914	uint64_t receive_data = p_dspin_m2p.data.read();
5915
5916	// coherence test packet (CC_TEST_M2P)
5917	if (DspinDhccpParam::dspin_get(receive_data, DspinDhccpParam::TEST_M2P_TEST))
5918	{
5919	r_cc_receive_fsm = CC_RECEIVE_TEST_HEADER;
5920	break;
5921	}
5922
5923	// initialize coherence packet type
5924	uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data,
5925	DspinDhccpParam::M2P_TYPE);
5926	// test for a broadcast
5927	if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))
5928	{
5929	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
5930	}
5931	// test for a multi updt
5932	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA)
5933	{
5934	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
5935	}
5936	else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST)
5937	{
5938	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER;
5939	}
5940	// test for a multi inval
5941	else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA)
5942	{
5943	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER;
5944	}
5945	else
5946	{
5947	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER;
5948	}
5949	}
5950	break;
5951	}
5952	///////////////////////////////
5953	case CC_RECEIVE_BRDCAST_HEADER:
5954	{
5955	// no actual data in the HEADER, just skip to second flit
5956	r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE;
5957	break;
5958	}
5959	//////////////////////////////
5960	case CC_RECEIVE_BRDCAST_NLINE:
5961	{
5962	// initialize dspin received data
5963	uint64_t receive_data = p_dspin_m2p.data.read();
5964	// wait for both dcache and icache to take the request
5965	if (not (r_cc_receive_icache_req.read()) and
5966	not (r_cc_receive_dcache_req.read()) and
5967	(p_dspin_m2p.write.read()))
5968	{
5969	// request dcache to handle the BROADCAST
5970	r_cc_receive_dcache_req = true;
5971	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,
5972	DspinDhccpParam::BROADCAST_NLINE);
5973	r_cc_receive_dcache_type = CC_TYPE_INVAL;
5974	// request icache to handle the BROADCAST
5975	r_cc_receive_icache_req = true;
5976	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,
5977	DspinDhccpParam::BROADCAST_NLINE);
5978	r_cc_receive_icache_type = CC_TYPE_INVAL;
5979	// get back to idle state
5980	r_cc_receive_fsm = CC_RECEIVE_IDLE;
5981	break;
5982	}
5983	// keep waiting for the caches to accept the request
5984	break;
5985	}
5986	/////////////////////////////
5987	case CC_RECEIVE_DATA_INVAL_HEADER:
5988	{
5989	// sample updt tab index in the HEADER, then skip to second flit
5990	r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE;
5991	break;
5992	}
5993	/////////////////////////////
5994	case CC_RECEIVE_INS_INVAL_HEADER:
5995	{
5996	// sample updt tab index in the HEADER, then skip to second flit
5997	r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE;
5998	break;
5999	}
6000	////////////////////////////
6001	case CC_RECEIVE_DATA_INVAL_NLINE:
6002	{
6003	// sample nline in the second flit
6004	uint64_t receive_data = p_dspin_m2p.data.read();
6005	// for data INVAL, wait for dcache to take the request
6006	if (p_dspin_m2p.write.read() and
6007	not r_cc_receive_dcache_req.read())
6008	{
6009	// request dcache to handle the INVAL
6010	r_cc_receive_dcache_req = true;
6011	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
6012	r_cc_receive_dcache_type = CC_TYPE_INVAL;
6013	// get back to idle state
6014	r_cc_receive_fsm = CC_RECEIVE_IDLE;
6015	break;
6016	}
6017	break;
6018	}
6019	//////////////////////////////
6020	case CC_RECEIVE_INS_INVAL_NLINE:
6021	{
6022	// sample nline in the second flit
6023	uint64_t receive_data = p_dspin_m2p.data.read();
6024	// for ins INVAL, wait for icache to take the request
6025	if (p_dspin_m2p.write.read() and
6026	not r_cc_receive_icache_req.read())
6027	{
6028	// request icache to handle the INVAL
6029	r_cc_receive_icache_req = true;
6030	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);
6031	r_cc_receive_icache_type = CC_TYPE_INVAL;
6032	// get back to idle state
6033	r_cc_receive_fsm = CC_RECEIVE_IDLE;
6034	break;
6035	}
6036	break;
6037	}
6038	////////////////////////////
6039	case CC_RECEIVE_DATA_UPDT_HEADER:
6040	{
6041	// sample updt tab index in the HEADER, than skip to second flit
6042	uint64_t receive_data = p_dspin_m2p.data.read();
6043	// for data INVAL, wait for dcache to take the request and fifo to
6044	// be empty
6045	if (not r_cc_receive_dcache_req.read())
6046	{
6047	r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
6048	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
6049	break;
6050	}
6051	break;
6052	}
6053	////////////////////////////
6054	case CC_RECEIVE_INS_UPDT_HEADER:
6055	{
6056	// sample updt tab index in the HEADER, than skip to second flit
6057	uint64_t receive_data = p_dspin_m2p.data.read();
6058	// for ins INVAL, wait for icache to take the request and fifo to be
6059	// empty
6060	if (not r_cc_receive_icache_req.read())
6061	{
6062	r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
6063	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
6064	break;
6065	}
6066	// keep waiting for the correct cache to accept the request
6067	break;
6068	}
6069	///////////////////////////
6070	case CC_RECEIVE_DATA_UPDT_NLINE:
6071	{
6072	// sample nline and word index in the second flit
6073	uint64_t receive_data = p_dspin_m2p.data.read();
6074	// for data INVAL, wait for dcache to take the request and fifo to
6075	// be empty
6076	if (r_cc_receive_updt_fifo_be.empty() and
6077	p_dspin_m2p.write.read())
6078	{
6079	r_cc_receive_dcache_req = true;
6080	r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
6081	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
6082	r_cc_receive_dcache_type = CC_TYPE_UPDT;
6083	// get back to idle state
6084	r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
6085	break;
6086	}
6087	break;
6088	}
6089	////////////////////////////
6090	case CC_RECEIVE_INS_UPDT_NLINE:
6091	{
6092	// sample nline and word index in the second flit
6093	uint64_t receive_data = p_dspin_m2p.data.read();
6094	// for ins INVAL, wait for icache to take the request and fifo to be
6095	// empty
6096	if (r_cc_receive_updt_fifo_be.empty() and
6097	p_dspin_m2p.write.read())
6098	{
6099	r_cc_receive_icache_req = true;
6100	r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);
6101	r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);
6102	r_cc_receive_icache_type = CC_TYPE_UPDT;
6103	// get back to idle state
6104	r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
6105	break;
6106	}
6107	break;
6108	}
6109	//////////////////////////
6110	case CC_RECEIVE_DATA_UPDT_DATA:
6111	{
6112	// wait for the fifo
6113	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
6114	{
6115	uint64_t receive_data = p_dspin_m2p.data.read();
6116	bool receive_eop = p_dspin_m2p.eop.read();
6117	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
6118	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
6119	cc_receive_updt_fifo_eop = receive_eop;
6120	cc_receive_updt_fifo_put = true;
6121	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
6122	}
6123	break;
6124	}
6125	//////////////////////////
6126	case CC_RECEIVE_INS_UPDT_DATA:
6127	{
6128	// wait for the fifo
6129	if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read()))
6130	{
6131	uint64_t receive_data = p_dspin_m2p.data.read();
6132	bool receive_eop = p_dspin_m2p.eop.read();
6133	cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);
6134	cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);
6135	cc_receive_updt_fifo_eop = receive_eop;
6136	cc_receive_updt_fifo_put = true;
6137	if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
6138	}
6139	break;
6140	}
6141	//////////////////////////
6142	case CC_RECEIVE_TEST_HEADER:
6143	{
6144	if (not p_dspin_m2p.write.read()) break;
6145
6146	typedef DspinDhccpParam DDP;
6147	uint64_t header = p_dspin_m2p.data.read();
6148	uint64_t dest = DDP::dspin_get(header, DDP::TEST_M2P_DEST);
6149	assert((size_t)dest == m_cc_global_id);
6150
6151	r_cc_receive_fsm = CC_RECEIVE_TEST_SIGNATURE;
6152	break;
6153	}
6154	//////////////////////////
6155	case CC_RECEIVE_TEST_SIGNATURE:
6156	{
6157	if (not p_dspin_m2p.write.read()) break;
6158	assert(not r_cc_test_m2p_req.read());
6159	r_cc_test_m2p_req = true;
6160	r_cc_test_m2p_sign = p_dspin_m2p.data.read();
6161	r_cc_receive_fsm = CC_RECEIVE_IDLE;
6162	break;
6163	}
6164
6165	} // end switch CC_RECEIVE FSM
6166
6167	///////////////// DSPIN CLACK interface ///////////////
6168
6169	uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6170	DspinDhccpParam::CLACK_TYPE);
6171
6172	size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6173	DspinDhccpParam::CLACK_WAY);
6174
6175	size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6176	DspinDhccpParam::CLACK_SET);
6177
6178	size_t clack_test = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6179	DspinDhccpParam::TEST_CLACK_TEST);
6180
6181	bool dspin_clack_get = false;
6182	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
6183	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
6184
6185	if (r_dspin_clack_req.read())
6186	{
6187	// CLACK TEST first flit
6188	if (clack_test and not r_dspin_clack_test.read())
6189	{
6190	r_dspin_clack_test = true;
6191	dspin_clack_get = true;
6192	}
6193
6194	// CLACK TEST second flit
6195	else if (r_dspin_clack_test.read())
6196	{
6197	assert (not r_cc_test_clack_req.read());
6198	r_cc_test_clack_req = true;
6199	r_cc_test_clack_sign = r_dspin_clack_flit.read();
6200
6201	r_dspin_clack_test = false;
6202	dspin_clack_get = true;
6203	}
6204
6205	// CLACK DATA: Send request to DCACHE FSM
6206	else if (dcache_clack_request and not r_dcache_clack_req.read())
6207	{
6208	r_dcache_clack_req = true;
6209	r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1);
6210	r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1);
6211	dspin_clack_get = true;
6212	}
6213
6214	// CLACK INST: Send request to ICACHE FSM
6215	else if (icache_clack_request and not r_icache_clack_req.read())
6216	{
6217	r_icache_clack_req = true;
6218	r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
6219	r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1);
6220	dspin_clack_get = true;
6221	}
6222	}
6223	else
6224	{
6225	dspin_clack_get = true;
6226	}
6227
6228	if (dspin_clack_get)
6229	{
6230	r_dspin_clack_req = p_dspin_clack.write.read();
6231	r_dspin_clack_flit = p_dspin_clack.data.read();
6232	}
6233
6234	///////////////////////////////////////////////////////////////
6235	// CC_TEST FSM
6236	///////////////////////////////////////////////////////////////
6237
6238	switch(r_cc_test_fsm.read())
6239	{
6240	case CC_TEST_IDLE:
6241	if (not r_dcache_to_cc_test_req.read()) break;
6242	r_cc_test_fsm = CC_TEST_P2M_REQ;
6243	break;
6244
6245	case CC_TEST_P2M_REQ:
6246	assert (not r_cc_test_to_cc_send_req.read());
6247	r_cc_test_to_cc_send_req = true;
6248	r_cc_test_fsm = CC_TEST_P2M_WAIT;
6249	break;
6250
6251	case CC_TEST_P2M_WAIT:
6252	if (r_cc_test_to_cc_send_req.read())
6253	{
6254	if (not dcache_watchdog_timeout) break;
6255	r_dcache_to_cc_test_req = false;
6256	r_cc_test_to_cc_send_req = false;
6257	r_cc_test_fsm = CC_TEST_IDLE;
6258	break;
6259	}
6260	assert (not r_cc_test_clack_req.read() and not r_cc_test_m2p_req.read());
6261	r_cc_test_fsm = CC_TEST_ACK_WAIT;
6262	break;
6263
6264	case CC_TEST_ACK_WAIT:
6265	if (not r_cc_test_clack_req.read() or not r_cc_test_m2p_req.read())
6266	{
6267	if (not dcache_watchdog_timeout) break;
6268	}
6269
6270	// TODO: compare signatures from M2P and CLACK with the sent one
6271	r_dcache_to_cc_test_req = false;
6272	r_cc_test_clack_req = false;
6273	r_cc_test_m2p_req = false;
6274	r_cc_test_fsm = CC_TEST_IDLE;
6275	break;
6276	}
6277
6278	///////////////// Response FIFOs update //////////////////////
6279	r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get,
6280	vci_rsp_fifo_icache_put,
6281	vci_rsp_fifo_icache_data);
6282
6283	r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get,
6284	vci_rsp_fifo_dcache_put,
6285	vci_rsp_fifo_dcache_data);
6286
6287	///////////////// updt FIFO update //////////////////////
6288	r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get,
6289	cc_receive_updt_fifo_put,
6290	cc_receive_updt_fifo_be);
6291	r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get,
6292	cc_receive_updt_fifo_put,
6293	cc_receive_updt_fifo_data);
6294	r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get,
6295	cc_receive_updt_fifo_put,
6296	cc_receive_updt_fifo_eop);
6297
6298	} // end transition()
6299
6300	///////////////////////
6301	tmpl(void)::genMoore()
6302	///////////////////////
6303	{
6304
6305	// VCI initiator command on the direct network
6306	// it depends on the CMD FSM state
6307
6308	bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
6309	(r_vci_cmd_fsm.read() == CMD_DATA_SC);
6310
6311	p_vci.pktid = 0;
6312	p_vci.srcid = m_srcid;
6313	p_vci.cons = is_sc_or_cas;
6314	p_vci.contig = not is_sc_or_cas;
6315	p_vci.wrap = false;
6316	p_vci.clen = 0;
6317	p_vci.cfixed = false;
6318
6319	if (m_monitor_ok) {
6320	if (p_vci.cmdack.read() == true and p_vci.cmdval == true) {
6321	if (((p_vci.address.read()) >= m_monitor_base) and
6322	((p_vci.address.read()) < m_monitor_base + m_monitor_length)) {
6323	std::cout << "CC_VCACHE Monitor " << name() << std::hex
6324	<< " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
6325	<< " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
6326	<< " : address = " << p_vci.address.read()
6327	<< " / be = " << p_vci.be.read();
6328	if (p_vci.cmd.read() == vci_param::CMD_WRITE ) {
6329	std::cout << " / data = " << p_vci.wdata.read();
6330	}
6331	std::cout << std::dec << std::endl;
6332	}
6333	}
6334	}
6335
6336	switch (r_vci_cmd_fsm.read()) {
6337
6338	case CMD_IDLE:
6339	p_vci.cmdval = false;
6340	p_vci.address = 0;
6341	p_vci.wdata = 0;
6342	p_vci.be = 0;
6343	p_vci.trdid = 0;
6344	p_vci.pktid = 0;
6345	p_vci.plen = 0;
6346	p_vci.cmd = vci_param::CMD_NOP;
6347	p_vci.eop = false;
6348	break;
6349
6350	case CMD_INS_MISS:
6351	p_vci.cmdval = true;
6352	p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask;
6353	p_vci.wdata = 0;
6354	p_vci.be = 0xF;
6355	p_vci.trdid = 0;
6356	p_vci.pktid = TYPE_READ_INS_MISS;
6357	p_vci.plen = m_icache_words << 2;
6358	p_vci.cmd = vci_param::CMD_READ;
6359	p_vci.eop = true;
6360	break;
6361
6362	case CMD_INS_UNC:
6363	p_vci.cmdval = true;
6364	p_vci.address = r_icache_vci_paddr.read() & ~0x3;
6365	p_vci.wdata = 0;
6366	p_vci.be = 0xF;
6367	p_vci.trdid = 0;
6368	p_vci.pktid = TYPE_READ_INS_UNC;
6369	p_vci.plen = 4;
6370	p_vci.cmd = vci_param::CMD_READ;
6371	p_vci.eop = true;
6372	break;
6373
6374	case CMD_DATA_MISS:
6375	p_vci.cmdval = true;
6376	p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask;
6377	p_vci.wdata = 0;
6378	p_vci.be = 0xF;
6379	p_vci.trdid = r_dcache_vci_wdt_trdid.read();
6380	p_vci.pktid = TYPE_READ_DATA_MISS;
6381	p_vci.plen = m_dcache_words << 2;
6382	p_vci.cmd = vci_param::CMD_READ;
6383	p_vci.eop = true;
6384	break;
6385
6386	case CMD_DATA_UNC_READ:
6387	p_vci.cmdval = true;
6388	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6389	p_vci.wdata = 0;
6390	p_vci.be = r_dcache_vci_unc_be.read();
6391	p_vci.trdid = r_dcache_vci_wdt_trdid.read();
6392	p_vci.pktid = TYPE_DATA_UNC;
6393	p_vci.plen = 4;
6394	p_vci.cmd = vci_param::CMD_READ;
6395	p_vci.eop = true;
6396	break;
6397
6398	case CMD_DATA_UNC_WRITE:
6399	p_vci.cmdval = true;
6400	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6401	p_vci.wdata = r_dcache_vci_wdata.read();
6402	p_vci.be = r_dcache_vci_unc_be.read();
6403	p_vci.trdid = r_dcache_vci_wdt_trdid.read();
6404	p_vci.pktid = TYPE_DATA_UNC;
6405	p_vci.plen = 4;
6406	p_vci.cmd = vci_param::CMD_WRITE;
6407	p_vci.eop = true;
6408	break;
6409
6410	case CMD_DATA_WRITE:
6411	p_vci.cmdval = true;
6412	p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3;
6413	p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read());
6414	p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read());
6415	p_vci.trdid = r_wbuf.getIndex();
6416	p_vci.pktid = TYPE_WRITE;
6417	p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2;
6418	p_vci.cmd = vci_param::CMD_WRITE;
6419	p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read());
6420	break;
6421
6422	case CMD_DATA_LL:
6423	p_vci.cmdval = true;
6424	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6425	p_vci.wdata = 0;
6426	p_vci.be = 0xF;
6427	p_vci.trdid = 0;
6428	p_vci.pktid = TYPE_LL;
6429	p_vci.plen = 8;
6430	p_vci.cmd = vci_param::CMD_LOCKED_READ;
6431	p_vci.eop = true;
6432	break;
6433
6434	case CMD_DATA_SC:
6435	p_vci.cmdval = true;
6436	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6437	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
6438	else p_vci.wdata = r_dcache_vci_sc_data.read();
6439	p_vci.be = 0xF;
6440	p_vci.trdid = 0;
6441	p_vci.pktid = TYPE_SC;
6442	p_vci.plen = 8;
6443	p_vci.cmd = vci_param::CMD_NOP;
6444	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6445	break;
6446
6447	case CMD_DATA_CAS:
6448	p_vci.cmdval = true;
6449	p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
6450	if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read();
6451	else p_vci.wdata = r_dcache_vci_cas_new.read();
6452	p_vci.be = 0xF;
6453	p_vci.trdid = 0;
6454	p_vci.pktid = TYPE_CAS;
6455	p_vci.plen = 8;
6456	p_vci.cmd = vci_param::CMD_NOP;
6457	p_vci.eop = (r_vci_cmd_cpt.read() == 1);
6458	break;
6459	} // end switch r_vci_cmd_fsm
6460
6461	// VCI initiator response on the direct network
6462	// it depends on the VCI_RSP FSM
6463
6464	switch (r_vci_rsp_fsm.read())
6465	{
6466	case RSP_DATA_WRITE : p_vci.rspack = true; break;
6467	case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6468	case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break;
6469	case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6470	case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6471	case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break;
6472	case RSP_IDLE : p_vci.rspack = false; break;
6473	} // end switch r_vci_rsp_fsm
6474
6475
6476	// Send coherence packets on DSPIN P2M
6477	// it depends on the CC_SEND FSM
6478
6479	uint64_t dspin_send_data = 0;
6480	switch (r_cc_send_fsm.read())
6481	{
6482	//////////////////
6483	case CC_SEND_IDLE:
6484	{
6485	p_dspin_p2m.write = false;
6486	break;
6487	}
6488	///////////////////////
6489	case CC_SEND_CLEANUP_1:
6490	{
6491	// initialize dspin send data
6492	DspinDhccpParam::dspin_set(dspin_send_data,
6493	m_cc_global_id,
6494	DspinDhccpParam::CLEANUP_SRCID);
6495	DspinDhccpParam::dspin_set(dspin_send_data,
6496	0,
6497	DspinDhccpParam::P2M_BC);
6498
6499	if (r_cc_send_last_client.read() == 0) // dcache active request
6500	{
6501	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6502	>> (m_nline_width - m_x_width - m_y_width)
6503	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6504
6505	DspinDhccpParam::dspin_set(dspin_send_data,
6506	dest,
6507	DspinDhccpParam::CLEANUP_DEST);
6508
6509	DspinDhccpParam::dspin_set(dspin_send_data,
6510	(r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
6511	DspinDhccpParam::CLEANUP_NLINE_MSB);
6512
6513	DspinDhccpParam::dspin_set(dspin_send_data,
6514	r_dcache_cc_send_way.read(),
6515	DspinDhccpParam::CLEANUP_WAY_INDEX);
6516
6517	DspinDhccpParam::dspin_set(dspin_send_data,
6518	DspinDhccpParam::TYPE_CLEANUP_DATA,
6519	DspinDhccpParam::P2M_TYPE);
6520	}
6521	else // icache active request
6522	{
6523	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6524	>> (m_nline_width - m_x_width - m_y_width)
6525	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6526
6527	DspinDhccpParam::dspin_set(dspin_send_data,
6528	dest,
6529	DspinDhccpParam::CLEANUP_DEST);
6530
6531	DspinDhccpParam::dspin_set(dspin_send_data,
6532	(r_icache_cc_send_nline.read() & 0x300000000ULL) >> 32,
6533	DspinDhccpParam::CLEANUP_NLINE_MSB);
6534
6535	DspinDhccpParam::dspin_set(dspin_send_data,
6536	r_icache_cc_send_way.read(),
6537	DspinDhccpParam::CLEANUP_WAY_INDEX);
6538
6539	DspinDhccpParam::dspin_set(dspin_send_data,
6540	DspinDhccpParam::TYPE_CLEANUP_INST,
6541	DspinDhccpParam::P2M_TYPE);
6542	}
6543	// send flit
6544	p_dspin_p2m.data = dspin_send_data;
6545	p_dspin_p2m.write = true;
6546	p_dspin_p2m.eop = false;
6547	break;
6548	}
6549	///////////////////////
6550	case CC_SEND_CLEANUP_2:
6551	{
6552	// initialize dspin send data
6553
6554	if (r_cc_send_last_client.read() == 0) // dcache active request
6555	{
6556	DspinDhccpParam::dspin_set(dspin_send_data,
6557	r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
6558	DspinDhccpParam::CLEANUP_NLINE_LSB);
6559	}
6560	else // icache active request
6561	{
6562	DspinDhccpParam::dspin_set(dspin_send_data,
6563	r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
6564	DspinDhccpParam::CLEANUP_NLINE_LSB);
6565	}
6566	// send flit
6567	p_dspin_p2m.data = dspin_send_data;
6568	p_dspin_p2m.write = true;
6569	p_dspin_p2m.eop = true;
6570	break;
6571	}
6572	///////////////////////
6573	case CC_SEND_MULTI_ACK:
6574	{
6575	// initialize dspin send data
6576	DspinDhccpParam::dspin_set(dspin_send_data,
6577	0,
6578	DspinDhccpParam::P2M_BC);
6579	DspinDhccpParam::dspin_set(dspin_send_data,
6580	DspinDhccpParam::TYPE_MULTI_ACK,
6581	DspinDhccpParam::P2M_TYPE);
6582
6583	if (r_cc_send_last_client.read() == 0) // dcache active request
6584	{
6585	uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
6586	>> (m_nline_width - m_x_width - m_y_width)
6587	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6588
6589	DspinDhccpParam::dspin_set(dspin_send_data,
6590	dest,
6591	DspinDhccpParam::MULTI_ACK_DEST);
6592
6593	DspinDhccpParam::dspin_set(dspin_send_data,
6594	r_dcache_cc_send_updt_tab_idx.read(),
6595	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6596	}
6597	else // icache active request
6598	{
6599	uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
6600	>> (m_nline_width - m_x_width - m_y_width)
6601	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6602
6603
6604	DspinDhccpParam::dspin_set(dspin_send_data,
6605	dest,
6606	DspinDhccpParam::MULTI_ACK_DEST);
6607
6608	DspinDhccpParam::dspin_set(dspin_send_data,
6609	r_icache_cc_send_updt_tab_idx.read(),
6610	DspinDhccpParam::MULTI_ACK_UPDT_INDEX);
6611	}
6612	// send flit
6613	p_dspin_p2m.data = dspin_send_data;
6614	p_dspin_p2m.write = true;
6615	p_dspin_p2m.eop = true;
6616
6617	break;
6618	}
6619	///////////////////////
6620	case CC_SEND_TEST_HEADER:
6621	{
6622	typedef DspinDhccpParam DDP;
6623	uint64_t flit = 0;
6624
6625	uint64_t dest = (uint64_t)r_dcache_to_cc_test_dest.read()
6626	<< (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);
6627
6628	DDP::dspin_set(flit, DDP::TYPE_TEST, DDP::P2M_TYPE);
6629	DDP::dspin_set(flit, dest, DDP::TEST_P2M_DEST);
6630	DDP::dspin_set(flit, m_cc_global_id, DDP::TEST_P2M_SRCID);
6631	DDP::dspin_set(flit, 1ULL, DDP::TEST_P2M_TEST);
6632
6633	p_dspin_p2m.data = flit;
6634	p_dspin_p2m.write = true;
6635	p_dspin_p2m.eop = false;
6636	break;
6637	}
6638	///////////////////////
6639	case CC_SEND_TEST_SIGNATURE:
6640	{
6641	typedef DspinDhccpParam DDP;
6642	uint64_t flit = 0;
6643
6644	DDP::dspin_set(flit, r_mmu_word_lo.read(), DDP::TEST_P2M_SIGNATURE);
6645
6646	p_dspin_p2m.data = flit;
6647	p_dspin_p2m.write = true;
6648	p_dspin_p2m.eop = true;
6649	break;
6650	}
6651
6652	} // end switch CC_SEND FSM
6653
6654	// Receive coherence packets
6655	// It depends on the CC_RECEIVE FSM
6656	switch (r_cc_receive_fsm.read())
6657	{
6658	/////////////////////
6659	case CC_RECEIVE_IDLE:
6660	{
6661	p_dspin_m2p.read = false;
6662	break;
6663	}
6664	///////////////////////////////
6665	case CC_RECEIVE_BRDCAST_HEADER:
6666	{
6667	p_dspin_m2p.read = true;
6668	break;
6669	}
6670	//////////////////////////////
6671	case CC_RECEIVE_BRDCAST_NLINE:
6672	{
6673	if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()))
6674	p_dspin_m2p.read = true;
6675	else
6676	p_dspin_m2p.read = false;
6677	break;
6678	}
6679	/////////////////////////////
6680	case CC_RECEIVE_DATA_INVAL_HEADER:
6681	case CC_RECEIVE_INS_INVAL_HEADER:
6682	{
6683	p_dspin_m2p.read = true;
6684	break;
6685	}
6686	////////////////////////////
6687	case CC_RECEIVE_DATA_INVAL_NLINE:
6688	{
6689	p_dspin_m2p.read = not r_cc_receive_dcache_req.read();
6690	break;
6691	}
6692	case CC_RECEIVE_INS_INVAL_NLINE:
6693	{
6694	p_dspin_m2p.read = not r_cc_receive_icache_req.read();
6695	break;
6696	}
6697	///////////////////////////
6698	case CC_RECEIVE_DATA_UPDT_HEADER:
6699	{
6700	if (not r_cc_receive_dcache_req.read())
6701	p_dspin_m2p.read = true;
6702	else
6703	p_dspin_m2p.read = false;
6704	break;
6705	}
6706	////////////////////////////
6707	case CC_RECEIVE_INS_UPDT_HEADER:
6708	{
6709	if (not r_cc_receive_icache_req.read())
6710	p_dspin_m2p.read = true;
6711	else
6712	p_dspin_m2p.read = false;
6713	break;
6714	}
6715	///////////////////////////
6716	case CC_RECEIVE_DATA_UPDT_NLINE:
6717	case CC_RECEIVE_INS_UPDT_NLINE:
6718	{
6719	if (r_cc_receive_updt_fifo_be.empty())
6720	p_dspin_m2p.read = true;
6721	else
6722	p_dspin_m2p.read = false;
6723	break;
6724	}
6725	///////////////////////////
6726	case CC_RECEIVE_DATA_UPDT_DATA:
6727	case CC_RECEIVE_INS_UPDT_DATA:
6728	{
6729	if (r_cc_receive_updt_fifo_be.wok())
6730	p_dspin_m2p.read = true;
6731	else
6732	p_dspin_m2p.read = false;
6733	break;
6734	}
6735	///////////////////////////////
6736	case CC_RECEIVE_TEST_HEADER:
6737	{
6738	p_dspin_m2p.read = true;
6739	break;
6740	}
6741	///////////////////////////////
6742	case CC_RECEIVE_TEST_SIGNATURE:
6743	{
6744	p_dspin_m2p.read = true;
6745	break;
6746	}
6747	} // end switch CC_RECEIVE FSM
6748
6749
6750	int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6751	DspinDhccpParam::CLACK_TYPE);
6752
6753	size_t clack_test = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(),
6754	DspinDhccpParam::TEST_CLACK_TEST);
6755
6756	bool dspin_clack_get = false;
6757	bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA);
6758	bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST);
6759
6760	if (r_dspin_clack_req.read())
6761	{
6762	// CLACK TEST
6763	if (clack_test or r_dspin_clack_test.read())
6764	{
6765	dspin_clack_get = true;
6766	}
6767
6768	// CLACK DATA: wait if pending request to DCACHE FSM
6769	else if (dcache_clack_request and not r_dcache_clack_req.read())
6770	{
6771	dspin_clack_get = true;
6772	}
6773
6774	// CLACK INST: wait if pending request to ICACHE FSM
6775	else if (icache_clack_request and not r_icache_clack_req.read())
6776	{
6777	dspin_clack_get = true;
6778	}
6779	}
6780	else
6781	{
6782	dspin_clack_get = true;
6783	}
6784
6785	p_dspin_clack.read = dspin_clack_get;
6786	} // end genMoore
6787
6788	tmpl(void)::start_monitor(paddr_t base, paddr_t length)
6789	// This version of monitor print both Read and Write request
6790	{
6791	m_monitor_ok = true;
6792	m_monitor_base = base;
6793	m_monitor_length = length;
6794	}
6795
6796	tmpl(void)::stop_monitor()
6797	{
6798	m_monitor_ok = false;
6799	}
6800
6801	}}
6802
6803	// Local Variables:
6804	// tab-width: 4
6805	// c-basic-offset: 4
6806	// c-file-offsets:((innamespace . 0)(inline-open . 0))
6807	// indent-tabs-mode: nil
6808	// End:
6809
6810	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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