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source: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp @ 884

Last change on this file since 884 was 884, checked in by cfuguet, 9 years ago

reconf: bind a config port of the xicu to the internal dspin_routers

This config port is bound to the blackhole_pos port of the dspin_router. This way, the software can configure the dspin_router by writing in the first configuration register of the xicu.

The same xicu's config port is connected to the 5 local routers of the internal interconnect. Therefore, the 5 routers share the same configuration.

File size: 33.7 KB

Line
1	//////////////////////////////////////////////////////////////////////////////
2	// File: tsar_iob_cluster.cpp
3	// Author: Alain Greiner
4	// Copyright: UPMC/LIP6
5	// Date : april 2013
6	// This program is released under the GNU public license
7	//////////////////////////////////////////////////////////////////////////////
8	// Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components.
9	// These two clusters contain 6 extra components:
10	// - 1 vci_io_bridge (connected to the 3 networks.
11	// - 3 vci_dspin_wrapper for the IOB.
12	// - 2 dspin_local_crossbar for commands and responses.
13	//////////////////////////////////////////////////////////////////////////////
14
15	#include "../include/tsar_iob_cluster.h"
16
17	#define tmpl(x) \
18	template<typename vci_param_int , typename vci_param_ext,\
19	size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\
20	size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\
21	x TsarIobCluster<\
22	vci_param_int , vci_param_ext,\
23	dspin_int_cmd_width, dspin_int_rsp_width,\
24	dspin_ram_cmd_width, dspin_ram_rsp_width>
25
26	namespace soclib { namespace caba {
27
28	//////////////////////////////////////////////////////////////////////////
29	// Constructor
30	//////////////////////////////////////////////////////////////////////////
31	tmpl(/**/)::TsarIobCluster(
32	sc_module_name insname,
33	size_t nb_procs,
34	size_t nb_dmas,
35	size_t x_id,
36	size_t y_id,
37	size_t x_size,
38	size_t y_size,
39
40	size_t p_width,
41
42	const soclib::common::MappingTable &mt_int,
43	const soclib::common::MappingTable &mt_ram,
44	const soclib::common::MappingTable &mt_iox,
45
46	size_t x_width,
47	size_t y_width,
48	size_t l_width,
49
50	size_t int_memc_tgt_id, // local index
51	size_t int_xicu_tgt_id, // local index
52	size_t int_mdma_tgt_id, // local index
53	size_t int_brom_tgt_id, // local index
54	size_t int_iobx_tgt_id, // local index
55
56	size_t int_proc_ini_id, // local index
57	size_t int_mdma_ini_id, // local index
58	size_t int_iobx_ini_id, // local index
59
60	size_t ram_xram_tgt_id, // local index
61	size_t ram_memc_ini_id, // local index
62	size_t ram_iobx_ini_id, // local index
63
64	bool is_io, // is IO cluster (IOB)?
65	size_t iox_iobx_tgt_id, // local_index
66	size_t iox_iobx_ini_id, // local index
67
68	size_t memc_ways,
69	size_t memc_sets,
70	size_t l1_i_ways,
71	size_t l1_i_sets,
72	size_t l1_d_ways,
73	size_t l1_d_sets,
74	size_t xram_latency,
75	size_t xcu_nb_inputs,
76
77	bool distboot,
78
79	const Loader &loader,
80
81	uint32_t frozen_cycles,
82	uint32_t debug_start_cycle,
83	bool memc_debug_ok,
84	bool proc_debug_ok,
85	bool iob_debug_ok ) :
86
87	// constructor initialization list
88
89	soclib::caba::BaseModule(insname),
90	p_clk("clk"),
91	p_resetn("resetn")
92	{
93
94	assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates");
95
96	size_t cluster_id = (x_id << x_width) \| y_id;
97
98	// Vectors of DSPIN ports for inter-cluster communications
99	p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
100	p_dspin_int_cmd_out = alloc_elems<DspinOutput<dspin_int_cmd_width> >("p_int_cmd_out", 4, 3);
101	p_dspin_int_rsp_in = alloc_elems<DspinInput<dspin_int_rsp_width> >("p_int_rsp_in", 4, 2);
102	p_dspin_int_rsp_out = alloc_elems<DspinOutput<dspin_int_rsp_width> >("p_int_rsp_out", 4, 2);
103
104	p_dspin_ram_cmd_in = alloc_elems<DspinInput<dspin_ram_cmd_width> >("p_ext_cmd_in", 4);
105	p_dspin_ram_cmd_out = alloc_elems<DspinOutput<dspin_ram_cmd_width> >("p_ext_cmd_out", 4);
106	p_dspin_ram_rsp_in = alloc_elems<DspinInput<dspin_ram_rsp_width> >("p_ext_rsp_in", 4);
107	p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
108
109	// VCI ports from IOB to IOX network (only in IO clusters)
110	if (is_io)
111	{
112	p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
113	p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>;
114	}
115
116	/////////////////////////////////////////////////////////////////////////////
117	// Hardware components
118	/////////////////////////////////////////////////////////////////////////////
119
120	//////////// PROCS
121	for (size_t p = 0; p < nb_procs; p++)
122	{
123	std::ostringstream s_proc;
124	s_proc << "proc_" << x_id << "_" << y_id << "_" << p;
125	proc[p] = new VciCcVCacheWrapper<vci_param_int,
126	dspin_int_cmd_width,
127	dspin_int_rsp_width,
128	GdbServer<Mips32ElIss> >(
129	s_proc.str().c_str(),
130	(cluster_id << p_width) \| p, // GLOBAL PROC_ID
131	mt_int, // Mapping Table INT network
132	IntTab(cluster_id,p), // SRCID
133	(cluster_id << l_width) \| p, // CC_GLOBAL_ID
134	8, // ITLB ways
135	8, // ITLB sets
136	8, // DTLB ways
137	8, // DTLB sets
138	l1_i_ways, l1_i_sets, 16, // ICACHE size
139	l1_d_ways, l1_d_sets, 16, // DCACHE size
140	4, // WBUF nlines
141	4, // WBUF nwords
142	x_width, // number of bits for x coordinate
143	y_width, // number of bits for y coordinate
144	frozen_cycles, // max frozen cycles
145	debug_start_cycle,
146	proc_debug_ok);
147
148	// initialize physical address extension with cluster ID when using
149	// distributed boot
150	if (distboot)
151	{
152	proc[p]->set_dcache_paddr_ext_reset(cluster_id);
153	proc[p]->set_icache_paddr_ext_reset(cluster_id);
154	}
155	}
156
157	/////////// MEMC
158	std::ostringstream s_memc;
159	s_memc << "memc_" << x_id << "_" << y_id;
160	memc = new VciMemCache<vci_param_int,
161	vci_param_ext,
162	dspin_int_rsp_width,
163	dspin_int_cmd_width>(
164	s_memc.str().c_str(),
165	mt_int, // Mapping Table INT network
166	mt_ram, // Mapping Table RAM network
167	IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
168	IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
169	x_width, // number of bits for x coordinate
170	y_width, // number of bits for y coordinate
171	memc_ways, memc_sets, 16, // CACHE SIZE
172	3, // MAX NUMBER OF COPIES
173	4096, // HEAP SIZE
174	8, // TRANSACTION TABLE DEPTH
175	8, // UPDATE TABLE DEPTH
176	8, // INVALIDATE TABLE DEPTH
177	debug_start_cycle,
178	memc_debug_ok );
179
180	std::ostringstream s_wi_memc;
181	s_wi_memc << "memc_wi_" << x_id << "_" << y_id;
182	memc_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
183	dspin_ram_cmd_width,
184	dspin_ram_rsp_width>(
185	s_wi_memc.str().c_str(),
186	x_width + y_width + l_width);
187
188	/////////// XICU
189	std::ostringstream s_xicu;
190	s_xicu << "xicu_" << x_id << "_" << y_id;
191	xicu = new VciXicu<vci_param_int>(
192	s_xicu.str().c_str(),
193	mt_int, // mapping table INT network
194	IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
195	xcu_nb_inputs, // number of timer IRQs
196	xcu_nb_inputs, // number of hard IRQs
197	xcu_nb_inputs, // number of soft IRQs
198	16, // number of output IRQs
199	1); // number of config regs
200
201	//////////// MDMA
202	std::ostringstream s_mdma;
203	s_mdma << "mdma_" << x_id << "_" << y_id;
204	mdma = new VciMultiDma<vci_param_int>(
205	s_mdma.str().c_str(),
206	mt_int,
207	IntTab(cluster_id, nb_procs), // SRCID
208	IntTab(cluster_id, int_mdma_tgt_id), // TGTID
209	64, // burst size
210	nb_dmas); // number of IRQs
211
212	/////////// DISTRIBUTED BOOT ROM
213	std::ostringstream s_brom;
214	s_brom << "brom_" << x_id << "_" << y_id;
215	brom = new VciSimpleRom<vci_param_int>(
216	s_brom.str().c_str(),
217	IntTab(cluster_id, int_brom_tgt_id),
218	mt_int,
219	loader,
220	x_width + y_width); // msb drop bits
221
222	/////////// Direct LOCAL_XBAR(S)
223	size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
224	size_t nb_direct_targets = is_io ? 5 : 4;
225
226	std::ostringstream s_int_xbar_d;
227	s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id;
228	int_xbar_d = new VciLocalCrossbar<vci_param_int>(
229	s_int_xbar_d.str().c_str(),
230	mt_int, // mapping table
231	cluster_id, // cluster id
232	nb_direct_initiators, // number of local initiators
233	nb_direct_targets, // number of local targets
234	0 ); // default target
235
236	std::ostringstream s_int_dspin_ini_wrapper_gate_d;
237	s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_"
238	<< x_id << "_" << y_id;
239	int_wi_gate_d = new VciDspinInitiatorWrapper<vci_param_int,
240	dspin_int_cmd_width,
241	dspin_int_rsp_width>(
242	s_int_dspin_ini_wrapper_gate_d.str().c_str(),
243	x_width + y_width + l_width);
244
245	std::ostringstream s_int_dspin_tgt_wrapper_gate_d;
246	s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_"
247	<< x_id << "_" << y_id;
248	int_wt_gate_d = new VciDspinTargetWrapper<vci_param_int,
249	dspin_int_cmd_width,
250	dspin_int_rsp_width>(
251	s_int_dspin_tgt_wrapper_gate_d.str().c_str(),
252	x_width + y_width + l_width);
253
254	//////////// Coherence LOCAL_XBAR(S)
255	std::ostringstream s_int_xbar_m2p_c;
256	s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id;
257	int_xbar_m2p_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
258	s_int_xbar_m2p_c.str().c_str(),
259	mt_int, // mapping table
260	x_id, y_id, // cluster coordinates
261	x_width, y_width, l_width, // several dests
262	1, // number of local sources
263	nb_procs, // number of local dests
264	2, 2, // fifo depths
265	true, // pseudo CMD
266	false, // no routing table
267	true ); // broacast
268
269	std::ostringstream s_int_xbar_p2m_c;
270	s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id;
271	int_xbar_p2m_c = new DspinLocalCrossbar<dspin_int_rsp_width>(
272	s_int_xbar_p2m_c.str().c_str(),
273	mt_int, // mapping table
274	x_id, y_id, // cluster coordinates
275	x_width, y_width, 0, // only one dest
276	nb_procs, // number of local sources
277	1, // number of local dests
278	2, 2, // fifo depths
279	false, // pseudo RSP
280	false, // no routing table
281	false ); // no broacast
282
283	std::ostringstream s_int_xbar_clack_c;
284	s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id;
285	int_xbar_clack_c = new DspinLocalCrossbar<dspin_int_cmd_width>(
286	s_int_xbar_clack_c.str().c_str(),
287	mt_int, // mapping table
288	x_id, y_id, // cluster coordinates
289	x_width, y_width, l_width,
290	1, // number of local sources
291	nb_procs, // number of local targets
292	1, 1, // fifo depths
293	true, // CMD
294	false, // no routing table
295	false); // broadcast
296
297	////////////// INT ROUTER(S)
298	int_router_cmd = new DspinRouter<dspin_int_cmd_width>*[3];
299	for (int k = 0; k < 3; k++)
300	{
301	std::ostringstream s_int_router_cmd;
302	s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id << "_" << k;
303	int_router_cmd[k] = new DspinRouter<dspin_int_cmd_width>(
304	s_int_router_cmd.str().c_str(),
305	x_id, y_id,
306	x_width, y_width,
307	4, 4,
308	(k == 1),
309	true); // use config interface
310	}
311
312	int_router_rsp = new DspinRouter<dspin_int_rsp_width>*[2];
313	for (int k = 0; k < 2; k++)
314	{
315	std::ostringstream s_int_router_rsp;
316	s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id << "_" << k;
317	int_router_rsp[k] = new DspinRouter<dspin_int_rsp_width>(
318	s_int_router_rsp.str().c_str(),
319	x_id, y_id,
320	x_width, y_width,
321	4, 4,
322	false,
323	true); // use config interface
324	}
325
326	////////////// XRAM
327	std::ostringstream s_xram;
328	s_xram << "xram_" << x_id << "_" << y_id;
329	xram = new VciSimpleRam<vci_param_ext>(
330	s_xram.str().c_str(),
331	IntTab(cluster_id, ram_xram_tgt_id),
332	mt_ram,
333	loader,
334	xram_latency);
335
336	std::ostringstream s_wt_xram;
337	s_wt_xram << "xram_wt_" << x_id << "_" << y_id;
338	xram_ram_wt = new VciDspinTargetWrapper<vci_param_ext,
339	dspin_ram_cmd_width,
340	dspin_ram_rsp_width>(
341	s_wt_xram.str().c_str(),
342	x_width + y_width + l_width);
343
344	///////////// RAM ROUTER(S)
345	std::ostringstream s_ram_router_cmd;
346	s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
347	ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
348	s_ram_router_cmd.str().c_str(),
349	x_id, y_id, // router coordinates in mesh
350	x_width, // x field width in first flit
351	y_width, // y field width in first flit
352	4, 4); // input & output fifo depths
353
354	std::ostringstream s_ram_router_rsp;
355	s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
356	ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
357	s_ram_router_rsp.str().c_str(),
358	x_id, y_id, // coordinates in mesh
359	x_width, // x field width in first flit
360	y_width, // y field width in first flit
361	4, 4); // input & output fifo depths
362
363
364	////////////////////// I/O CLUSTER ONLY ///////////////////////
365	if ( is_io )
366	{
367	/////////// IO_BRIDGE
368	std::ostringstream s_iob;
369	s_iob << "iob_" << x_id << "_" << y_id;
370	iob = new VciIoBridge<vci_param_int,
371	vci_param_ext>(
372	s_iob.str().c_str(),
373	mt_ram, // EXT network maptab
374	mt_int, // INT network maptab
375	mt_iox, // IOX network maptab
376	IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
377	IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
378	IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID
379	IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID
380	16, // cache line words
381	8, // IOTLB ways
382	8, // IOTLB sets
383	debug_start_cycle,
384	iob_debug_ok );
385
386	std::ostringstream s_iob_ram_wi;
387	s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id;
388	iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext,
389	dspin_ram_cmd_width,
390	dspin_ram_rsp_width>(
391	s_iob_ram_wi.str().c_str(),
392	vci_param_int::S);
393
394	std::ostringstream s_ram_xbar_cmd;
395	s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
396	ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
397	s_ram_xbar_cmd.str().c_str(), // name
398	mt_ram, // mapping table
399	x_id, y_id, // x, y
400	x_width, y_width, l_width, // x_width, y_width, l_width
401	2, 0, // local inputs, local outputs
402	2, 2, // in fifo, out fifo depths
403	true, // is cmd ?
404	false, // use routing table ?
405	false); // support broadcast ?
406
407	std::ostringstream s_ram_xbar_rsp;
408	s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
409	ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
410	s_ram_xbar_rsp.str().c_str(), // name
411	mt_ram, // mapping table
412	x_id, y_id, // x, y
413	x_width, y_width, l_width, // x_width, y_width, l_width
414	0, 2, // local inputs, local outputs
415	2, 2, // in fifo, out fifo depths
416	false, // is cmd ?
417	true, // use routing table ?
418	false); // support broadcast ?
419	} // end if IO
420
421	////////////////////////////////////
422	// Connections are defined here
423	////////////////////////////////////
424
425	// on coherence network : local srcid[proc] in [0...nb_procs-1]
426	// : local srcid[memc] = nb_procs
427
428	//////////////////////// internal CMD & RSP routers
429	for(int k = 0; k < 3; k++)
430	{
431	int_router_cmd[k]->p_clk (this->p_clk);
432	int_router_cmd[k]->p_resetn (this->p_resetn);
433	(*int_router_cmd[k]->p_blackhole_pos) (signal_cfg_router);
434	for (int i = 0; i < 4; i++)
435	{
436	int_router_cmd[k]->p_out[i] (this->p_dspin_int_cmd_out[i][k]);
437	int_router_cmd[k]->p_in[i] (this->p_dspin_int_cmd_in[i][k]);
438	}
439	}
440
441	for(int k = 0; k < 2; k++)
442	{
443	int_router_rsp[k]->p_clk (this->p_clk);
444	int_router_rsp[k]->p_resetn (this->p_resetn);
445	(*int_router_rsp[k]->p_blackhole_pos) (signal_cfg_router);
446	for (int i = 0; i < 4; i++)
447	{
448	int_router_rsp[k]->p_out[i] (this->p_dspin_int_rsp_out[i][k]);
449	int_router_rsp[k]->p_in[i] (this->p_dspin_int_rsp_in[i][k]);
450	}
451	}
452
453	// local ports
454	int_router_cmd[0]->p_out[4] (signal_int_dspin_cmd_g2l_d);
455	int_router_cmd[1]->p_out[4] (signal_int_dspin_m2p_g2l_c);
456	int_router_cmd[2]->p_out[4] (signal_int_dspin_clack_g2l_c);
457	int_router_cmd[0]->p_in[4] (signal_int_dspin_cmd_l2g_d);
458	int_router_cmd[1]->p_in[4] (signal_int_dspin_m2p_l2g_c);
459	int_router_cmd[2]->p_in[4] (signal_int_dspin_clack_l2g_c);
460
461	int_router_rsp[0]->p_out[4] (signal_int_dspin_rsp_g2l_d);
462	int_router_rsp[1]->p_out[4] (signal_int_dspin_p2m_g2l_c);
463	int_router_rsp[0]->p_in[4] (signal_int_dspin_rsp_l2g_d);
464	int_router_rsp[1]->p_in[4] (signal_int_dspin_p2m_l2g_c);
465
466	///////////////////// CMD DSPIN local crossbar direct
467	int_xbar_d->p_clk (this->p_clk);
468	int_xbar_d->p_resetn (this->p_resetn);
469	int_xbar_d->p_initiator_to_up (signal_int_vci_l2g);
470	int_xbar_d->p_target_to_up (signal_int_vci_g2l);
471
472	int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc);
473	int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu);
474	int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma);
475	int_xbar_d->p_to_target[int_brom_tgt_id] (signal_int_vci_tgt_brom);
476	int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma);
477	for (size_t p = 0; p < nb_procs; p++)
478	int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
479
480	if ( is_io )
481	{
482	int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx);
483	int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx);
484	}
485
486	int_wi_gate_d->p_clk (this->p_clk);
487	int_wi_gate_d->p_resetn (this->p_resetn);
488	int_wi_gate_d->p_vci (signal_int_vci_l2g);
489	int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d);
490	int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d);
491
492	int_wt_gate_d->p_clk (this->p_clk);
493	int_wt_gate_d->p_resetn (this->p_resetn);
494	int_wt_gate_d->p_vci (signal_int_vci_g2l);
495	int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d);
496	int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d);
497
498	////////////////////// M2P DSPIN local crossbar coherence
499	int_xbar_m2p_c->p_clk (this->p_clk);
500	int_xbar_m2p_c->p_resetn (this->p_resetn);
501	int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c);
502	int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c);
503	int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc);
504	for (size_t p = 0; p < nb_procs; p++)
505	int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]);
506
507	////////////////////////// P2M DSPIN local crossbar coherence
508	int_xbar_p2m_c->p_clk (this->p_clk);
509	int_xbar_p2m_c->p_resetn (this->p_resetn);
510	int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c);
511	int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c);
512	int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc);
513	for (size_t p = 0; p < nb_procs; p++)
514	int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]);
515
516	////////////////////// CLACK DSPIN local crossbar coherence
517	int_xbar_clack_c->p_clk (this->p_clk);
518	int_xbar_clack_c->p_resetn (this->p_resetn);
519	int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c);
520	int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c);
521	int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc);
522	for (size_t p = 0; p < nb_procs; p++)
523	int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]);
524
525	//////////////////////////////////// Processors
526	for (size_t p = 0; p < nb_procs; p++)
527	{
528	proc[p]->p_clk (this->p_clk);
529	proc[p]->p_resetn (this->p_resetn);
530	proc[p]->p_vci (signal_int_vci_ini_proc[p]);
531	proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]);
532	proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]);
533	proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]);
534
535	for ( size_t j = 0 ; j < 6 ; j++)
536	{
537	if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]);
538	else proc[p]->p_irq[j] (signal_false);
539	}
540	}
541
542	///////////////////////////////////// XICU
543	xicu->p_clk (this->p_clk);
544	xicu->p_resetn (this->p_resetn);
545	xicu->p_vci (signal_int_vci_tgt_xicu);
546	for ( size_t i=0 ; i < 16 ; i++)
547	{
548	xicu->p_irq[i] (signal_proc_it[i]);
549	}
550	for ( size_t i=0 ; i < xcu_nb_inputs ; i++)
551	{
552	if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc);
553	else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]);
554	else xicu->p_hwi[i] (signal_false);
555	}
556	xicu->p_cfg[0] (signal_cfg_router);
557
558	///////////////////////////////////// MEMC
559	memc->p_clk (this->p_clk);
560	memc->p_resetn (this->p_resetn);
561	memc->p_vci_ixr (signal_ram_vci_ini_memc);
562	memc->p_vci_tgt (signal_int_vci_tgt_memc);
563	memc->p_dspin_p2m (signal_int_dspin_p2m_memc);
564	memc->p_dspin_m2p (signal_int_dspin_m2p_memc);
565	memc->p_dspin_clack (signal_int_dspin_clack_memc);
566	memc->p_irq (signal_irq_memc);
567
568	// wrapper to RAM network
569	memc_ram_wi->p_clk (this->p_clk);
570	memc_ram_wi->p_resetn (this->p_resetn);
571	memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i);
572	memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i);
573	memc_ram_wi->p_vci (signal_ram_vci_ini_memc);
574
575	//////////////////////////////////// XRAM
576	xram->p_clk (this->p_clk);
577	xram->p_resetn (this->p_resetn);
578	xram->p_vci (signal_ram_vci_tgt_xram);
579
580	// wrapper to RAM network
581	xram_ram_wt->p_clk (this->p_clk);
582	xram_ram_wt->p_resetn (this->p_resetn);
583	xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t);
584	xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t);
585	xram_ram_wt->p_vci (signal_ram_vci_tgt_xram);
586
587	/////////////////////////////////// MDMA
588	mdma->p_clk (this->p_clk);
589	mdma->p_resetn (this->p_resetn);
590	mdma->p_vci_target (signal_int_vci_tgt_mdma);
591	mdma->p_vci_initiator (signal_int_vci_ini_mdma);
592	for (size_t i=0 ; i<nb_dmas ; i++)
593	mdma->p_irq[i] (signal_irq_mdma[i]);
594
595	/////////////////////////////////// BROM
596	brom->p_clk (this->p_clk);
597	brom->p_resetn (this->p_resetn);
598	brom->p_vci (signal_int_vci_tgt_brom);
599
600	//////////////////////////// RAM network CMD & RSP routers
601	ram_router_cmd->p_clk (this->p_clk);
602	ram_router_cmd->p_resetn (this->p_resetn);
603	ram_router_rsp->p_clk (this->p_clk);
604	ram_router_rsp->p_resetn (this->p_resetn);
605	for( size_t n=0 ; n<4 ; n++)
606	{
607	ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]);
608	ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]);
609	ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]);
610	ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]);
611	}
612
613	ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t);
614	ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t);
615
616	if ( is_io )
617	{
618	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar);
619	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar);
620	}
621	else
622	{
623	ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);
624	ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);
625	}
626
627	///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1.
628	if ( is_io )
629	{
630	// IO bridge
631	iob->p_clk (this->p_clk);
632	iob->p_resetn (this->p_resetn);
633	iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));
634	iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));
635	iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);
636	iob->p_vci_ini_int (signal_int_vci_ini_iobx);
637	iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);
638
639	// initiator wrapper to RAM network
640	iob_ram_wi->p_clk (this->p_clk);
641	iob_ram_wi->p_resetn (this->p_resetn);
642	iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i);
643	iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i);
644	iob_ram_wi->p_vci (signal_ram_vci_ini_iobx);
645
646	// crossbar between MEMC and IOB to RAM network
647	ram_xbar_cmd->p_clk (this->p_clk);
648	ram_xbar_cmd->p_resetn (this->p_resetn);
649	ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar);
650	ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false);
651	ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i);
652	ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i);
653
654	ram_xbar_rsp->p_clk (this->p_clk);
655	ram_xbar_rsp->p_resetn (this->p_resetn);
656	ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false);
657	ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar);
658	ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
659	ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
660	}
661
662	SC_METHOD(init);
663
664	} // end constructor
665
666	tmpl(void)::init()
667	{
668	signal_ram_dspin_cmd_false.write = false;
669	signal_ram_dspin_rsp_false.read = true;
670	} // end init
671
672	tmpl(/**/)::~TsarIobCluster()
673	{
674	for (int k = 0; k < 3; k++)
675	{
676	delete int_router_cmd[k];
677	}
678	delete [] int_router_cmd;
679
680	for (int k = 0; k < 2; k++)
681	{
682	delete int_router_rsp[k];
683	}
684	delete [] int_router_rsp;
685	}
686
687	}}
688
689
690	// Local Variables:
691	// tab-width: 4
692	// c-basic-offset: 4
693	// c-file-offsets:((innamespace . 0)(inline-open . 0))
694	// indent-tabs-mode: nil
695	// End:
696
697	// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
698

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Project-Id-Version: Trac 0.12
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POT-Creation-Date: 2018-07-07 16:55+0000
PO-Revision-Date: 2010-07-19 23:05+0200
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